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| revision date: mar. 15 , 2007 32 renesas 32-bit risc microcomputer superh tm risc engine family / sh7619 series sh7619 r4s76190 rev.5.00 rej09b0237-0500 sh7619 group hardware manual
rev. 5.00 mar. 15, 2007 page ii of xxxviii rev. 5.00 mar. 15, 2007 page iii of xxxviii 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials rev. 5.00 mar. 15, 2007 page iv of xxxviii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed. rev. 5.00 mar. 15, 2007 page v of xxxviii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index rev. 5.00 mar. 15, 2007 page vi of xxxviii preface the sh7619 group risc (reduced instruction set computer) microcomputers include a renesas technology-original risc cpu as its core, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using the sh/7619 in the design of application systems. target users are expected to understand the fundamentals of electrical circuits, logical ci rcuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the sh/7619 to the target users. refer to the sh-1/sh-2/sh-dsp software manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the sh-1/sh-2/sh-d sp software manual. ? in order to understand the details of a register when its name is known the addresses, bits, and initial values of the re gisters are summarized in section 23, list of registers. examples: register name: the following notation is used fo r cases when the same or a similar function, e.g. 16-bit timer pulse unit or serial communication interface, is im plemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. number notation: binary is b'xxxx, hexadecimal is h'xxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ rev. 5.00 mar. 15, 2007 page vii of xxxviii sh/7619 group manuals: document title document no. sh/7619 group hardware manual this manual sh-1/sh-2/sh-dsp software manual rej09b0171 user's manuals for development tools: document title document no. superh tm risc engine c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0152 superh risc engine high-performance embedded workshop 3 user's manual rej10b0025 superh risc engine high-performance embedded workshop 3 tutorial rej10b0023 application note: document title document no. superh risc engine c/c++ compiler rej05b0463 rev. 5.00 mar. 15, 2007 page viii of xxxviii rev. 5.00 mar. 15, 2007 page ix of xxxviii contents section 1 overview..................................................................................................1 1.1 features....................................................................................................................... .......... 2 1.2 block diagram.................................................................................................................. .... 7 1.3 pin assign ments ................................................................................................................ ... 8 1.4 pin functions .................................................................................................................. ...... 9 section 2 cpu........................................................................................................23 2.1 features....................................................................................................................... ........ 23 2.2 register conf iguratio n........................................................................................................ 2 3 2.2.1 general regist ers (rn)........................................................................................ 25 2.2.2 control registers ................................................................................................ 25 2.2.3 system registers................................................................................................. 26 2.2.4 initial values of registers................................................................................... 27 2.3 data formats................................................................................................................... .... 28 2.3.1 register data format .......................................................................................... 28 2.3.2 memory data formats ........................................................................................ 28 2.3.3 immediate data formats..................................................................................... 29 2.4 features of instructions....................................................................................................... 29 2.4.1 risc type .......................................................................................................... 29 2.4.2 addressing modes .............................................................................................. 32 2.4.3 instruction formats ............................................................................................. 35 2.5 instruction set ................................................................................................................ ..... 39 2.5.1 instruction set by type....................................................................................... 39 2.6 processing states.............................................................................................................. ... 51 2.6.1 state tran sition ................................................................................................... 51 section 3 cache .....................................................................................................53 3.1 features....................................................................................................................... ........ 53 3.1.1 cache stru cture................................................................................................... 53 3.1.2 divided areas and cache.................................................................................... 55 3.2 register de scriptions.......................................................................................................... 56 3.2.1 cache control regi ster 1 (ccr1) ...................................................................... 56 3.3 operation ...................................................................................................................... ...... 57 3.3.1 searching cache ................................................................................................. 57 3.3.2 read a ccess........................................................................................................ 58 3.3.3 write access ....................................................................................................... 59 rev. 5.00 mar. 15, 2007 page x of xxxviii 3.3.4 write-back buffer .............................................................................................. 59 3.3.5 coherency of cache and external memory........................................................ 59 3.4 memory-mappe d cache ..................................................................................................... 60 3.4.1 address array..................................................................................................... 60 3.4.2 data array .......................................................................................................... 61 3.4.3 usage examples.................................................................................................. 63 section 4 u memory ............................................................................................. 65 4.1 features....................................................................................................................... ........ 65 4.2 usage notes .................................................................................................................... .... 65 section 5 exception handling ............................................................................... 67 5.1 overview ....................................................................................................................... ..... 67 5.1.1 types of exception ha ndling and pr iority ......................................................... 67 5.1.2 exception handlin g operations.......................................................................... 68 5.1.3 exception handling vector table ...................................................................... 69 5.2 resets......................................................................................................................... ......... 71 5.2.1 types of resets................................................................................................... 71 5.2.2 power-on reset .................................................................................................. 71 5.2.3 h-udi reset ....................................................................................................... 72 5.3 address errors ................................................................................................................. ... 73 5.3.1 address error sources ........................................................................................ 73 5.3.2 address error exce ption source......................................................................... 73 5.4 interrupts..................................................................................................................... ........ 74 5.4.1 interrupt sources................................................................................................. 74 5.4.2 interrupt priority ................................................................................................. 75 5.4.3 interrupt excep tion handling ............................................................................. 75 5.5 exceptions triggered by instructions ................................................................................. 76 5.5.1 types of exceptions trig gered by instructions .................................................. 76 5.5.2 trap instructions................................................................................................. 76 5.5.3 illegal slot in structions....................................................................................... 77 5.5.4 general illegal instructions................................................................................. 77 5.6 cases when exceptions are accepted................................................................................. 78 5.7 stack states after exce ption handling ends....................................................................... 79 5.8 usage notes .................................................................................................................... .... 81 5.8.1 value of stack pointer (sp) ................................................................................ 81 5.8.2 value of vector base register (vbr)................................................................ 81 5.8.3 address errors caused by stacking fo r address error exception handling...... 81 5.8.4 notes on slot illegal instru ction exception handling ........................................ 81 rev. 5.00 mar. 15, 2007 page xi of xxxviii section 6 interrupt controller (intc) ...................................................................83 6.1 features....................................................................................................................... ........ 83 6.2 input/output pins.............................................................................................................. .. 85 6.3 register de scriptions.......................................................................................................... 85 6.3.1 interrupt control re gister 0 (icr0).................................................................... 86 6.3.2 irq control register (irqcr) .......................................................................... 87 6.3.3 irq status regi ster (irqsr) .............................................................................. 90 6.3.4 interrupt priority registers a to g (ipra to iprg)........................................... 95 6.4 interrupt sources.............................................................................................................. ... 97 6.4.1 external interrupts .............................................................................................. 97 6.4.2 on-chip peripheral mo dule interrupts ............................................................... 99 6.4.3 user break interrupt ........................................................................................... 99 6.4.4 h-udi interrupt .................................................................................................. 99 6.5 interrupt exception hand ling vector table...................................................................... 100 6.6 interrupt op eration ........................................................................................................... 1 02 6.6.1 interrupt sequence ............................................................................................ 102 6.6.2 stack after interrupt ex ception hand ling ......................................................... 104 6.7 interrupt respon se time................................................................................................... 104 section 7 bus state controller (bsc)..................................................................107 7.1 features....................................................................................................................... ...... 107 7.2 input/output pins.............................................................................................................. 110 7.3 area overview.................................................................................................................. 111 7.3.1 area division.................................................................................................... 111 7.3.2 shadow area..................................................................................................... 112 7.3.3 address ma p ..................................................................................................... 112 7.3.4 area 0 memory type and memory bus width ................................................ 114 7.3.5 data alignment................................................................................................. 114 7.4 register desc riptions........................................................................................................ 11 5 7.4.1 common control regi ster (cmn cr) .............................................................. 116 7.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5b, 6b) ............... 117 7.4.3 csn space wait control register (csnw cr) (n = 0, 3, 4, 5b, 6b) ................ 122 7.4.4 sdram control regi ster (sd cr)................................................................... 138 7.4.5 refresh timer control/statu s register (r tcsr)............................................. 139 7.4.6 refresh timer coun ter (rtcnt)..................................................................... 141 7.4.7 refresh time constant register (rtcor) ...................................................... 142 7.5 operation ...................................................................................................................... .... 143 7.5.1 endian/access size and da ta alignment.......................................................... 143 7.5.2 normal space interface..................................................................................... 149 7.5.3 access wait control ......................................................................................... 154 rev. 5.00 mar. 15, 2007 page xii of xxxviii 7.5.4 extension of chip select ( csn ) assertion period............................................. 156 7.5.5 sdram interface ............................................................................................. 157 7.5.6 byte-selection sram interface ....................................................................... 186 7.5.7 pcmcia inte rface............................................................................................ 191 7.5.8 wait between a ccess cycl es ............................................................................ 198 7.5.9 others................................................................................................................ 198 section 8 clock pulse generator (cpg) ............................................................. 201 8.1 features....................................................................................................................... ...... 201 8.2 input/output pins.............................................................................................................. 204 8.3 clock operating modes .................................................................................................... 204 8.4 register desc riptions........................................................................................................ 20 6 8.4.1 frequency control re gister (f rqcr) ............................................................. 206 8.4.2 phy clock frequency contro l register (m clkcr) ...................................... 208 8.4.3 usage notes ...................................................................................................... 209 8.5 changing frequency ......................................................................................................... 210 8.5.1 changing multipli cation ra tio ......................................................................... 210 8.5.2 changing divisi on ratio .................................................................................. 211 8.5.3 changing clock op erating mode ..................................................................... 211 8.6 notes on boar d design ..................................................................................................... 213 section 9 watchdog timer (wdt) ..................................................................... 215 9.1 features....................................................................................................................... ...... 215 9.2 register desc riptions........................................................................................................ 21 7 9.2.1 watchdog timer coun ter (wtcnt)................................................................ 217 9.2.2 watchdog timer control/statu s register (wtcsr)........................................ 217 9.2.3 notes on regist er access ................................................................................. 219 9.3 wdt operation ................................................................................................................ 22 0 9.3.1 canceling software standbys ........................................................................... 220 9.3.2 changing frequency ......................................................................................... 221 9.3.3 using watchdog ti mer mode .......................................................................... 221 9.3.4 using interval timer mode .............................................................................. 222 9.4 usage notes .................................................................................................................... .. 222 section 10 power-down modes.......................................................................... 223 10.1 features....................................................................................................................... ...... 223 10.1.1 types of power-down modes .......................................................................... 223 10.2 input/output pins.............................................................................................................. 224 10.3 register desc riptions........................................................................................................ 22 4 10.3.1 standby control regi ster (st bcr).................................................................. 225 rev. 5.00 mar. 15, 2007 page xiii of xxxviii 10.3.2 standby control regist er 2 (st bcr2)............................................................. 226 10.3.3 standby control regist er 3 (st bcr3)............................................................. 227 10.3.4 standby control regist er 4 (st bcr4)............................................................. 228 10.4 sleep mode ..................................................................................................................... .. 229 10.4.1 transition to sl eep mode.................................................................................. 229 10.4.2 canceling slee p mode ...................................................................................... 229 10.5 software sta ndby mode.................................................................................................... 230 10.5.1 transition to software standby mode .............................................................. 230 10.5.2 canceling software standby m ode................................................................... 231 10.6 module standby mode...................................................................................................... 232 10.6.1 transition to module standby mode ................................................................ 232 10.6.2 canceling module stan dby function................................................................ 232 section 11 ethernet controller (etherc)..............................................................233 11.1 features....................................................................................................................... ...... 233 11.2 input/output pins.............................................................................................................. 235 11.3 register desc ription ......................................................................................................... 23 7 11.3.1 etherc mode regi ster (ecm r)........................................................................ 238 11.3.2 etherc status regi ster (ecsr)......................................................................... 241 11.3.3 etherc interrupt permission register (e csipr) .............................................. 243 11.3.4 phy interface regist er (pir) ........................................................................... 244 11.3.5 mac address high re gister (m ahr)............................................................. 245 11.3.6 mac address low regi ster (malr).............................................................. 245 11.3.7 receive frame length register (rflr) .......................................................... 246 11.3.8 phy status regist er (psr)............................................................................... 247 11.3.9 transmit retry over counter register (trocr) ............................................ 247 11.3.10 delayed collision detect coun ter register (cdcr)........................................ 248 11.3.11 lost carrier counter register (lccr) ............................................................. 248 11.3.12 carrier not detect counte r register (cndcr) ............................................... 248 11.3.13 crc error frame counter re gister (cef cr).................................................. 249 11.3.14 frame receive error counte r register (frecr) ............................................. 249 11.3.15 too-short frame receive count er register (tsfrcr)................................... 249 11.3.16 too-long frame receive count er register (tlfrcr)................................... 250 11.3.17 residual-bit frame counte r register (rfcr) ................................................. 250 11.3.18 multicast address frame coun ter register (mafcr)..................................... 250 11.3.19 ipg register (ipgr) ......................................................................................... 251 11.3.20 automatic pause frame se t register (apr) ................................................. 251 11.3.21 manual pause frame set register (mpr) ..................................................... 252 11.3.22 pause frame retransfer count set register (t pauser)............................. 252 11.4 operation ...................................................................................................................... .... 253 rev. 5.00 mar. 15, 2007 page xiv of xxxviii 11.4.1 transmissi on..................................................................................................... 253 11.4.2 reception .......................................................................................................... 255 11.4.3 mii frame timing ............................................................................................ 256 11.4.4 accessing mii re gisters................................................................................... 258 11.4.5 magic packet de tection .................................................................................... 261 11.4.6 operation by ip g setting.................................................................................. 262 11.4.7 flow cont rol..................................................................................................... 262 11.5 connection to phy-lsi.................................................................................................... 263 11.6 usage notes .................................................................................................................... .. 264 section 12 ethernet controller d irect memory access controller (e-dmac)........................................................................................ 265 12.1 features....................................................................................................................... ...... 265 12.2 register desc riptions........................................................................................................ 26 6 12.2.1 e-dmac mode regi ster (edm r) ................................................................... 267 12.2.2 e-dmac transmit request register (e dtrr) .............................................. 268 12.2.3 e-dmac receive request register (edrrr)................................................ 269 12.2.4 transmit descriptor list addr ess register (tdlar)...................................... 270 12.2.5 receive descriptor list addr ess register (rdlar) ....................................... 270 12.2.6 etherc/e-dmac status register (e esr)........................................................ 271 12.2.7 etherc/e-dmac status interrupt pe rmission register (eesipr)................... 276 12.2.8 transmit/receive status copy en able register (trscer)............................. 279 12.2.9 receive missed-frame counte r register (rmfcr) ........................................ 281 12.2.10 transmit fifo threshold register (tftr)...................................................... 282 12.2.11 fifo depth regist er (fdr) ............................................................................. 283 12.2.12 receiving method contro l register (rmcr) .................................................. 284 12.2.13 e-dmac operation contro l register (edocr) ............................................. 285 12.2.14 receiving-buffer write addre ss register (rbwar) ...................................... 286 12.2.15 receiving-descriptor fetch addr ess register (rdfar) ................................. 286 12.2.16 transmission-buffer read ad dress register (tbrar)................................... 286 12.2.17 transmission-descriptor fetch a ddress register (tdfar) ............................ 287 12.2.18 flow control fifo threshol d register (fcftr) ............................................ 287 12.2.19 transmit interrupt regi ster (trimd) .............................................................. 288 12.3 operation ...................................................................................................................... .... 289 12.3.1 descriptor list and data buffers ...................................................................... 289 12.3.2 transmissi on..................................................................................................... 298 12.3.3 reception .......................................................................................................... 300 12.3.4 multi-buffer fram e transmit/receive processing ........................................... 302 rev. 5.00 mar. 15, 2007 page xv of xxxviii 12.4 usage notes .................................................................................................................... .. 304 12.4.1 usage notes on sh-ether etherc/e-d mac status register (eesr).............. 304 12.4.2 usage notes on sh-ether transmit-fifo underflow...................................... 313 section 13 direct memory access controller (dmac) .....................................323 13.1 features....................................................................................................................... ...... 323 13.2 input/output pins.............................................................................................................. 325 13.3 register desc riptions........................................................................................................ 32 6 13.3.1 dma source address registers 0 to 3 (sar_0 to sar_3) ............................. 327 13.3.2 dma destination address registers 0 to 3 (dar_0 to dar_3) .................... 327 13.3.3 dma transfer count registers 0 to 3 (dmatcr_0 to dmatcr_3) ........... 327 13.3.4 dma channel control registers 0 to 3 (chcr_0 to chcr_3)...................... 328 13.3.5 dma operation regist er (dmaor) ............................................................... 333 13.3.6 dma extended resource selectors 0 and 1 (dmars0 and dmars1) ......... 335 13.4 operation ...................................................................................................................... .... 337 13.4.1 dma transfer flow ......................................................................................... 337 13.4.2 dma transfer requests ................................................................................... 339 13.4.3 channel prio rity................................................................................................ 341 13.4.4 dma transfer types........................................................................................ 344 13.4.5 number of bus cycle states and dreq pin sampli ng timing ....................... 353 13.5 usage notes .................................................................................................................... .. 357 13.5.1 notes on dack pin output ............................................................................. 357 13.5.2 notes on dreq sampling when dack is divided in external access ........ 358 13.5.3 other notes ....................................................................................................... 361 section 14 compare match timer (cmt) ..........................................................363 14.1 features....................................................................................................................... ...... 363 14.2 register desc riptions........................................................................................................ 36 4 14.2.1 compare match timer start register (c mstr) .............................................. 364 14.2.2 compare match timer control/sta tus register (cmcsr) .............................. 365 14.2.3 compare match coun ter (cmcnt) ................................................................. 366 14.2.4 compare match constant register (c mcor) ................................................. 366 14.3 operation ...................................................................................................................... .... 367 14.3.1 interval count operation .................................................................................. 367 14.3.2 cmcnt count timing..................................................................................... 367 14.4 interrupts..................................................................................................................... ...... 368 14.4.1 interrupt sources............................................................................................... 368 14.4.2 timing of setting comp are match flag ........................................................... 368 14.4.3 timing of clearing co mpare match flag......................................................... 368 14.5 usage notes .................................................................................................................... .. 369 rev. 5.00 mar. 15, 2007 page xvi of xxxviii 14.5.1 conflict between write and compare- match processes of cmcnt ............... 369 14.5.2 conflict between word-write and count-up processes of cmcnt ............... 370 14.5.3 conflict between byte-write and c ount-up processes of cmcnt................. 371 14.5.4 conflict between write processes to cmcnt with the counting stopped and cmco r ..................................................................................................... 371 section 15 serial communication in terface with fifo (scif).......................... 373 15.1 overview ....................................................................................................................... ... 373 15.1.1 features............................................................................................................. 373 15.2 pin config uration.............................................................................................................. 376 15.3 register desc ription ......................................................................................................... 37 7 15.3.1 receive shift regi ster (scrs r) ...................................................................... 378 15.3.2 receive fifo data re gister (scf rdr) .......................................................... 378 15.3.3 transmit shift regist er (sctsr) ..................................................................... 378 15.3.4 transmit fifo data re gister (scftdr)......................................................... 379 15.3.5 serial mode regist er (scsmr)........................................................................ 379 15.3.6 serial control regi ster (scs cr)...................................................................... 382 15.3.7 serial status regi ster (scfsr) ........................................................................ 386 15.3.8 bit rate regist er (scbrr) .............................................................................. 394 15.3.9 fifo control regi ster (scf cr) ...................................................................... 401 15.3.10 fifo data count regi ster (scfdr)................................................................ 404 15.3.11 serial port regist er (scsptr) ......................................................................... 405 15.3.12 line status regist er (sclsr) .......................................................................... 409 15.4 operation ...................................................................................................................... .... 410 15.4.1 overview .......................................................................................................... 410 15.4.2 operation in asynch ronous mode .................................................................... 412 15.4.3 synchronous mode ........................................................................................... 423 15.5 scif inte rrupts ................................................................................................................ .431 15.6 serial port register (scs ptr) and scif pins ................................................................. 432 15.7 usage notes .................................................................................................................... .. 436 section 16 serial i/o with fifo (siof) ............................................................. 441 16.1 features....................................................................................................................... ...... 441 16.2 input/output pins.............................................................................................................. 443 16.3 register desc riptions........................................................................................................ 44 4 16.3.1 mode register (simdr) .................................................................................. 445 16.3.2 control register (sictr)................................................................................. 448 16.3.3 transmit data regist er (sitdr) ...................................................................... 451 16.3.4 receive data regist er (sirdr) ....................................................................... 452 16.3.5 transmit control data re gister (sitcr) ......................................................... 453 rev. 5.00 mar. 15, 2007 page xvii of xxxviii 16.3.6 receive control data register (s ircr)........................................................... 454 16.3.7 status register (sistr).................................................................................... 455 16.3.8 interrupt enable regi ster (siier)..................................................................... 461 16.3.9 fifo control regist er (sifctr) ..................................................................... 463 16.3.10 clock select regi ster (sis cr) ......................................................................... 465 16.3.11 transmit data assign re gister (sitdar) ....................................................... 466 16.3.12 receive data assign re gister (sirdar)......................................................... 468 16.3.13 control data assign re gister (sicdar) ......................................................... 469 16.3.14 spi control regist er (spicr) .......................................................................... 470 16.4 operation ...................................................................................................................... .... 473 16.4.1 serial cl ocks ..................................................................................................... 473 16.4.2 serial ti ming .................................................................................................... 474 16.4.3 transfer data format........................................................................................ 475 16.4.4 register allocation of transfer data ................................................................ 477 16.4.5 control data interface....................................................................................... 479 16.4.6 fifo.................................................................................................................. 481 16.4.7 transmit and receive procedures..................................................................... 483 16.4.8 interrupts........................................................................................................... 488 16.4.9 transmit and recei ve timi ng........................................................................... 490 16.4.10 spi mode .......................................................................................................... 494 section 17 host interface (hif)...........................................................................503 17.1 features....................................................................................................................... ...... 503 17.2 input/output pins.............................................................................................................. 505 17.3 parallel access................................................................................................................ .. 506 17.3.1 operation .......................................................................................................... 506 17.3.2 connection me thod........................................................................................... 506 17.4 register desc riptions........................................................................................................ 50 7 17.4.1 hif index register (hifidx)........................................................................... 507 17.4.2 hif general status re gister (hif gsr)............................................................ 510 17.4.3 hif status/control re gister (hifscr) ............................................................ 510 17.4.4 hif memory control re gister (hif mcr) ....................................................... 513 17.4.5 hif internal interrupt cont rol register (hifiicr) .......................................... 515 17.4.6 hif external interrupt cont rol register (hifeicr) ........................................ 515 17.4.7 hif address regist er (hifadr) ..................................................................... 516 17.4.8 hif data register (hifdata) ........................................................................ 517 17.4.9 hif boot control re gister (h ifbcr).............................................................. 517 17.4.10 hifdreq trigger register (hifdtr) ............................................................ 518 17.4.11 hif bank interrupt contro l register (h ifbicr) ............................................. 519 17.5 memory map .................................................................................................................... 5 21 rev. 5.00 mar. 15, 2007 page xviii of xxxviii 17.6 interface (b asic).............................................................................................................. .. 522 17.7 interface (d etails) ............................................................................................................ .523 17.7.1 hifidx write/hi fgsr read .......................................................................... 523 17.7.2 reading/writing of hif registers ot her than hifidx and hifgsr............... 523 17.7.3 consecutive data writing to hifr am by external device............................. 524 17.7.4 consecutive data reading from hi fram to external device ........................ 524 17.8 external dmac interface................................................................................................. 525 17.9 alignment co ntrol ............................................................................................................ 53 1 17.10 interface when external devi ce power is cu t off........................................................... 532 section 18 pin function controller (pfc) .......................................................... 535 18.1 register desc riptions........................................................................................................ 54 5 18.1.1 port a io register h (paiorh) ...................................................................... 546 18.1.2 port a control register h1 an d h2 (pacrh1 an d pacrh2) ........................ 546 18.1.3 port b io register l (pbiorl) ....................................................................... 549 18.1.4 port b control register l1 and l2 (pbcrl1 an d pbcrl2)........................... 549 18.1.5 port c io register h and l (pciorh and pciorl) ...................................... 553 18.1.6 port c control register h2, l1, and l2 (pccrh2, pccrl1, and pccrl2). 553 18.1.7 port d io register l (pdiorl)....................................................................... 558 18.1.8 port d control regist er l2 (pdcrl2)............................................................. 559 18.1.9 port e io register h and l (peiorh and peiorl) ....................................... 561 18.1.10 port e control register h1, h2, l1 , and l2 (pecrh1, pecrh2, pecrl1, and pecrl2) .................................................................................................... 561 section 19 i/o ports............................................................................................. 569 19.1 port a......................................................................................................................... ....... 569 19.1.1 register desc ription ......................................................................................... 569 19.1.2 port a data regist er h (padrh) .................................................................... 569 19.2 port b......................................................................................................................... ....... 571 19.2.1 register desc ription ......................................................................................... 571 19.2.2 port b data regist er l (pbdrl) ..................................................................... 571 19.3 port c......................................................................................................................... ....... 573 19.3.1 register desc ription ......................................................................................... 574 19.3.2 port c data registers h an d l (pcdrh and pcdrl) .................................... 574 19.4 port d......................................................................................................................... ....... 576 19.4.1 register desc ription ......................................................................................... 576 19.4.2 port d data regist er l (pddrl)..................................................................... 576 rev. 5.00 mar. 15, 2007 page xix of xxxviii 19.5 port e ......................................................................................................................... ....... 578 19.5.1 register desc ription ......................................................................................... 579 19.5.2 port e data registers h an d l (pedrh and pedrl) ..................................... 579 19.6 usage notes .................................................................................................................... .. 581 section 20 user break controller (ubc) ............................................................583 20.1 features....................................................................................................................... ...... 583 20.2 register desc riptions........................................................................................................ 58 5 20.2.1 break address regist er a (bara) .................................................................. 585 20.2.2 break address mask regi ster a (bamra)..................................................... 586 20.2.3 break bus cycle regi ster a ( bbra)............................................................... 586 20.2.4 break address regist er b (barb) .................................................................. 587 20.2.5 break address mask re gister b (b amrb) ..................................................... 588 20.2.6 break data regist er b (bdrb) ........................................................................ 588 20.2.7 break data mask regi ster b (b dmrb)........................................................... 589 20.2.8 break bus cycle regi ster b ( bbrb) ............................................................... 589 20.2.9 break control regi ster (brc r) ....................................................................... 591 20.2.10 execution times break register (betr)......................................................... 594 20.2.11 branch source regi ster (brs r)....................................................................... 594 20.2.12 branch destination re gister (brdr)............................................................... 595 20.3 operation ...................................................................................................................... .... 596 20.3.1 flow of user break operatio n .......................................................................... 596 20.3.2 break on instructio n fetch cy cle...................................................................... 597 20.3.3 break on data a ccess cycle............................................................................. 597 20.3.4 sequential br eak ............................................................................................... 598 20.3.5 value of saved progra m counter (pc)............................................................. 598 20.3.6 pc trace ........................................................................................................... 599 20.3.7 usage examples................................................................................................ 600 20.3.8 notes ................................................................................................................. 604 section 21 user debugging interface (h-udi) ...................................................605 21.1 features....................................................................................................................... ...... 605 21.2 input/output pins.............................................................................................................. 606 21.3 register desc riptions........................................................................................................ 60 7 21.3.1 bypass register (sdbpr) ................................................................................ 607 21.3.2 instruction regist er (sdir) .............................................................................. 607 21.3.3 boundary scan regist er (sdbsr) ................................................................... 608 21.3.4 id register (sdid)........................................................................................... 615 21.4 operation ...................................................................................................................... .... 616 21.4.1 tap controller ................................................................................................. 616 rev. 5.00 mar. 15, 2007 page xx of xxxviii 21.4.2 reset configur ation .......................................................................................... 617 21.4.3 tdo output timing ......................................................................................... 617 21.4.4 h-udi reset ..................................................................................................... 618 21.4.5 h-udi interrupt ................................................................................................ 618 21.5 boundary scan.................................................................................................................. 619 21.5.1 supported inst ructions ...................................................................................... 619 21.5.2 points for a ttention........................................................................................... 620 21.6 usage notes .................................................................................................................... .. 620 section 22 ethernet physical layer transceiver (phy) ..................................... 621 22.1 features....................................................................................................................... ...... 621 22.2 pin config uration.............................................................................................................. 623 22.3 top level functional architecture................................................................................... 624 22.4 phy management control ............................................................................................... 625 22.4.1 serial management interface (s mi) ................................................................. 625 22.4.2 smi register mapping...................................................................................... 632 22.5 100base-tx tr ansmit....................................................................................................... 638 22.6 100base-tx receive ........................................................................................................ 641 22.7 10base-t tran smit ........................................................................................................... 644 22.8 10base-t receive............................................................................................................. 64 6 22.9 mac inte rface .................................................................................................................. 647 22.10 miscellaneous functions................................................................................................... 651 22.11 internal i/ o signals........................................................................................................... 655 22.12 signals relevant to phy-if ............................................................................................. 657 22.13 usage notes .................................................................................................................... .. 658 22.14 guidelines fo r layout ....................................................................................................... 662 22.14.1 general guidelines ........................................................................................... 662 22.14.2 guidelines for layout ....................................................................................... 663 section 23 phy interface (phy-if) ................................................................... 667 23.1 features....................................................................................................................... ...... 667 23.2 register desc riptions........................................................................................................ 66 9 23.2.1 phy-if control regi ster (phyifcr).............................................................. 669 23.2.2 phy -if smi register 2 (phyifsmir2) ......................................................... 670 23.2.3 phy -if smi register 3 (phyifsmir3) ......................................................... 671 23.2.4 phy -if address register (phyifaddrr) .................................................... 671 23.2.5 phy-if status regi ster (phyifsr) ................................................................. 672 23.3 phy-if operation ............................................................................................................ 673 23.3.1 the procedures of setting up the on-chip phy ............................................. 673 23.3.2 the procedures of set up the external phy lsi ............................................. 674 rev. 5.00 mar. 15, 2007 page xxi of xxxviii section 24 list of registers .................................................................................675 24.1 register addresses (a ddress order)................................................................................. 676 24.2 register bits.................................................................................................................. .... 684 24.3 register states in each processing state .......................................................................... 706 section 25 electrical characteristics ...................................................................713 25.1 absolute maximum ratings ............................................................................................. 713 25.2 power-on and powe r-off orde r ....................................................................................... 714 25.3 dc character istics ............................................................................................................ 7 16 25.4 ac character istics ............................................................................................................ 7 18 25.4.1 clock timing .................................................................................................... 719 25.4.2 control signal timing ...................................................................................... 723 25.4.3 ac bus ti ming................................................................................................. 725 25.4.4 basic timi ng..................................................................................................... 727 25.4.5 synchronous dram timing ............................................................................ 733 25.4.6 pcmcia timing .............................................................................................. 750 25.4.7 dmac signal timing....................................................................................... 754 25.4.8 scif timi ng ..................................................................................................... 755 25.4.9 siof module si gnal timi ng ............................................................................ 756 25.4.10 port timi ng ....................................................................................................... 760 25.4.11 hif timi ng ....................................................................................................... 761 25.4.12 etherc timing .................................................................................................. 764 25.4.13 h-udi related pi n timing............................................................................... 767 25.4.14 ac characteristic te st conditions ................................................................... 769 25.5 physical layer ttransceiver (phy) char acteristics (refer ence values).......................... 770 appendix..............................................................................................................771 a. port states in e ach pin state............................................................................................. 771 b. product code lineup ........................................................................................................ 776 c. package dime nsions ......................................................................................................... 777 main revisions and additions in this edition .....................................................779 index ....................................................................................................................787 rev. 5.00 mar. 15, 2007 page xxii of xxxviii rev. 5.00 mar. 15, 2007 page xxiii of xxxviii figures section 1 overview figure 1.1 block di agram ..................................................................................................... ......... 7 figure 1.2 pin assignments ................................................................................................... ......... 8 section 2 cpu figure 2.1 cpu internal register conf iguration .......................................................................... 24 figure 2.2 regi ster data format.............................................................................................. ..... 28 figure 2.3 memo ry data format ................................................................................................ .. 28 figure 2.4 cpu state tran sition.............................................................................................. ..... 51 section 3 cache figure 3.1 cache structure ................................................................................................... ........ 53 figure 3.2 cache search scheme ............................................................................................... .. 58 figure 3.3 write-back buffer config uration................................................................................ 59 figure 3.4 specifying address and data for memo ry-mapped cache access............................. 62 section 6 interrupt controller (intc) figure 6.1 intc block diagram ................................................................................................ .. 84 figure 6.2 block diagram of ir q7 to irq0 inte rrupts control................................................... 98 figure 6.3 interrupt sequence flowchart.................................................................................... 10 3 figure 6.4 stack after in terrupt exception handling .................................................................. 104 section 7 bus state controller (bsc) figure 7.1 bloc k diagram of bsc.............................................................................................. 109 figure 7.2 address space ..................................................................................................... ...... 112 figure 7.3 normal space basic access timing (no- wait access)............................................ 149 figure 7.4 consecutive access to normal space (1): bus width = 16 bits, longword access, csnwcr.wm = 0 (access wait = 0, cycle wa it = 0) ............................................ 150 figure 7.5 consecutive access to normal space (2): bus width = 16 bits, longword access, csnwcr.wm = 1 (access wait = 0, cycle wa it = 0) ............................................ 151 figure 7.6 example of 32-bit data-width sram connection .................................................. 152 figure 7.7 example of 16-bit data-width sram connection .................................................. 153 figure 7.8 example of 8-bit data-width sram connectio n.................................................... 153 figure 7.9 wait timing for normal space access (softwar e wait only ) ................................. 154 figure 7.10 wait cycle ti ming for normal space access | (wait cycle insertion using wait )........................................................................ 155 figure 7.11 example of timing when csn assertion period is extended ................................. 156 figure 7.12 example of 32-bit data-width sdram connection ............................................. 158 figure 7.13 example of 16-bit data-width sdram connection ............................................. 159 rev. 5.00 mar. 15, 2007 page xxiv of xxxviii figure 7.14 burst read ba sic timing (auto precharge) ............................................................ 170 figure 7.15 burst read wait speci fication timing (auto precharge) ....................................... 171 figure 7.16 basic timing for single read (auto precharge)..................................................... 172 figure 7.17 basic timing for burst write (auto precharge) ..................................................... 173 figure 7.18 basic timing for single write (auto- precharge).................................................... 174 figure 7.19 burst read ti ming (no auto precharge) ................................................................ 176 figure 7.20 burst read timing (bank active, same row address) ......................................... 177 figure 7.21 burst read timing (ban k active, different row addresses) ................................ 178 figure 7.22 single write ti ming (no auto precharge).............................................................. 179 figure 7.23 single write timing (b ank active, same row address)....................................... 180 figure 7.24 single write timing (ban k active, different row addresses).............................. 181 figure 7.25 auto -refreshing timing ......................................................................................... 18 2 figure 7.26 self-refreshing timing........................................................................................... 184 figure 7.27 write timing for sdram mode register (based on jedec)............................... 186 figure 7.28 basic access timing fo r byte-selection sram (bas = 0)................................... 187 figure 7.29 basic access timing fo r byte-selection sram (bas = 1)................................... 188 figure 7.30 wait timing for byte-selection sram (bas = 1) (software wait only)............. 189 figure 7.31 example of connection with 32-bit data-width byte-selection sram ............... 190 figure 7.32 example of connection with 16-bit data-width byte-selection sram ............... 190 figure 7.33 example of pc mcia interface connectio n............................................................ 192 figure 7.34 basic access timing fo r pcmcia memory ca rd interface................................... 193 figure 7.35 wait timing for pc mcia memory card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1)................................................................................................ 194 figure 7.36 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b'10, cs6bwcr.sa[1:0] = b'10) .................................................................................. 195 figure 7.37 basic timing for pcmcia i/o card interface ....................................................... 196 figure 7.38 wait timing for pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1) ............................... 197 figure 7.39 timing for dynamic bus si zing of pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b' 0001, software waits = 3) ............................ 197 section 8 clock pulse generator (cpg) figure 8.1 block diagram of cpg ............................................................................................. 2 02 figure 8.2 note on usin g a crystal re sonator ........................................................................... 213 figure 8.3 note on using a pll oscillator circuit .................................................................... 214 section 9 watchdog timer (wdt) figure 9.1 block diagram of wdt ............................................................................................ 21 6 figure 9.2 writing to wtcnt and wtcsr.............................................................................. 220 rev. 5.00 mar. 15, 2007 page xxv of xxxviii section 10 power-down modes figure 10.1 canceling standby mode with stby bit in st bcr.............................................. 232 section 11 ethernet controller (etherc) figure 11.1 conf iguration of etherc.......................................................................................... 234 figure 11.2 etherc tran smitter state tr ansitions ...................................................................... 254 figure 11.3 etherc recei ver state tran smissions...................................................................... 255 figure 11.4 (1) mii frame tran smit timing (normal transmission)........................................ 256 figure 11.4 (2) mii frame transmit timing (c ollision) ............................................................ 256 figure 11.4 (3) mii frame tr ansmit timing (transmit error)................................................... 257 figure 11.4 (4) mii frame r eceive timing (norma l reception)............................................... 257 figure 11.4 (5) mii frame recei ve timing (reception error (1 ))............................................. 257 figure 11.4 (6) mii fame recei ve timing (reception error (2)) .............................................. 257 figure 11.5 mii mana gement frame format ............................................................................. 258 figure 11.6 (1) 1-bit data write fl owchart ............................................................................... 259 figure 11.6 (2) bus release flowchar t (ta in read in figure 11.5) ......................................... 260 figure 11.6 (3) 1-bit data read flowchart ................................................................................ 260 figure 11.6 (4) independent bus release fl owchart (idle in write in figure 11.5)................ 261 figure 11.7 changing ipg and transmission efficiency ........................................................... 262 figure 11.8 example of connection to dp 83846avhg............................................................ 263 section 12 ethernet controller direct memory access controller (e-dmac) figure 12.1 configuration of e-dm ac, and descriptors and buffers....................................... 265 figure 12.2 relationship between transm it descriptor and transmit buffer ............................ 290 figure 12.3 relationship between recei ve descriptor and receive bu ffer ............................... 294 figure 12.4 sample tr ansmission fl owchart ............................................................................. 299 figure 12.5 sample reception flow chart................................................................................... 301 figure 12.6 e-dmac opera tion after transm it error ............................................................... 302 figure 12.7 e-dmac opera tion after receive error................................................................. 303 figure 12.8 timing of the case where setting of the interrupt source bit in eesr by the e-dmac fails ............................................................................................ 304 figure 12.9 countermeasure by monitoring the transmit descriptor in processing of interrupts other than the frame tran smit complete (tc) interrupt...................... 310 figure 12.10 method of ad ding timeout pr ocessing ................................................................. 312 figure 12.11 operation when e-dm ac stops and the transmit fifo ..................................... 314 figure 12.12 processing transmission without handling of the tc interrupt ........................... 317 figure 12.13 countermeasure for the case with tc interrupt-driven software: addition of timeout processing within the limit imposed by the maximum specified time. 320 rev. 5.00 mar. 15, 2007 page xxvi of xxxviii section 13 direct memory access controller (dmac) figure 13.1 block diagram of dmac ....................................................................................... 324 figure 13.2 dma transfer flowchart........................................................................................ 338 figure 13.3 round-robin mode................................................................................................. 342 figure 13.4 changes in channel priority in roun d-robin mode............................................... 343 figure 13.5 data flow of dual addr ess mode........................................................................... 345 figure 13.6 example of dma transfer timing in dual mode (source: ordinary memory, destin ation: ordinary memory) ............................... 346 figure 13.7 data flow in single addr ess mode......................................................................... 347 figure 13.8 example of dma transf er timing in single address mode ................................. 348 figure 13.9 dma transfer exampl e in cycle-steal normal mode (dual address, dreq lo w level det ection)........................................................ 349 figure 13.10 example of dma transfer in cycle steal intermittent mode (dual address, dreq lo w level det ection)..................................................... 350 figure 13.11 dma transfer example in burst mode (dual address, dreq lo w level det ection)..................................................... 350 figure 13.12 bus state when mu ltiple channels ar e operating................................................. 352 figure 13.13 example of dreq input detec tion in cycle steal mode edge detection............ 353 figure 13.14 example of dreq input detec tion in cycle steal mode level detection........... 353 figure 13.15 example of dreq input det ection in burst mode edge detection ..................... 354 figure 13.16 example of dreq input det ection in burst mode level detection .................... 354 figure 13.17 example of dma transfer en d in cycle steal mode level detection ................ 355 figure 13.18 example of bsc ordinary memory access (no wait, idle cycle 1, longwor d access to 16-b it device)............................. 356 figure 13.19 example of dreq input detection in cycle steal mode edge detection when dack is divided to 4 by idle cycles ........................................................ 358 figure 13.20 example of dreq input detection in cycle steal mode edge detection when dack is divided to 2 by idle cycles........................................................ 359 figure 13.21 example of dreq input det ection in cycle steal mo de level detection when dack is divided to 4 by idle cycles ........................................................ 359 figure 13.22 example of dreq input det ection in cycle steal mo de level detection when dack is divided to 2 by idle cycles ........................................................ 360 section 14 compare match timer (cmt) figure 14.1 block diagram of compare match timer............................................................... 363 figure 14.2 co unter operation ................................................................................................ ... 367 figure 14.3 count timing ..................................................................................................... ..... 367 figure 14.4 timi ng of cmf setting ........................................................................................... 3 68 figure 14.5 conflict between write an d compare-match proce sses of cmcnt...................... 369 figure 14.6 conflict between word-write and count-up proce sses of cmcnt...................... 370 rev. 5.00 mar. 15, 2007 page xxvii of xxxviii figure 14.7 conflict between byte-write and count-up proces ses of cmcnt ....................... 371 section 15 serial communication interface with fifo (scif) figure 15.1 bloc k diagram of scif........................................................................................... 3 75 figure 15.2 example of data format in asynchronous communication (8-bit data with parity and two stop bits) ........................................................... 412 figure 15.3 sample flowch art for scif in itializatio n ............................................................... 415 figure 15.4 sample flowchart for transmitting serial data...................................................... 416 figure 15.5 example of transmit opera tion (8-bit data, parity , one stop bit)........................ 418 figure 15.6 example of operation using modem control ( cts ).............................................. 418 figure 15.7 sample flowchart fo r receiving serial data (1)..................................................... 419 figure 15.8 sample flowchart fo r receiving serial data (2)..................................................... 420 figure 15.9 example of scif receive oper ation (8-bit data, parity , one stop bit)................ 422 figure 15.10 example of operation using modem control ( rts )............................................ 422 figure 15.11 data format in synchronous co mmunication ...................................................... 423 figure 15.12 sample flowch art for scif in itializati on.............................................................. 425 figure 15.13 sample flowchart for transmitting se rial data.................................................... 426 figure 15.14 example of sc if transmit operation................................................................... 427 figure 15.15 sample flowchart for receiving serial data (1)................................................... 428 figure 15.16 sample flowchart for receiving serial data (2)................................................... 428 figure 15.17 example of scif receive op eration .................................................................... 429 figure 15.18 sample flowchart for transmitting/receiving serial da ta................................... 430 figure 15.19 rtsio bit, rtsdt bit, and rts pin................................................................... 432 figure 15.20 ctsio bit, ctsdt bit, and cts pin................................................................... 433 figure 15.21 sckio bit, sckdt bit, and sck pin ................................................................. 434 figure 15.22 spbio bit, spbdt bit, and txd pin ................................................................... 434 figure 15.23 spbdt bit and rxd pin ....................................................................................... 435 figure 15.24 receive data sampli ng timing in asynchronous mode ...................................... 437 section 16 serial i/o with fifo (siof) figure 16.1 bloc k diagram of siof .......................................................................................... 44 2 figure 16.2 se rial cloc k supply.............................................................................................. ... 473 figure 16.3 serial data synchronizati on timing ....................................................................... 474 figure 16.4 siof tr ansmit/receive timing .............................................................................. 475 figure 16.5 transmit/receiv e data bit a lignment .................................................................... 477 figure 16.6 control data bit alig nment .................................................................................... 478 figure 16.7 control data interface (slot position) ..................................................................... 479 figure 16.8 control data interface (seconda ry fs) ................................................................... 480 figure 16.9 example of transm it operation in ma ster mode.................................................... 483 figure 16.10 example of receive operation in ma ster mode ................................................... 484 figure 16.11 example of tran smit operation in slave mode .................................................... 485 rev. 5.00 mar. 15, 2007 page xxviii of xxxviii figure 16.12 example of recei ve operation in slave m ode ..................................................... 486 figure 16.13 transmit and receive timing (8-bit monaur al data (1))..................................... 490 figure 16.14 transmit and receive timing (8-bit monaur al data (2))..................................... 490 figure 16.15 transmit and receive ti ming (16-bit monaur al data (1))................................... 491 figure 16.16 transmit and receive timing (16-bit ster eo data (1)) ........................................ 491 figure 16.17 transmit and receive timing (16-bit ster eo data (2)) ........................................ 492 figure 16.18 transmit and receive timing (16-bit ster eo data (3)) ........................................ 492 figure 16.19 transmit and receive timing (16-bit ster eo data (4)) ........................................ 493 figure 16.20 transmit and receive timing (16-bit st ereo data).............................................. 493 figure 16.21 example of co nfiguration in spi mode................................................................ 494 figure 16.22 spi data/clo ck timing 1 (cpha = 0).................................................................. 496 figure 16.23 spi data/clo ck timing 2 (cpha = 1).................................................................. 497 figure 16.24 spi transmission/reception operation (example of full-duplex transmi ssion/reception by the cpu with tdmae = 0) ........................................................................................................ 498 figure 16.25 spi transmission operation (example of half-duplex transmissi on by the cpu with tdmae = 0)............. 499 figure 16.26 spi transmission operation (example of half-duplex transmi ssion by dma with tdmae = 1) ................. 500 figure 16.27 spi reception operation (example of half-duplex reception by dma with rdmae = 1)...................... 501 section 17 host interface (hif) figure 17.1 bloc k diagram of hif............................................................................................. 504 figure 17.2 hif co nnection exam ple........................................................................................ 506 figure 17.3 basic ti ming for hif interface ............................................................................... 522 figure 17.4 hifidx wr ite and hifgsr read .......................................................................... 523 figure 17.5 hif register settings ............................................................................................ .. 523 figure 17.6 consecutive data writing to hifram................................................................... 524 figure 17.7 consecutive da ta reading from hifram ............................................................. 525 figure 17.8 hifdreq timing (when dmd = 0 and dpol = 0)............................................. 526 figure 17.9 hifdreq timing (when dmd = 0 and dpol = 1)............................................. 526 figure 17.10 hifdreq timing (w hen dmd = 1 and dpol = 0) ........................................... 527 figure 17.11 hifdreq timing (w hen dmd = 1 and dpol = 1) ........................................... 527 figure 17.12 image of high-impedance co ntrol of hif pins by hifebl pin .......................... 532 section 19 i/o ports figure 19.1 port a ........................................................................................................... ........... 569 figure 19.2 port b ........................................................................................................... ........... 571 figure 19.3 port c ........................................................................................................... ........... 573 figure 19.4 port d ........................................................................................................... ........... 576 rev. 5.00 mar. 15, 2007 page xxix of xxxviii figure 19.5 port e........................................................................................................... ............ 578 section 20 user break controller (ubc) figure 20.1 bloc k diagram of ubc........................................................................................... 58 4 section 21 user debugging interface (h-udi) figure 21.1 block diagram of h-udi........................................................................................ 605 figure 21.2 tap contro ller state tran sitions ............................................................................ 616 figure 21.3 h-udi da ta transfer timing.................................................................................. 618 figure 21.4 h-udi reset...................................................................................................... ...... 618 section 22 ethernet physic al layer transceiver (phy) figure 22.1 the block diag ram around phy module................................................................ 622 figure 22.2 arch itectural overview ........................................................................................... 624 figure 22.3 how to derive md io signal from co re signa ls .................................................... 625 figure 22.4 mdio timing and frame structure (r ead cycle) ............................................... 626 figure 22.5 mdio timing and fr ame structure (wri te cycle).............................................. 626 figure 22.6 100b ase-tx data path ............................................................................................ 6 38 figure 22.7 r eceive data path ................................................................................................ ... 641 figure 22.8 relationship between r eceived data and some mii sign als.................................. 643 figure 22.9 manchest er encoded output ................................................................................... 645 figure 22.10 role of each bit field (example of rising waveform) slope is controlled in four segments................................................................... 661 figure 22.11 example of connection with a pulse transf ormer (rj45) .................................... 663 section 23 phy in terface (phy-if) figure 23.1 block diagram of phy-if ...................................................................................... 668 section 25 electrical characteristics figure 25.1 external clock input timing................................................................................... 720 figure 25.2 ckio clock output ti ming and ck_phy clock input timing ............................ 720 figure 25.3 oscillation settli ng timing after power-on............................................................ 721 figure 25.4 oscillation settling timi ng after standby mode (by rese t)................................... 721 figure 25.5 oscillation settling timing after standby mode (b y nmi or irq)........................ 721 figure 25.6 pll synchronize se ttling timing by re set or nm i .............................................. 722 figure 25.7 re set input timing............................................................................................... ... 723 figure 25.8 interrupt input timing........................................................................................... .. 724 figure 25.9 pin drive ti ming in sta ndby mode ........................................................................ 724 figure 25.10 basic bus timing: no wa it cycle ........................................................................ 727 figure 25.11 basic bus timing: one software wait cycl e ....................................................... 728 figure 25.12 basic bus timing: one external wait cycl e ........................................................ 729 figure 25.13 basic bus timing: one software wait cycle, external wait enabled (wm bit = 0), no idle cycle............................................ 730 rev. 5.00 mar. 15, 2007 page xxx of xxxviii figure 25.14 byte control sram timing: sw = 1 cycle, hw = 1 cycle, one asynchronous external wait cycle, csnwcr.bas = 0 (ub-/lb-controlled write cycle) ...... 731 figure 25.15 byte control sram timing: sw = 1 cycle, hw = 1 cycle, one asynchronous external wait cycle, csnwcr.bas = 1 (we-controlled write cycle)............. 732 figure 25.16 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 0 cycle)...... 733 figure 25.17 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 1 cycle)...... 734 figure 25.18 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 1 cycle)....... 735 figure 25.19 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 0 cycle)....... 736 figure 25.20 synchronous dram single write bus cycle (auto-precharge, trwl = 1 cycl e)..................................................................... 737 figure 25.21 synchronous dram single write bus cycle (auto-precharge, wtrcd = 2 cy cles, trwl = 1 cycle) ................................... 738 figure 25.22 synchronous dram burst write bus cycle (single write 4) (auto-precharge, wtrcd = 0 cy cle, trwl = 1 cycle) .................................... 739 figure 25.23 synchronous dram burst write bus cycle (single write 4) (auto-precharge, wtrcd = 1 cy cle, trwl = 1 cycle) .................................... 740 figure 25.24 synchronous dram burst read bus cycle (single read 4) (bank active mode: act + read commands, cas latency = 2, wtrcd = 0 cy cle) .............................................................................................. 741 figure 25.25 synchronous dram burst read bus cycle (single read 4) (bank active mode: read command, same row address, cas latency = 2, wtrcd = 0 cy cle) .............................................................................................. 742 figure 25.26 synchronous dram burst read bus cycle (single read 4) (bank active mode: pre + act + read commands, different row addresses, cas latency = 2, wt rcd = 0 cy cle)................................................................. 743 figure 25.27 synchronous dram burst write bus cycle (single write 4) (bank active mode: act + write commands, wtrcd = 0 cycle, trwl = 0 cy cle) ................................................................................................. 744 figure 25.28 synchronous dram burst write bus cycle (single write 4) (bank active mode: write command, same row address, wtrcd = 0 cycle, trwl = 0 cy cle) ................................................................................................. 745 figure 25.29 synchronous dram burst write bus cycle (single write 4) (bank active mode: pre + act + write commands, different row addresses, wtrcd = 0 cycle, tr wl = 0 cycle)................................................................. 746 figure 25.30 synchronous dram auto-refreshing timing (wtrp = 1 cycle, wt rc = 3 cycl es)................................................................. 747 rev. 5.00 mar. 15, 2007 page xxxi of xxxviii figure 25.31 synchronous dram self-r efreshing timing (w trp = 1 cy cle) ....................... 748 figure 25.32 synchronous dram mode re gister write timing (wtrp = 1 cycle)............... 749 figure 25.33 pcmcia memory card interface bus timing ..................................................... 750 figure 25.34 pcmcia memory card interface bus timing (ted = 2.5 cycles, teh = 1.5 cycl es, one software wait cycle, one external wa it cycle) ..................................................................................... 751 figure 25.35 pcmcia i/o ca rd interface bus timing.............................................................. 752 figure 25.36 pcmcia i/o card interface bus timing (ted = 2.5 cycles, teh = 1.5 cycl es, one software wait cycle, one external wa it cycle) ..................................................................................... 753 figure 25.37 dreq input timing.............................................................................................. 7 54 figure 25.38 tendn, dac kn output timing .......................................................................... 754 figure 25.39 sck i nput clock ti ming....................................................................................... 755 figure 25.40 sci input/output timi ng in clocked sync hronous mode .................................... 756 figure 25.41 siom clk input ti ming....................................................................................... 757 figure 25.42 siof transmit/receive timing (master mode 1/falling edge sampling).......... 757 figure 25.43 siof transmit/receive timing (master mode 1/rising edge sampling)........... 758 figure 25.44 siof transmit/receive timing (master mode 2/falling edge sampling).......... 758 figure 25.45 siof transmit/receive timing (master mode 2/rising edge sampling)........... 759 figure 25.46 siof transmit/receive timi ng (slave mode 1/ slave mode 2) ......................... 759 figure 25.47 i/o port timing ................................................................................................. .... 760 figure 25.48 hif access timing ............................................................................................... 762 figure 25.49 hifint and hifdreq timing ............................................................................ 762 figure 25.50 hifrdy and hif pin enable/disable timing...................................................... 763 figure 25.51 mii transmissi on timing (normal operation)..................................................... 765 figure 25.52 mii transmissi on timing (collisi on occurred).................................................... 765 figure 25.53 mii reception timing (normal operation) .......................................................... 766 figure 25.54 mii receptio n timing (error occurred) ............................................................... 766 figure 25.55 md io input timing .............................................................................................. 7 66 figure 25.56 mdio output timing ........................................................................................... 766 figure 25.57 wol output timing ............................................................................................. 76 7 figure 25.58 exou t output timing......................................................................................... 767 figure 25.59 tck input timing................................................................................................ .768 figure 25.60 tck input timi ng in reset hold state ................................................................. 768 figure 25.61 h-udi data transmission timing ........................................................................ 768 figure 25.62 output load circuit............................................................................................. .. 769 appendix figure c.1 package di mensions (bp-176) ................................................................................. 777 rev. 5.00 mar. 15, 2007 page xxxii of xxxviii rev. 5.00 mar. 15, 2007 page xxxiii of xxxviii tables section 1 overview table 1.1 features of sh7619 .................................................................................................. 2 table 1.2 pin functions ............................................................................................................ 9 table 1.3 pin features ............................................................................................................ 17 section 2 cpu table 2.1 initial values of registers....................................................................................... 27 table 2.2 word data sign extension...................................................................................... 29 table 2.3 delayed branch instructions................................................................................... 30 table 2.4 t bit ........................................................................................................................ 30 table 2.5 access to imme diate data ...................................................................................... 31 table 2.6 access to absolu te address.................................................................................... 31 table 2.7 access with di splacement ...................................................................................... 32 table 2.8 addressing modes and ef fective addresses........................................................... 32 table 2.9 instruction formats ................................................................................................. 36 table 2.10 instruction types .................................................................................................... 39 section 3 cache table 3.1 lru and way to be replaced ................................................................................ 54 table 3.2 correspondence between divided areas and cache............................................... 55 section 5 exception handling table 5.1 types of exceptions and priority............................................................................ 67 table 5.2 timing for exception detection and start of exception handling ......................... 68 table 5.3 vector numbers and vector table address offsets............................................... 69 table 5.4 calculating exception handling vector table addresses ...................................... 70 table 5.5 reset st atus............................................................................................................. 71 table 5.6 bus cycles and ad dress errors............................................................................... 73 table 5.7 interrupt sources..................................................................................................... 74 table 5.8 interrupt priority ..................................................................................................... 75 table 5.9 types of exceptions trig gered by instructions ...................................................... 76 table 5.10 delay slot instructions, interrupt disa bled instructions, and exceptions............... 78 table 5.11 stack status after exce ption handling ends........................................................... 79 section 6 interrupt controller (intc) table 6.1 pin configuration.................................................................................................... 85 table 6.2 interrupt exception handling vectors and pr iorities............................................ 100 table 6.3 interrupt response time....................................................................................... 105 rev. 5.00 mar. 15, 2007 page xxxiv of xxxviii section 7 bus state controller (bsc) table 7.1 pin configuration.................................................................................................. 110 table 7.2 address map 1 (cmn cr.map = 0) .................................................................... 113 table 7.3 address map 2 (cmn cr.map = 1) .................................................................... 113 table 7.4 correspondence between external pin (md3), memory type, and bus width for cs0......................................................................................... 114 table 7.5 correspondence between external pin (md5) and endians................................. 114 table 7.6 32-bit external device/big endian access and data alignment......................... 143 table 7.7 16-bit external device/big endian access and data alignment......................... 144 table 7.8 8-bit external device/big endian access and data alignment........................... 145 table 7.9 32-bit external device/big endian access and data alignment......................... 146 table 7.10 16-bit external device/little endian access and data alignment ...................... 147 table 7.11 8-bit external device/little endian access and data alignment ........................ 148 table 7.12 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (1)........................................... 160 table 7.13 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (2)........................................... 161 table 7.14 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (3)........................................... 163 table 7.15 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (4)........................................... 164 table 7.16 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (5)........................................... 165 table 7.17 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (6)........................................... 167 table 7.18 relationship between access size and number of bursts.................................... 169 table 7.19 access address for sdram m ode register write.............................................. 185 section 8 clock pulse generator (cpg) table 8.1 pin configuration.................................................................................................. 204 table 8.2 mode control pins and cl ock operating modes .................................................. 204 table 8.3 possible combination of clock modes and frqcr values................................ 205 section 10 power-down modes table 10.1 states of power- down modes .............................................................................. 223 table 10.2 pin configuration.................................................................................................. 224 table 10.3 register states in soft ware standby mode........................................................... 230 section 11 ethernet controller (etherc) table 11.1 pin configuration.................................................................................................. 235 rev. 5.00 mar. 15, 2007 page xxxv of xxxviii section 12 ethernet controller direct memory access controller (e-dmac) table 12.1 eesr bits for which this problem can occur and reflection of interrupt sources in the descri ptor................................................................... 305 table 12.2 reference values for maxi mum specified time.................................................. 321 section 13 direct memory access controller (dmac) table 13.1 pin configuration.................................................................................................. 325 table 13.2 transfer request sources ..................................................................................... 336 table 13.3 selecting external request modes with rs bits .................................................. 339 table 13.4 selecting external request det ection with dl, ds bits ...................................... 340 table 13.5 selecting external request de tection with do bit .............................................. 340 table 13.6 selecting on-chip peripheral module re quest modes with rs3 to rs0 bits ..... 341 table 13.7 supported dma transfers.................................................................................... 344 table 13.8 relationship between request modes and bus modes by dma transfer category .................................................................................. 351 section 15 serial communication interface with fifo (scif) table 15.1 scif pins .............................................................................................................. 376 table 15.2 scsmr settin gs ................................................................................................... 395 table 15.3 bit rates and scbrr settings in asynchronous mode ....................................... 395 table 15.4 bit rates and scbrr settings in synchronous mode ......................................... 398 table 15.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) .......................................................................................... 399 table 15.6 maximum bit rates with external cl ock input (asynchronous mode)............... 400 table 15.7 maximum bit rates with external cl ock input (synchr onous mode) ................. 400 table 15.8 scsmr settings and scif co mmunication fo rmats........................................... 411 table 15.9 scsmr and scscr settings and scif clock source selection......................... 411 table 15.10 serial communication formats (asynchronous mode).................................... 413 table 15.11 scif interrup t sources ..................................................................................... 431 section 16 serial i/o with fifo (siof) table 16.1 pin configuration.................................................................................................. 443 table 16.2 operation in each transfer mode......................................................................... 447 table 16.3 siof serial cloc k frequency ............................................................................... 473 table 16.4 serial transfer modes........................................................................................... 475 table 16.5 frame length........................................................................................................ 476 table 16.6 audio mode specification for transmit data....................................................... 478 table 16.7 audio mode specification for receive data ........................................................ 478 table 16.8 setting number of channels in control data ....................................................... 479 table 16.9 conditions to issue transmit request .................................................................. 481 table 16.10 conditions to issue receive request ................................................................ 481 rev. 5.00 mar. 15, 2007 page xxxvi of xxxviii table 16.11 transmit and recei ve reset ............................................................................. 487 table 16.12 siof interrupt sources ..................................................................................... 488 table 16.13 states of transmit and receive operations in spi mode ................................. 495 section 17 host interface (hif) table 17.1 pin configuration.................................................................................................. 505 table 17.2 hif opera tions ..................................................................................................... 506 table 17.3 memory map ........................................................................................................ 521 table 17.4 consecutive write procedure to hifram by external dmac........................... 528 table 17.5 consecutive read procedure from hifram by external dmac....................... 529 table 17.6 hifdata register alignment for a ccess by an extern al device ...................... 531 table 17.7 hif registers (other than hifdata) alignment for access by an external device........................................................................................... 531 table 17.8 input/output control for hif pins........................................................................ 533 section 18 pin function controller (pfc) table 18.1 list of multiplexed pins (port a) ......................................................................... 535 table 18.2 list of multiplexed pins (por t b).......................................................................... 535 table 18.3 list of multiplexed pins (por t c).......................................................................... 537 table 18.4 list of multiplexed pins (port d) ......................................................................... 538 table 18.5 list of multiplexed pins (por t e).......................................................................... 538 table 18.6 pin functions in each operating mode ................................................................ 540 section 19 i/o ports table 19.1 port a data register h (padrh ) read/write op eration.................................... 570 table 19.2 port b data register l (pbdrl ) read/write operation ..................................... 572 table 19.3 port c data registers h and l (pcdrh and pcdrl) read/write operation .... 575 table 19.4 port d data register l (pddrl) read/write operation..................................... 577 table 19.5 port e data registers h, l (pedrh, pedrl) read/write operation ................ 580 section 20 user break controller (ubc) table 20.1 data access cycle addresses and oper and size comparison conditions........... 597 section 21 user debugging interface (h-udi) table 21.1 pin configuration.................................................................................................. 606 table 21.2 h-udi commands................................................................................................ 608 table 21.3 external pins and boundary scan regist er bits ................................................... 609 table 21.4 reset configur ation .............................................................................................. 617 section 22 ethernet physic al layer transceiver (phy) table 22.1 pin configuration.................................................................................................. 623 table 22.2 4b/5b code table ................................................................................................ 639 rev. 5.00 mar. 15, 2007 page xxxvii of xxxviii section 25 electrical characteristics table 25.1 absolute maximum ratings ................................................................................. 713 table 25.2 recommended timing at power-on..................................................................... 714 table 25.3 recommended timing in power-off.................................................................... 715 table 25.4 dc characteris tics (1)........................................................................................... 716 table 25.4 dc characteris tics (2)........................................................................................... 717 table 25.5 permissible output currents ................................................................................. 718 table 25.6 maximum operating frequency ........................................................................... 718 table 25.7 clock timing ........................................................................................................ 719 table 25.8 control signal timing .......................................................................................... 723 table 25.9 bus timing ........................................................................................................... 725 table 25.10 dmac signal timing....................................................................................... 754 table 25.11 scif timing ..................................................................................................... 755 table 25.12 scif timing ..................................................................................................... 756 table 25.13 port timing ....................................................................................................... 760 table 25.14 hif timing ....................................................................................................... 761 table 25.15 etherc timing .................................................................................................. 764 table 25.16 h-udi related pi n timing............................................................................... 767 table 25.17 phy character istics.......................................................................................... 770 appendix table a.1 port states in e ach pin state................................................................................. 771 rev. 5.00 mar. 15, 2007 page xxxviii of xxxviii section 1 overview rev. 5.00 mar. 15, 2007 page 1 of 794 rej09b0237-0500 section 1 overview this lsi is a cmos single-chip microcontroller that integrates a renesas technology original risc (reduced instruction set computer) cpu core with peripheral functions required for an ethernet system. the cpu of this lsi has a risc (reduced instru ction set computer) type instruction set. the cpu basically operates at a rate of one instruc tion per cycle, offering a great improvement in instruction execution speed. in addition, the 32-bit internal architecture provides improved data processing power. with this cpu, it has beco me possible to assemble low-cost and high- performance/high-functionality systems even for ap plications such as realtime control, which could not previously be handled by microcontr ollers because of thei r high-speed processing requirements. this lsi is equipped with an ethernet controlle r that includes a media access controller (mac) conforming to the ieee802.3u standard and a physical layer transceiver (phy), enabling 10/100 mbps lan connection. as the eq uipped ethernet controller also includes a media independent interface (mii) standard unit, a phy lsi can be externally connected. in addition, this lsi provides on-chip peripheral functions necessary for system configuration, such as cache memory, ram, a direct memo ry access controller (dmac), timers, a serial communication interface with fifo (scif), a serial io with fi fo (siof), a host interface (hfi), an interrupt controller (intc), and i/o ports. the external memory access support function of this lsi enables direct connection to various types of memory, such as standard memory, sd ram, and pcmcia. this greatly reduces system cost. section 1 overview rev. 5.00 mar. 15, 2007 page 2 of 794 rej09b0237-0500 1.1 features the features of this lsi are listed in table 1.1. table 1.1 features of sh7619 items specification cpu ? central processing unit with an internal 32-bit risc (reduced instruction set computer) architecture ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture (basic operations are executed between registers) ? sixteen 32-bit general registers ? five-stage pipeline ? on-chip multiplier: multiplication operations (32 bits 32 bits 64 bits) executed in two to five cycles ? c language-oriented 62 basic instructions note: some specifications on the slot illegal instruction differ from the conventional sh2 core. for details, see section 5.8, usage notes in section 5, exception handling. user break controller (ubc) ? address, data value, access type, and data size are available for setting as break conditions ? supports the sequential break function ? two break channels u memory ? 16 kbytes cache memory ? unified cache, mixture of instructions and data ? 4-way set associative type ? selection of write-back or write-through mode ? 16 kbytes section 1 overview rev. 5.00 mar. 15, 2007 page 3 of 794 rej09b0237-0500 items specification bus state controller (bsc) ? address space is divided into five areas: three areas 0, 3, and 4; each a maximum of 64 mbytes, and two areas 5b and 6b; each a maximum of 32 mbytes (address map 1 mode). ? address space is divided into five areas, 0, 3, 4, 5, and 6; each a maximum of 64 mbytes (address map 2 mode). ? 32-bit external bus (max.) ? the following features ar e settable for each area. ? bus size (8, 16, or 32 bits) (area 0 does not support the bus size of 32 bits.) ? number of access wait cycles ? setting of idle wait cycles ? specifying the memory to be connect ed to each area enables direct connection to sram, sdram, and pcmcia. ? outputs chip select signals (cs0, cs3, cs4, cs5b, and cs6b) for corresponding area ? sdram refresh function ? supports auto-refresh and self-refresh modes ? sdram burst access function ? pcmcia access function ? conforms to the jeida ver. 4.2 standard, two slots ? selection of big or little endian mode (the mode of all the areas is switched collectively by a mode pin.) direct memory access controller (dmac) ? four channels; external request available for two of them ? burst mode and cycle steal mode ? outputs a transfer end signal of the channel handling an external request ? intermittent mode available (16 and 64 cycles supported) interrupt controller (intc) ? supports nine external interrupt pins (nmi, irq7 to irq0) ? on-chip peripheral interrupt: priority level is independently selected for each module ? vector address: specified vector address for each interrupt source user debugging interface (h-udi) ? supports the jtag interface emulator ? jtag standard pins arranged section 1 overview rev. 5.00 mar. 15, 2007 page 4 of 794 rej09b0237-0500 items specification clock pulse generator (cpg) ? clock mode: input clock can be selected from external input or crystal resonator ? three types of clocks generated: ? cpu clock: 125 mhz (max.) ? bus clock: 62.5 mhz (max.) ? peripheral clock: 31.25 mhz (max.) ? supports power-down modes: ? sleep mode ? software standby mode ? selection of four types of clock modes (pll2 2/ 4 and clock/crystal resonator are selectable) ethernet controller (etherc) ? mac (media access control) function ? data frame assembly/disassembly (frame format conforming to ieee802.3u) ? csma/cd link management (collision prevention and collision processing) ? crc processing ? 512 bytes each for transmit/receive fifo ? full-duplex transmit/receive support ? short frame/long frame detectable ? conforms to the mii (media independent interface) standard ? conversion from 8-bit stream data in mac layer to mii nibble (4-bit) stream ? station management (sta function) ? 18 ttl-level signals ? 10/100 mbps transfer rate adjustable ? magic packet tm * (wol (wake-on-lan) output) ethernet controller dmac (edmac) ? cpu load reduced with the descriptor management method ? for transferring from etherc receive fifo to receive buffer 1 channel ? for transferring from transmit buffer to etherc transmit fifo 1 channel ? 16-byte burst transfer improves the efficiency of system bus ? supports single frame and multiple buffer section 1 overview rev. 5.00 mar. 15, 2007 page 5 of 794 rej09b0237-0500 items specification ethernet physical layer transceiver (phy) ? conforms to the ieee802.3u standard. 10base-t and 100base-tx supported ? supports auto-negotiation and manual-negotiation modes ? supports power-down modes ? outputs the status of link, activity, duplex, and speed ? selection of either on-chip clock oscillator output or dedicated clock externally input host interface (hif) ? 1 kbyte 2 banks: in total 2-kbyte buffer ram ? the buffer ram and the external device are connected in parallel via 16 data pins ? the buffer ram and the cpu of this lsi are connected in parallel via internal bus ? the external device can access the desired register after the register index has been specified. (however, when the buffer ram is accessed successively, the address is updated automatically.) ? selection of endian mode ? interrupt requested to the external device ? internal interrupt requested to the cpu of this lsi ? booting from the buffer ram is enabled if the external device has stored the instruction code in the buffer ram compare match timer (cmt) ? 16-bit counter ? generates compare match interrupts ? two channels serial communication interface with fifo (scif) ? synchronous and asynchronous modes ? 16 bytes each for transmit/receive fifo ? high-speed uart ? the uart supports fifo stop and fifo trigger ? flow control enabled (channel 0 and channel 1 only) ? three channels section 1 overview rev. 5.00 mar. 15, 2007 page 6 of 794 rej09b0237-0500 items specification serial io with fifo (siof) ? 64 bytes each for transmit/receive fifo ? supports 8-/16-/16-bit stereo sound input/output ? can operate together with the dmac ? supports frame synchronous signals ? one channel i/o ports ? 78 general input/output pins ? input or output can be set per bit within the input/output common port package ? bp1313-176 (0.8 pitch) power supply voltage ? i/o: 3.0 to 3.6 v internal: 1.8 0.09 v (two power sources are externally provided.) note: * magic packet tm is the registered trademark of advance micro devices, inc. section 1 overview rev. 5.00 mar. 15, 2007 page 7 of 794 rej09b0237-0500 1.2 block diagram figure 1.1 is a block diagram of this lsi. superh cpu core user break controller (ubc) cache access controller (ccn) u memory 16 kbytes cache memory 16 kbytes bus state controller (bsc) peripheral bus controller direct memory access controller for ethernet controller (e-dmac) cpu bus (i clock) internal bus (b clock) external bus notes: host interface (hif) user debugging interface (h-udi) interrupt controller (intc) power- down mode control watchdog timer (wdt) clock pulse generator (cpg) serial communication interface with fifo (scif) * 1 transmit fifo (512 bytes) ethernet physical layer transceiver (phy) receive fifo (512 bytes) peripheral bus (p clock) i/o port, pin function controller (pfc) compare match timer (cmt) * 2 1-kbyte sram 1. scif includes three channels. 2. cmt includes two channels. direct memory access controller (dmac) ethernet controller (etherc) serial io with fifo (siof) figure 1.1 block diagram section 1 overview rev. 5.00 mar. 15, 2007 page 8 of 794 rej09b0237-0500 1.3 pin assignments 1 a b c d e f g h j k l m n p r 23456789101112131415 vccq bp1313-176 (top view) vssq pd4 pd0 vss pe22 pe18 pe16 pe13 vccq pe06 pe04 pe00 pc15 txm pa25 pd7 pd5 pd2 vcc pe20 pe17 pe15 pe11 vssq pe05 pe02 pc16 pc18 txp pa 2 2 pa24 pd6 pd3 pe08 pe23 pe19 vss pe12 pe09 pe07 pe01 vss1a vss1a rxm pa 1 8 pa 2 0 pa 2 1 pa 2 3 pa 1 6 pa 1 7 pb08 pa 1 9 pb09 pb07 pb10 pb01 vcc vss pb06 pb05 rd pb00 pb11 cs0 vccq vssq pb13 a14 a13 a15 a12 a10 a11 a09 a08 a06 pd1 pe24 pe21 vcc pe14 pe10 pe03 pc17 vcc1a vcc2a rxp tstbusa exres1 vss2a vcc3a pc09 pc08 pc02 pc00 pc01 pc03 vssq vccq pc13 pc11 pc04 pc10 pc05 pc07 pc12 pc06 vcc vss pc20 pc14 md5 pc19 ck_phy testout a07 a05 a04 pb03 vss d13 d06 d03 md2 vcc nmi tdi tdo tck md3 a03 a02 a00 rd/( wr ) vcc d11 d15 d05 d01 vss asemd tms md0 vccq extal a01 vssq pb04 we1 / dqmlu/ we d09 d10 d14 vccq d04 d00 testmd trst vss(pll1) vssq xtal pb12 vccq pb02 we0 / dqmll d08 d12 d07 vssq d02 ckio md1 res vcc(pll1) vss(pll2) vcc(pll2) 123456789101112131415 a b c d e f g h j k l m n p r figure 1.2 pin assignments section 1 overview rev. 5.00 mar. 15, 2007 page 9 of 794 rej09b0237-0500 1.4 pin functions table 1.2 pin functions classifi- cation abbr. i/o pin name description power supply vcc input power supply power supply for the inte rnal logic of this lsi. all the vcc pins must be connected to the system power supply. this lsi does not operate correctly if there is a pin left open. vss input ground ground pins. all the vss pins must be connected to the system power supply (0 v) . this lsi does not operate correctly if there is a pin left open. vccq input power supply power supply for i nput/output pins. all the vccq pins must be connected to the system power supply. this lsi does not operate correctly if there is a pin left open. vssq input ground ground pins. all t he vssq pins must be connected to the system power supply (0 v) . this lsi does not operate correctly if there is a pin left open. clock vcc (pll1) input power supply for pll1 power supply pin for the on-chip pll1 oscillator vss (pll1) input ground for pll1 ground pin for the on-chip pll1 oscillator vcc (pll2) input power supply for pll2 power supply pin for the on-chip pll2 oscillator vss (pll2) input ground for pll2 ground pin for the on-chip pll2 oscillator extal input external clock connects to a cryst al resonator. an external clock is also input on this pin. for details on connection of an external clock, see section 8, clock pulse generator (cpg). xtal output crystal connects to a crystal resonator. ckio output system clock supplies the system clock to external devices. operating mode control md5, md3 to md0 input mode setting these pins set operat ing mode. the signal levels of these pins must not be changed during operation. pins md2 to md0 are used for setting clock mode, pin md3 is for setting bus width mode for area 0, and pin md5 is for setting endian. system control res input power-on reset this lsi enters the power-on reset state when this signal goes low. section 1 overview rev. 5.00 mar. 15, 2007 page 10 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description interrupt nmi input non-maskable interrupt non-maskable interrupt request pin. this pin must be fixed high when not in use. irq7 to irq0 input interrupt request 7 to 0 maskable interrupt request pins. level-input or edge-input detection can be selected. when the edge-input detection is selected, the rising or falling edge can also be selected. address bus a25 to a0 output address bus these pins output addresses. data bus d31 to d0 input/ output data bus 32-bit bidirectional bus bus control cs0 , cs3 , cs4 , cs5b , cs6b output chip select 0, 3, 4, 5b, 6b chip select signals for external memory and devices. rd output read indicates that data is read from an external device. rd/ wr output read/write read/write signal bs output bus cycle start indicates start of a bus cycle. we3 output most significant byte write indicates that bits 31 to 24 of data of external memory or devices are written to. we2 output second byte write indicates that bits 23 to 16 of data of external memory or devices are written to. we1 output third byte write indicates that bits 15 to 8 of data of external memory or devices are written to. we0 output least significant byte write indicates that bits 7 to 0 of data of external memory or devices are written to. wait input wait input pin used to insert wait cycles into the bus cycle when accessing the external space ras output ras connects to the ras pin of sdram. cas output cas connects to the cas pin of sdram. cke output clock enable connects to the cke pin of sdram. dqmuu output most significant byte select selects bits 31 to 24 of sdram data bus. section 1 overview rev. 5.00 mar. 15, 2007 page 11 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description bus control dqmul output second byte select selects bits 23 to 16 of sdram data bus. dqmlu output third byte select selects bits 15 to 8 of sdram data bus. dqmll output least significant byte select selects bits 7 to 0 of sdram data bus. ce1a output pcmcia card select lower side chip enable for pcmcia allocated to area 5 ce1b output pcmcia card select lower side chip enable for pcmcia allocated to area 6 ce2a output pcmcia card select upper side chip enable for pcmcia allocated to area 5 ce2b output pcmcia card select upper side chip enable for pcmcia allocated to area 6 iciowr output pcmcia i/o write strobe connects to the pcmcia i/o write strobe pin. iciord output pcmcia i/o read strobe connects to the pcmcia i/o read strobe pin. we output pcmcia memory write strobe connects to the pcmcia memory write strobe. iois16 input pcmcia dynamic bus sizing in little endian mode, this signal indicates 16-bit bus width of pcmcia. in big endian mode, fix this pin low. crs input carrier sense carrier sense pin ethernet controller col input collision collision detect pin mii_txd3 to mii_txd0 output transmit data 4-bit transmit data pins tx_en output transmit enable indicates that transmit data is on pins mii_txd3 to mii_txd0. section 1 overview rev. 5.00 mar. 15, 2007 page 12 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description ethernet controller tx_clk input transmit clock timing reference input for the tx_en, tx_er, and mii_txd3 to mii_txd0 pins tx_er output transmit error informs ph y lsi of an error during transmission. mii_rxd3 to mii_rxd0 input receive data 4-bit receive data pins rx_dv input receive data valid indicates that valid receive data is on pins mii_rxd3 to mii_rxd0. rx_clk input receive clock timing refe rence input for the rx_dv, rx_er, and mii_rxd3 to mii_rxd0 pins rx_er input receive error pin for det ection of an error during reception mdc output management clock timing reference input for transfer information on the mdio pin mdio input/ output management data i/o bidirectional pin for managem ent information transfer wol output magic packet receive indicates that a magic packet ? * has received. lnksta input link status input pin for a link state from a phy lsi. exout output general output output pin to external devices dreq1, dreq0 input dma transfer request input pins for external dma transfer request dack1, dack0 output dma transfer request receive request receive output pins for external dma transfer request direct memory access controller tend1, tend0 output dma transfer end output pins for dma transfer end signal txd2 to txd0 output transmit data transmit data pins rxd2 to rxd0 input receive data receive data pins sck2 to sck0 input/ output serial clock cl ock input pins serial communi- cation interface with fifo rts1 and rts0 output transmit request modem control pins. supported only by scif0 and scif1. section 1 overview rev. 5.00 mar. 15, 2007 page 13 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description serial communi- cation interface with fifo cts1 and cts0 input transmit enable modem control pins. supported only by scif0 and scif1. siomclk0 input siof0 clock input master clock input pin serial i/o with fifo sck_sio0 input/ output siof0 communication clock input/output pin for communi cation clock common to transmit/receive siofsync0 input/ output siof0 frame sync input/output pin for frame synchronization signal common to transmit/receive txd_sio0 output siof0 transmit data transmit data rxd_sio0 input siof0 receive data receive data host interface hifd15 to hifd00 input/ output hif data bus address, data, and command input/output pins for the hif. hifcs input hif chip select chip select input for the hif. hifrs input hif register select controls the access type switching for the hif. hifwr input hif write write strobe signal hifrd input hif read read strobe signal hifint output hif interrupt interrupt request to external devices by the hif. hifmd input hif mode specifies hif boot mode. hifdreq output hif dmac transfer request requests dmac transfer for the hifram to external devices. hifrdy output hif boot ready indicates that a reset of the hif has been cleared in this lsi and the hif is ready for accesses to it. hifebl input hif pin enable hif pins other than this pin ar e enabled by driving this pin high. section 1 overview rev. 5.00 mar. 15, 2007 page 14 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description tck input test clock test clock input pin tms input test mode select input pin for test mode select signal user debugging interface (h-udi) tdi input test data input serial input pin for an instruction and data tdo output test data output serial output pin for an instruction and data trst input test reset input pin for initialization i/o ports pa25 to pa16 input/ output general port pins for 10-bit general input/output port pb13 to pb00 input/ output general port pins for 14-bit general input/output port pc20 to pc00 input/ output general port pins for 21-bit general input/output port pd07 to pd00 input/ output general port pins for 8-bit general input/output port pe24 to pe00 input/ output general port pins for 25-bit general input/output port emulator interface asemd input ase mode specifies ase mode. this lsi enters ase mode when this signal goes low and normal mode when this pin goes high. in ase mode, functions for the emulator are available. test mode testmd input test mode specifies test mode. this lsi enters test mode when th is signal goes low. fix this signal high. testout output test output output pin for testing. this pin should be open. vcc1a input analog power supply 1 for phy analog power supply pin for the phy physical layer trans- ceiver (phy) vcc2a input analog power supply 2 for phy analog power supply pin for the phy section 1 overview rev. 5.00 mar. 15, 2007 page 15 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description vcc3a input analog power supply 3 for phy analog power supply pin for the phy physical layer trans- ceiver (phy) vss1a input analog ground 1 for phy analog ground pin for the phy vss2a input analog ground 2 for phy analog ground pin for the phy ck_phy input phy clock this pins is used to externally supply clocks to the phy. when clocks are supplied to the on-chip phy from the on- chip clock pulse generator (cpg), this pins should be pulled up to vccq or pulled down to vssq. txp output differential transmit data (+) differential transmit output (+) for the ethernet circuit by the phy. txm output differential transmit data (-) differential transmit output (-) for the ethernet circuit by the phy. rxp input differential receive data (+) differential receive input (+) for the phy by the ethernet circuit. rxm input differential receive data (-) differential receive input (-) for the phy by the ethernet circuit. section 1 overview rev. 5.00 mar. 15, 2007 page 16 of 794 rej09b0237-0500 classifi- cation abbr. i/o pin name description physical layer trans- ceiver (phy) speed100 link crs duplex output output output output speed100 signal link signal crs signal duplex signal monitor output pins indica ting communication status exres1 input reference resistor connect to the phy analog ground through a 12.4-k ? (accuracy: 1%) resistor. tstbusa input/ output test i/o input/output pin for testing the on-chip ieee802.3u phy. this pin should be open. notes fix all unused pins that have no weak keeper circuit to high or low level. unused pins that internally have weak keeper circuit need not to be fixed to high or low level. the weak keeper is a circuit that is included in i/o pins and fixes the input pins to high or low when i/o pins are not driven from outside. * magic packet ? is the trademark of advanced micro devices, inc. section 1 overview rev. 5.00 mar. 15, 2007 page 17 of 794 rej09b0237-0500 table 1.3 pin features pin no. pin name i/o features a1 vccq power a2 pa25/a25/siofsync0 io/o/io a3 pa22/a22/siomclk0 io/o/i a4 pa18/a18 io/o a5 pa16/a16 io/o a6 pb09/ ce2a io/o a7 vcc power a8 rd o a9 vccq power a10 a13 o a11 a11 o a12 a07 o a13 a03 o a14 a01 o a15 pb12/ cs3 io/o b1 vssq power b2 pd7/irq7/sck2 io/i/io b3 pa24/a24/txd_sio0 io/o/o b4 pa20/a20 io/o b5 pa17/a17 io/o b6 pb07/ce2b io/o b7 vss power b8 pb00/ wait io/i b9 vssq power b10 a15 o b11 a09 o b12 a05 o b13 a02 o b14 vssq power b15 vccq power section 1 overview rev. 5.00 mar. 15, 2007 page 18 of 794 rej09b0237-0500 pin no. pin name i/o features c1 pd4/irq4/sck1 io/i/io c2 pd5/irq5/txd2/dreq1 io/i/o/i c3 pd6/irq6/rxd2/dack1 io/i/i/o c4 pa21/a21/sck_sio0 io/o/io c5 pb08/ cs6b / ce1b io/o/o c6 pb10/ cs5b / ce1a io/o/o c7 pb06/ we3 (be3) /dqmuu/ iciowr io/o/o/o c8 pb11/ cs4 io/o c9 pb13/ bs io/o c10 a12 o c11 a08 o c12 a04 o c13 a00 o c14 pb04/ ras io/o c15 pb02/cke io/o d1 pd0/irq0/-/tend0 io/i/-/o d2 pd2/irq2/txd1/dreq0 io/i/o/i d3 pd3/irq3/rxd1/dack0 io/i/i/o d4 pa23/a23/rxd_sio0 io/o/i d5 pa19/a19 io/o d6 pb01/ iois16 io/i d7 pb05/ we2 (be2) /dqmul/ iciord io/o/o/o d8 cs0 o d9 a14 o d10 a10 o d11 a06 o d12 pb03/ cas io/o d13 rd/ wr o d14 we1 /dqmlu/ we o/o/o d15 we0 /dqmll o/o e1 vss power e2 vcc power section 1 overview rev. 5.00 mar. 15, 2007 page 19 of 794 rej09b0237-0500 pin no. pin name i/o features e3 pe08/ hifcs io/i e4 pd1/irq1/-/tend1 io/i/-/o e12 vss power e13 vcc power e14 d09 io e15 d08 io f1 pe22/hifd13/cts0/d29 io/io/i/io f2 pe20/hifd11/sck1/d27 io/io/io/io f3 pe23/hifd14/rts1/d30 io/io/o/io f4 pe24/hifd15/cts1/d31 io/io/i/io f12 d13 io f13 d11 io f14 d10 io f15 d12 io g1 pe18/hifd09/txd1/d25 io/io/o/io g2 pe17/hifd08/sck0/d24 io/io/io/io g3 pe19/hifd10/rxd1/d26 io/io/i/io g4 pe21/hifd12/rts0/d28 io/io/o/io g12 d06 io g13 d15 io g14 d14 io g15 d07 io h1 pe16/hifd07/rxd0/d23 io/io/i/io h2 pe15/hifd06/txd0/d22 io/io/o/io h3 vss power h4 vcc power h12 d03 io h13 d05 io h14 vccq power h15 vssq power j1 pe13/hifd04/-/d20 io/io/-/io j2 pe11/hifd02/-/d18 io/io/-/io section 1 overview rev. 5.00 mar. 15, 2007 page 20 of 794 rej09b0237-0500 pin no. pin name i/o features j3 pe12/hifd03/-/d19 io/io/-/io j4 pe14/hifd05/-/d21 io/io/-/io j12 md2 i j13 d01 io j14 d04 io j15 d02 io k1 vccq power k2 vssq power k3 pe09/hifd00/-/d16 io/io/-/io k4 pe10/hifd01/-/d17 io/io/-/io k12 vcc power k13 vss power k14 d00 io k15 ckio o l1 pe06/ hifwr /siofsync0 io/i/io l2 pe05/ hifrd io/i l3 pe07/hifrs io/i l4 pe03/hifmd io/i l12 nmi i l13 asemd i l14 testmd i l15 md1 i m1 pe04/ hifint /txd_sio0 io/o/o m2 pe02/hifdreq/rxd_sio0 io/o/i m3 pe01/hifrdy/siomclk0 io/o/i m4 pc17/mdc io/o m5 tstbusa io m6 pc09/rx_er io/i m7 pc01/mii_rxd1 io/i m8 pc13/tx_clk io/i m9 pc05/mii_txd1/-/ link io/o/-/o m10 vcc power section 1 overview rev. 5.00 mar. 15, 2007 page 21 of 794 rej09b0237-0500 pin no. pin name i/o features m11 md5 i m12 tdi i m13 tms i m14 trst i m15 res i n1 pe00/hifebl/sck_sio0 io/i/io n2 pc16/mdio io/io n3 vss1a power n4 vcc1a power n5 exres1 i n6 pc08/rx_dv io/i n7 pc03/mii_rxd3 io/i n8 pc11/tx_er io/o n9 pc07/mii_txd3/-/duplex io/o/-/o n10 vss power n11 pc19/exout io/o n12 tdo o n13 md0 i n14 vss (pll1) power n15 vcc (pll1) power p1 pc15/crs io/i p2 pc18/lnksta io/i p3 vss1a power p4 vcc2a power p5 vss2a power p6 pc02/mii_rxd2 io/i p7 vssq power p8 pc04/mii_txd0/-/ speed100 io/o/-/o p9 pc12/tx_en io/o p10 pc20/wol io/o p11 ck_phy i p12 tck i section 1 overview rev. 5.00 mar. 15, 2007 page 22 of 794 rej09b0237-0500 pin no. pin name i/o features p13 vccq power p14 vssq power p15 vss (pll2) power r1 txm o r2 txp o r3 rxm i r4 rxp i r5 vcc3a power r6 pc00/mii_rxd0 io/i r7 vccq power r8 pc10/rx_clk io/i r9 pc06/mii_txd2/-/ crs io/o/-/o r10 pc14/col io/i r11 testout o r12 md3 i r13 extal i r14 xtal o r15 vcc (pll2) power section 2 cpu rev. 5.00 mar. 15, 2007 page 23 of 794 rej09b0237-0500 section 2 cpu 2.1 features ? general registers: 32-bit register 16 ? basic instructions: 62 ? addressing modes: 11 register direct (rn) register indirect (@rn) post-increment regi ster indirect (@rn + ) pre-decrement register indirect (@-rn) register indirect with displacement (@disp:4, rn) index register indirect (@r0, rn) gbr indirect with disp lacement (@disp:8, gbr) index gbr indirect (@r0, gbr) pc relative with displacement (@disp:8, pc) pc relative (disp:8/disp:12/rn) immediate (#imm:8) 2.2 register configuration there are three types of registers: general registers (32-bit 16), control registers (32-bit 3), and system registers (32-bit 4). section 2 cpu rev. 5.00 mar. 15, 2007 page 24 of 794 rej09b0237-0500 31 0 r0 * 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer)0 * 2 31 9 8 7 6 5 4 3 2 1 0 0 0 31 m gbr 31 vbr qi3i2i1i0 s t 31 0 mach 31 0 pr 31 0 pc macl notes: 1. r0 can be used as an index register in index register indirect or index gbr indirect addressing mode. for some instructions, only r0 is used as the source or destination register. 2. r15 is used as a hardware stack pointer during exception handling. general register (rn) status register (sr) global base register (gbr) vector base register (vbr) multiply and accumulate register (mac) procedure register (pr) program counter (pc) figure 2.1 cpu internal register configuration section 2 cpu rev. 5.00 mar. 15, 2007 page 25 of 794 rej09b0237-0500 2.2.1 general registers (rn) there are sixteen 32-bit general registers (rn), designated r0 to r15. the general registers are used for data processing and addr ess calculation. r0 is also used as an index register. with a number of instructions, r0 is the only register that can be used. r15 is used as a hardware stack pointer (sp). in exception handling, r15 is used for accessing the stack to save or restore the status register (sr) and program counter (pc) values. 2.2.2 control registers there are three 32-bit control regi sters, designated status regist er (sr), global base register (gbr), and vector base register (vbr). sr indicates a processing state. gbr is used as a base address in gbr indirect addressing mode for data transfer of on-chip peripheral module registers. vbr is used as a base address of the exception handling (including interrupts) vector table. ? status register (sr) bit bit name default read/ write description 31 to 10 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 9 m undefined r/w used by the div0 u, div0s, and div1 instructions. 8 q undefined r/w used by the div0 u, div0s, and div1 instructions. 7 6 5 4 i3 i2 i1 i0 1 1 1 1 r/w r/w r/w r/w interrupt mask 3, 2 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 1 s undefined r/w s used by the multiply and accumulate instruction. section 2 cpu rev. 5.00 mar. 15, 2007 page 26 of 794 rej09b0237-0500 bit bit name default read/ write description 0 t undefined r/w t indicates true (1) or false (0) in the following instructions: movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, clrt indicates carry, borrow, overflow, or underflow in the following instructions: addv, addc, subv, subc, negc, div0u, div0s, di v1, shar, shal, shlr, shll, rotr, rotl, rotcr, rotcl ? global-base register (gbr) this register indicates a base address in gb r indirect addressing mode. the gbr indirect addressing mode is used for data transfer of the on-chip peripheral module registers and logic operations. ? vector-base register (vbr) this register indicates the base address of the exception handling vector table. 2.2.3 system registers there are four 32-bit sy stem registers, designated two mul tiply and accumulate registers (mach and macl), a procedure register (pr), and program counter (pc). ? multiply and accumulate registers (mac) this register stores the results of multipli cation and multiply-and-accumulate operation. ? procedure register (pr) this register stores the return-destination address from subroutine procedures. ? program counter (pc) the pc indicates the point which is four bytes (two instructions) after the current execution instruction. section 2 cpu rev. 5.00 mar. 15, 2007 page 27 of 794 rej09b0237-0500 2.2.4 initial values of registers table 2.1 lists the initial values of registers after a reset. table 2.1 initial values of registers type of register register default general register r0 to r14 undefined r15 (sp) sp value set in the exception handling vector table control register sr i3 to i0: 1111 (h'f) reserved bits: 0 other bits: undefined gbr undefined vbr h'00000000 system register mach, macl, pr undefined pc pc value set in the exception handling vector table section 2 cpu rev. 5.00 mar. 15, 2007 page 28 of 794 rej09b0237-0500 2.3 data formats 2.3.1 register data format the size of register operands is always longwords (32 bits). when loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register. longword 31 0 figure 2.2 register data format 2.3.2 memory data formats memory data formats are classified into byte, word, and longword. byte data can be accessed from any address. if word data starting from boundary other than 2n or longword data starting from a boundary other than 4n is accessed, an address error will occur. in such cases, the data accessed cannot be guaranteed. see figure 2.3. byte 0 byte 1 byte 2 byte 3 word 0 word 1 longword big endian 31 23 15 7 address a + 1 address a + 4 address a + 8 address a address a address a + 3 address a + 2 0 byte 3 byte 2 byte 1 byte 0 word 1 word 0 longword little endian 31 23 15 7 address a + 10 address a + 4 address a + 8 address a + 11 address a address a + 8 address a + 9 0 figure 2.3 memory data format either big endian and little endian formats can be selected according to the mode pin setting at a reset. for details on mode pin settings, see section 7, bus state controller (bsc). section 2 cpu rev. 5.00 mar. 15, 2007 page 29 of 794 rej09b0237-0500 2.3.3 immediate data formats immediate data of eight bits is placed in the instruction code. for the mov, add, and cmp/eq instructions, the immediate data is sign-extended to longword and then calculated. for the ts t, and, or, and xor instructio ns, the immediate data is zero- extended to longword and then calculated. thus, if the immedi ate data is used for the and instruction, the upper 24 bits in the destination register are always cleared. the immediate data of word or l ongword is not placed in the instruction code . it is placed in a table in memory. the table in memory is accesse d by the mov immediate data instruction in pc relative addressing m ode with displacement. 2.4 features of instructions 2.4.1 risc type the instructions are risc-type instru ctions with the fo llowing features: fixed 16-bit length: all instructions have a fixed length of 16 bits. this improves program code efficiency. one instruction per cycle: since pipelining is used, basic instructions can be executed in one cycle. one cycle is 25ns with 40 mhz operation. data size: the basic data size for operations is longword. byte, word, or longword can be selected as the memory access size. byte or word data in memory is sign-extended to longword and then calculated. immediate data is sign-extended to longword for arithmetic operations or zero-extended to longword si ze for logical operations. table 2.2 word data sign extension cpu in this lsi description example of other cpus mov.w @(disp,pc),r1 add r1,r0 ........ .data.w h'1234 sign-extended to 32 bits, r1 becomes h'00001234, and is then operated on by the add instruction. add.w #h'1234,r0 note: * immediate data is accessed by @(disp,pc). section 2 cpu rev. 5.00 mar. 15, 2007 page 30 of 794 rej09b0237-0500 load/store architecture: basic operations are executed be tween registers. in operations involving memory, data is first loaded into a register (load/store arch itecture). however, bit manipulation instructions such as and are executed dir ectly in memory. delayed branching: unconditional branch instructions mean the delayed branch instructions. with a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. the conditional branch instructions have two types of instructions: conditional branch instructions and delayed branch instructions. table 2.3 delayed branch instructions cpu in this lsi description example of other cpus bra trget add r1,r0 add is executed before branch to trget. add.w r1,r0 bra trget multiply/multiply-and-ac cumulate operations: a 16 16 32 multiply operation is executed in one to two cycles, and a 16 16 + 64 64 multiply-and-accumulate operation in two to three cycles. a 32 32 64 multiply operation and a 32 32 + 64 64 multiply-and- accumulate operation are each execu ted in two to four cycles. t bit: the result of a comparison is indicated by th e t bit in sr, and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum. table 2.4 t bit cpu in this lsi description example of other cpus cmp/ge r1,r0 when r0 r1, the t bit is set. cmp.w r1,r0 bt trget0 when r0 r1, a branch is made to trget0. bge trget0 bf trget1 when r0 < r1, a branch is made to trget1. blt trget1 add # ? 1,r0 the t bit is not c hanged by add. sub.w #1,r0 cmp/eq #0,r0 when r0 = 0, the t bit is set. beq trget bt trget a branch is made when r0 = 0. section 2 cpu rev. 5.00 mar. 15, 2007 page 31 of 794 rej09b0237-0500 immediate data: 8-bit immediate data is placed in the instruction code. word and longword immediate data is not placed in the instruction code. it is placed in a table in memory. the table in memory is accessed with the mov immediate data instruction using pc relative addressing mode with displacement. table 2.5 access to immediate data type this lsi's cpu example of other cpu 8-bit immediate mov #h' 12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ........ .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ........ .data.l h'12345678 mov.l #h'12345678,r 0 note: * immediate data is accessed by @(disp,pc). absolute addresses: when data is accessed by absolute addr ess, place the absolute address value in a table in memory beforehand. the absolute addr ess value is transferred to a register using the method whereby immediate data is loaded when an instruction is executed, and the data is accessed using the register in direct addressing mode. table 2.6 access to absolute address type cpu in this lsi example of other cpus absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 ........ .data.l h'12345678 mov.b @h'12345678,r0 note: * immediate data is referenced by @(disp,pc). 16-bit/32-bit displacement: when data is accessed using th e 16- or 32-bit displacement addressing mode, the displacement value is placed in a table in memory beforehand. using the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is accessed using index register indi rect addressing mode. section 2 cpu rev. 5.00 mar. 15, 2007 page 32 of 794 rej09b0237-0500 table 2.7 access with displacement type cpu in this lsi example of other cpus 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 ........ .data.w h'1234 mov.w @(h'1234,r1),r 2 note: * immediate data is referenced by @(disp,pc). 2.4.2 addressing modes table 2.8 lists addressing modes and effective address calculation methods. table 2.8 addressing modes and effective addresses addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post-increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, and 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn register indirect with pre-decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn - 1/2/4 1/2/4 - rn - 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation) section 2 cpu rev. 5.00 mar. 15, 2007 page 33 of 794 rej09b0237-0500 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. 1/2/4 disp (zero-extended) rn + disp 1/2/4 + rn byte: rn + disp word: rn + disp 2 longword: rn + disp 4 index register indirect @(r0, rn) effective address is sum of register rn and r0 contents. + rn r0 rn + r0 rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 disp (zero-extended) gbr + disp 1/2/4 + byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 index gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr gbr + r0 r0 + gbr + r0 section 2 cpu rev. 5.00 mar. 15, 2007 page 34 of 794 rej09b0237-0500 addressing mode instruction format effective address calculation method calculation formula pc relative with displacement @(disp:8, pc) effective address is pc with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc pc + disp 2 or pc& h'fffffffc + disp 4 h'fffffffc + & 2/4 disp (zero-extended) * * with longword operand word: pc + disp 2 longword: pc&h'fffffffc + disp 4 pc relative disp:8 effective addre ss is pc with 8-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 disp (sign-extended) pc + disp 2 + pc + disp 2 disp:12 effective address is pc with 12-bit displacement disp added after being sign- extended and multiplied by 2. pc 2 disp (sign-extended) pc + disp 2 + pc + disp 2 section 2 cpu rev. 5.00 mar. 15, 2007 page 35 of 794 rej09b0237-0500 addressing mode instruction format effective address calculation method calculation formula pc relative rn effective address is sum of pc and rn. pc pc + rn rn + pc + rn immediate #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? 2.4.3 instruction formats this section describes the instruction formats, and the meaning of the source and destination operands. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement section 2 cpu rev. 5.00 mar. 15, 2007 page 36 of 794 rej09b0237-0500 table 2.9 instruction formats instruction format source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 ? ? nop ? nnnn : register direct movt rn control register or system register nnnn : register direct sts mach,rn n type xxxx nnnn xxxx xxxx 15 0 control register or system register nnnn : pre- decrement register indirect stc.l sr,@-rn mmmm : register direct control register or system register ldc rm,sr mmmm : post- increment register indirect control register or system register ldc.l @rm+,sr mmmm : register indirect ? jmp @rm m type xxxx mmmm xxxx xxxx 15 0 pc relative using rm ? braf rm section 2 cpu rev. 5.00 mar. 15, 2007 page 37 of 794 rej09b0237-0500 instruction format source operand destination operand sample instruction mmmm : register direct nnnn : register direct add rm,rn mmmm : register direct nnnn : register indirect mov.l rm,@rn mmmm : post- increment register indirect (multiply- and-accumulate operation) nnnn : * post- increment register indirect (multiply- and-accumulate operation) mach, macl mac.w @rm+,@rn+ mmmm : post- increment register indirect nnnn : register direct mov.l @rm+,rn mmmm : register direct nnnn : pre- decrement register indirect mov.l rm,@-rn nm type xxxx nnnn mmmm xxxx 15 0 mmmm : register direct nnnn : index register indirect mov.l rm,@(r0,rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd : register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type xxxx xxxx nnnn dddd 15 0 r0 (register direct) nnnndddd : register indirect with displacement mov.b r0,@(disp,rn) mmmm : register direct nnnndddd : register indirect with displacement mov.l rm,@(disp,rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmmdddd : register indirect with displacement nnnn : register direct mov.l @(disp,rm),rn section 2 cpu rev. 5.00 mar. 15, 2007 page 38 of 794 rej09b0237-0500 instruction format source operand destination operand sample instruction dddddddd : gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r0 r0 (register direct) dddddddd : gbr indirect with displacement mov.l r0,@(disp,gbr) dddddddd : pc relative with displacement r0 (register direct) mova @(disp,pc),r0 d type xxxx xxxx dddd dddd 15 0 ? dddddddd : pc relative bf label d12 type xxxx dddd dddd dddd 15 0 ? dddddddddddd : pc relative bra label (label=disp+pc) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd : pc relative with displacement nnnn : register direct mov.l @(disp,pc),rn iiiiiiii : immediate index gbr indirect and.b #imm,@(r0,gbr) iiiiiiii : immediate r0 (register direct) and #imm,r0 i type xxxx xxxx iiii iiii 15 0 iiiiiiii : immediate ? trapa #imm ni type xxxx nnnn iiii iiii 15 0 iiiiiiii : immediate nnnn : register direct add #imm,rn note: * in multiply and accumulate instructions, nnnn is the source register. section 2 cpu rev. 5.00 mar. 15, 2007 page 39 of 794 rej09b0237-0500 2.5 instruction set 2.5.1 instruction set by type table 2.10 lists the instruct ions classified by type. table 2.10 instruction types type kinds of instruction op code function number of instructions mov data transfer immediate data transfer peripheral module data transfer structure data transfer mova effective address transfer movt t bit transfer swap upper/lower swap data transfer instructions 5 xtrct extraction of middl e of linked registers 39 add binary addition addc binary addition with carry addv binary addition with overflow cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double- precision multiply-and-accumulate arithmetic operation instructions 21 mul double-precision multiplication 33 section 2 cpu rev. 5.00 mar. 15, 2007 page 40 of 794 rej09b0237-0500 type kinds of instruction op code function number of instructions muls signed multiplication mulu unsigned multiplication neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with carry arithmetic operation instructions 21 subv binary subtraction with underflow 33 and logical and not bit inversion or logical or tas memory test and bit setting tst t bit setting for logical and logic operation instructions 6 xor exclusive logical or 14 rotl 1-bit left shift rotr 1-bit right shift rotcl 1-bit left shift with t bit rotcr 1-bit right shift with t bit shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shift instructions 10 shlrn logical n-bit right shift 14 section 2 cpu rev. 5.00 mar. 15, 2007 page 41 of 794 rej09b0237-0500 type kinds of instruction op code function number of instructions bf conditional branch, delayed conditional branch (t = 0) bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure branch instructions 9 rts return from subroutine procedure 11 clrt t bit clear clrmac mac register clear ldc load into control register lds load into system register nop no operation rte return from exception handling sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register system control instructions 11 trapa trap exception handling 31 total: 62 142 section 2 cpu rev. 5.00 mar. 15, 2007 page 42 of 794 rej09b0237-0500 the instruction code, operation, an d execution cycles of the instruc tions are listed in the following tables, classified by type. instruction instruction code summary of operation execution cycles t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 2 indicated in msb ? lsb order. explanation of symbols mmmm: source register nnnn: destination register 0000: r0 0001: r1 ......... 1111: r15 iiii: immediate data dddd: displacement indicates summary of operation. explanation of symbols , : transfer direction (xx): memory operand m/q/t: flag bits in sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ?: logical not of each bit < section 2 cpu rev. 5.00 mar. 15, 2007 page 43 of 794 rej09b0237-0500 ? data transfer instructions instruction operation code execution cycles t bit mov #imm,rn imm sign extension rn 1110nnnniiiiiiii 1 ? mov.w @(disp,pc),rn (disp 2 + pc) sign extension rn 1001nnnndddddddd 1 ? mov.l @(disp,pc),rn (disp 4 + pc) rn 1101nnnndddddddd 1 ? mov rm,rn rm rn 0110nnnnmmmm0011 1 ? mov.b rm,@rn rm (rn) 0010nnnnmmmm0000 1 ? mov.w rm,@rn rm (rn) 0010nnnnmmmm0001 1 ? mov.l rm,@rn rm (rn) 0010nnnnmmmm0010 1 ? mov.b @rm,rn (rm) sign extension rn 0110nnnnmmmm0000 1 ? mov.w @rm,rn (rm) sign extension rn 0110nnnnmmmm0001 1 ? mov.l @rm,rn (rm) rn 0110nnnnmmmm0010 1 ? mov.b rm,@ ? rn rn?1 rn, rm (rn) 0010nnnnmmmm0100 1 ? mov.w rm,@ ? rn rn?2 rn, rm (rn) 0010nnnnmmmm0101 1 ? mov.l rm,@ ? rn rn?4 rn, rm (rn) 0010nnnnmmmm0110 1 ? mov.b @rm+,rn (rm) sign extension rn, rm + 1 rm 0110nnnnmmmm0100 1 ? mov.w @rm+,rn (rm) sign extension rn, rm + 2 rm 0110nnnnmmmm0101 1 ? mov.l @rm+,rn (rm) rn,rm + 4 rm 0110nnnnmmmm0110 1 ? mov.b r0,@(disp,rn) r0 (disp + rn) 10000000nnnndddd 1 ? mov.w r0,@(disp,rn) r0 (disp 2 + rn) 10000001nnnndddd 1 ? mov.l rm,@(disp,rn) rm (disp 4 + rn) 0001nnnnmmmmdddd 1 ? mov.b @(disp,rm),r0 (disp + rm) sign extension r0 10000100mmmmdddd 1 ? mov.w @(disp,rm),r0 (disp 2 + rm) sign extension r0 10000101mmmmdddd 1 ? mov.l @(disp,rm),rn (disp 4 + rm) rn 0101nnnnmmmmdddd 1 ? mov.b rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0100 1 ? mov.w rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0101 1 ? section 2 cpu rev. 5.00 mar. 15, 2007 page 44 of 794 rej09b0237-0500 instruction operation code execution cycles t bit mov.l rm,@(r0,rn) rm (r0 + rn) 0000nnnnmmmm0110 1 ? mov.b @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1100 1 ? mov.w @(r0,rm),rn (r0 + rm) sign extension rn 0000nnnnmmmm1101 1 ? mov.l @(r0,rm),rn (r0 + rm) rn 0000nnnnmmmm1110 1 ? mov.b r0,@(disp,gbr) r0 (disp + gbr) 11000000dddddddd 1 ? mov.w r0,@(disp,gbr) r0 (disp 2 + gbr) 11000001dddddddd 1 ? mov.l r0,@(disp,gbr) r0 (disp 4 + gbr) 11000010dddddddd 1 ? mov.b @(disp,gbr),r0 (disp + gbr) sign extension r0 11000100dddddddd 1 ? mov.w @(disp,gbr),r0 (disp 2 + gbr) sign extension r0 11000101dddddddd 1 ? mov.l @(disp,gbr),r0 (disp 4 + gbr) r0 11000110dddddddd 1 ? mova @(disp,pc),r0 disp 4 + pc r0 11000111dddddddd 1 ? movt rn t rn 0000nnnn00101001 1 ? swap.b rm,rn rm swap lowest two bytes rn 0110nnnnmmmm1000 1 ? swap.w rm,rn rm swap two consecutive words rn 0110nnnnmmmm1001 1 ? xtrct rm,rn rm: middle 32 bits of rn rn 0010nnnnmmmm1101 1 ? section 2 cpu rev. 5.00 mar. 15, 2007 page 45 of 794 rej09b0237-0500 ? arithmetic operation instructions instruction operation code execution cycles t bit add rm,rn rn + rm rn 0011nnnnmmmm1100 1 ? add #imm,rn rn + imm rn 0111nnnniiiiiiii 1 ? addc rm,rn rn + rm + t rn, carry t 0011nnnnmmmm1110 1 carry addv rm,rn rn + rm rn, overflow t 0011nnnnmmmm1111 1 overflow cmp/eq #imm,r0 if r0 = imm, 1 t 10001000iiiiiiii 1 comparison result cmp/eq rm,rn if rn = rm, 1 t 0011nnnnmmmm0000 1 comparison result cmp/hs rm,rn if rn rm with unsigned data, 1 t 0011nnnnmmmm0010 1 comparison result cmp/ge rm,rn if rn rm with signed data, 1 t 0011nnnnmmmm0011 1 comparison result cmp/hi rm,rn if rn > rm with unsigned data, 1 t 0011nnnnmmmm0110 1 comparison result cmp/gt rm,rn if rn > rm with signed data, 1 t 0011nnnnmmmm0111 1 comparison result cmp/pz rn if rn 0, 1 t 0100nnnn00010001 1 comparison result cmp/pl rn if rn > 0, 1 t 0100nnnn00010101 1 comparison result cmp/str rm,rn if rn and rm have an equivalent byte, 1 t 0010nnnnmmmm1100 1 comparison result div1 rm,rn single-step division (rn/rm) 0011nnnnmmmm0100 1 calculation result div0s rm,rn msb of rn q, msb of rm m, m^ q t 0010nnnnmmmm0111 1 calculation result div0u 0 m/q/t 0000000000011001 1 0 dmuls.l rm,rn signed operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm1101 2 to 5 * ? section 2 cpu rev. 5.00 mar. 15, 2007 page 46 of 794 rej09b0237-0500 instruction operation code execution cycles t bit dmulu.l rm,rn unsigned operation of rn rm mach, macl 32 32 64 bits 0011nnnnmmmm0101 2 to 5 * ? dt rn rn - 1 rn, if rn = 0, 1 t, else 0 t 0100nnnn00010000 1 comparison result exts.b rm,rn a byte in rm is sign- extended rn 0110nnnnmmmm1110 1 ? exts.w rm,rn a word in rm is sign- extended rn 0110nnnnmmmm1111 1 ? extu.b rm,rn a byte in rm is zero- extended rn 0110nnnnmmmm1100 1 ? extu.w rm,rn a word in rm is zero- extended rn 0110nnnnmmmm1101 1 ? mac.l @rm+,@rn+ signed operation of (rn) (rm) + mac mac, 32 32 + 64 64 bits 0000nnnnmmmm1111 2 to 5 * ? mac.w @rm+,@rn+ signed operation of (rn) (rm) + mac mac, 16 16 + 64 64 bits 0100nnnnmmmm1111 2 to 4 * ? mul.l rm,rn rn rm macl 32 32 32 bits 0000nnnnmmmm0111 2 to 5 * ? muls.w rm,rn signed operation of rn rm mac 16 16 32 bits 0010nnnnmmmm1111 1 (3) * ? mulu.w rm,rn unsigned operation of rn rm mac 16 16 32 bits 0010nnnnmmmm1110 1 (3) * ? neg rm,rn 0-rm rn 0110nnnnmmmm1011 1 ? negc rm,rn 0-rm-t rn, borrow t 0110nnnnmmmm1010 1 borrow sub rm,rn rn-rm rn 0011nnnnmmmm1000 1 ? subc rm,rn rn-rm?t rn, borrow t 0011nnnnmmmm1010 1 borrow section 2 cpu rev. 5.00 mar. 15, 2007 page 47 of 794 rej09b0237-0500 instruction operation code execution cycles t bit subv rm,rn rn-rm rn, underflow t 0011nnnnmmmm1011 1 overflow note: * indicates the number of execution cycles for normal o peration. the values in parentheses indicate the number of exec ution cycles when conf licts occur with the previous or next instruction. ? logic operation instructions instruction operation code execution cycles t bit and rm,rn rn & rm rn 0010nnnnmmmm1001 1 ? and #imm,r0 r0 & imm r0 11001001iiiiiiii 1 ? and.b #imm,@(r0,gbr) (r0 + gbr) & imm (r0 + gbr) 11001101iiiiiiii 3 ? not rm,rn ~rm rn 0110nnnnmmmm0111 1 ? or rm,rn rn | rm rn 0010nnnnmmmm1011 1 ? or #imm,r0 r0 | imm r0 11001011iiiiiiii 1 ? or.b #imm,@(r0,gbr) (r0 + gbr) | imm (r0 + gbr) 11001111iiiiiiii 3 ? tas.b @rn if (rn) is 0, 1 t; 1 msb of (rn) 0100nnnn00011011 4 test result tst rm,rn rn & rm; if the result is 0, 1 t 0010nnnnmmmm1000 1 test result tst #imm,r0 r0 & imm; if the result is 0, 1 t 11001000iiiiiiii 1 test result tst.b #imm,@(r0,gbr) (r0 + gbr) & imm; if the result is 0, 1 t 11001100iiiiiiii 3 test result xor rm,rn rn ^ rm rn 0010nnnnmmmm1010 1 ? xor #imm,r0 r0 ^ imm r0 11001010iiiiiiii 1 ? xor.b #imm,@(r0,gbr) (r0 + gbr) ^ imm (r0 + gbr) 11001110iiiiiiii 3 ? section 2 cpu rev. 5.00 mar. 15, 2007 page 48 of 794 rej09b0237-0500 ? shift instructions instruction operation code execution cycles t bit rotl rn t rn msb 0100nnnn00000100 1 msb rotr rn lsb rn t 0100nnnn00000101 1 lsb rotcl rn t rn t 0100nnnn00100100 1 msb rotcr rn t rn t 0100nnnn00100101 1 lsb shal rn t rn 0 0100nnnn00100000 1 msb shar rn msb rn t 0100nnnn00100001 1 lsb shll rn t rn 0 0100nnnn00000000 1 msb shlr rn 0 rn t 0100nnnn00000001 1 lsb shll2 rn rn << 2 rn 0100nnnn00001000 1 ? shlr2 rn rn >> 2 rn 0100nnnn00001001 1 ? shll8 rn rn << 8 rn 0100nnnn00011000 1 ? shlr8 rn rn >> 8 rn 0100nnnn00011001 1 ? shll16 rn rn << 16 rn 0100nnnn00101000 1 ? shlr16 rn rn >> 16 rn 0100nnnn00101001 1 ? ? branch instructions instruction operation code execution cycles t bit bf label if t = 0, disp 2 + pc pc; if t = 1, nop 10001011dddddddd 3/1 * ? bf/s label delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 10001111dddddddd 2/1 * ? bt label if t = 1, disp 2 + pc pc; if t = 0, nop 10001001dddddddd 3/1 * ? bt/s label delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 10001101dddddddd 2/1 * ? section 2 cpu rev. 5.00 mar. 15, 2007 page 49 of 794 rej09b0237-0500 instruction operation code execution cycles t bit bra label delayed branch, disp 2 + pc pc 1010dddddddddddd 2 ? braf rm delayed branch, rm + pc pc 0000mmmm00100011 2 ? bsr label delayed branch, pc pr, disp 2 + pc pc 1011dddddddddddd 2 ? bsrf rm delayed branch, pc pr, rm + pc pc 0000mmmm00000011 2 ? jmp @rm delayed branch, rm pc 0100mmmm00101011 2 ? jsr @rm delayed branch, pc pr, rm pc 0100mmmm00001011 2 ? rts delayed branch, pr pc 0000000000001011 2 ? note: * one cycle when the branch is not executed. ? system control instructions instruction operation code execution cycles t bit clrt 0 t 0000000000001000 1 0 clrmac 0 mach, macl 0000000000101000 1 ? ldc rm,sr rm sr 0100mmmm00001110 6 lsb ldc rm,gbr rm gbr 0100mmmm00011110 4 ? ldc rm,vbr rm vbr 0100mmmm00101110 4 ? ldc.l @rm+,sr (rm) sr, rm + 4 rm 0100mmmm00000111 8 lsb ldc.l @rm+,gbr (rm) gbr, rm + 4 rm 0100mmmm00010111 4 ? ldc.l @rm+,vbr (rm) vbr, rm + 4 rm 0100mmmm00100111 4 ? lds rm,mach rm mach 0100mmmm00001010 1 ? lds rm,macl rm macl 0100mmmm00011010 1 ? lds rm,pr rm pr 0100mmmm00101010 1 ? lds.l @rm+,mach (rm) mach, rm + 4 rm 0100mmmm00000110 1 ? lds.l @rm+,macl (rm) macl, rm + 4 rm 0100mmmm00010110 1 ? section 2 cpu rev. 5.00 mar. 15, 2007 page 50 of 794 rej09b0237-0500 instruction operation code execution cycles t bit lds.l @rm+,pr (rm) pr, rm + 4 rm 0100mmmm00100110 1 ? nop no operation 0000000000001001 1 ? rte delayed branch, stack area pc/sr 0000000000101011 5 ? sett 1 t 0000000000011000 1 1 sleep sleep 0000000000011011 4 * ? stc sr,rn sr rn 0000nnnn00000010 1 ? stc gbr,rn gbr rn 0000nnnn00010010 1 ? stc vbr,rn vbr rn 0000nnnn00100010 1 ? stc.l sr,@ ? rn rn?4 rn, sr (rn) 0100nnnn00000011 1 ? stc.l gbr,@ ? rn rn?4 rn, gbr (rn) 0100nnnn00010011 1 ? stc.l vbr,@ ? rn rn?4 rn, vbr (rn) 0100nnnn00100011 1 ? sts mach,rn mach rn 0000nnnn00001010 1 ? sts macl,rn macl rn 0000nnnn00011010 1 ? sts pr,rn pr rn 0000nnnn00101010 1 ? sts.l mach,@ ? rn rn?4 rn, mach (rn) 0100nnnn00000010 1 ? sts.l macl,@ ? rn rn?4 rn, macl (rn) 0100nnnn00010010 1 ? sts.l pr,@ ? rn rn?4 rn, pr (rn) 0100nnnn00100010 1 ? trapa #imm pc / sr stack area, (imm 4 + vbr) pc 11000011iiiiiiii 8 ? note: * number of execution cycles unt il this lsi enters sleep mode. about the number of execution cycles: the table lists the minimum number of ex ecution cycles. in practice, the number of execution cycles will be increased d epending on t he conditions such as: ? when there is a conflict between instruction fetch and data access ? when the destination register of a load instruction (memory register) is also used by the instruction immediatel y after the load instruction. section 2 cpu rev. 5.00 mar. 15, 2007 page 51 of 794 rej09b0237-0500 2.6 processing states 2.6.1 state transition the cpu has the four processing states: reset, exception handling, program execution, and power- down. figure 2.4 shows the cpu state transition. note that some products do not support the manual reset function and the mres pin. software standby mode res = 0 in any state res = 1 and mres = 0 in any state power-on reset state manual reset state reset state request for internal power-on reset or internal manual reset by the wdt exception handling state request for exception handling end of exception handling program execution state sleep instruction by clearing ssby bit sleep instruction by setting ssby bit sleep mode request for nmi or irq interrupt power-down mode figure 2.4 cpu state transition section 2 cpu rev. 5.00 mar. 15, 2007 page 52 of 794 rej09b0237-0500 ? reset state the cpu is reset. when the res pin is driven low, the cpu enters the power-on reset state. when the res pin is high and mres pin is low, the cpu enters the manual reset state. ? exception handling state this state is a transitional state in which the cpu processing state changes due to a request for exception handling such as a reset or an interrupt. when a reset occurs, the execu tion start address as the initial value of the program counter (pc) and the initial value of the stack pointer (sp) are fetched from the exception handling vector table. then, a branch is made fo r the start address to execute a program. when an interrupt occurs, the pc and status regist er (sr) are saved in the stack area pointed to by sp. the start address of an exception handling routine is fetched from the exception handling vector table and a branch to th e address is made to execute a program. then the processing state enters the program execution state. ? program execution state the cpu executes programs sequentially. ? power-down state the cpu stops to reduce power consumption. the sleep instruction makes the cpu enter sleep mode or software standby mode. section 3 cache rev. 5.00 mar. 15, 2007 page 53 of 794 rej09b0237-0500 section 3 cache 3.1 features ? capacity: 16 kbytes ? structure: instructions/data un ified, 4-way set associative ? line size: 16 bytes ? number of entries: 256 entries/way in 16-kbyte mode ? write method: write-back/write-through is selectable ? replacement method: least-r ecently-used (lru) algorithm 3.1.1 cache structure the cache holds both instructions and data and employs a 4-way set associative system. it is composed of four ways (banks), and each of which is divided into an address section and a data section. each of the address and data sections is divided into 256 entries. the data of an entry is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 4 kbytes (16 bytes 256 entries), with a total of 16 kbytes in the cache (4 ways). figure 3.1 shows the cache structure. 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 to lw3: longword data 0 to 3 entry 0 entry 1 entry 255 0 1 255 0 1 255 v u tag address lw0 lw1 lw2 lw3 address array (ways 0 to 3) data array (ways 0 to 3) lru . . . . . . . . . . . . . . . . . . figure 3.1 cache structure section 3 cache rev. 5.00 mar. 15, 2007 page 54 of 794 rej09b0237-0500 address array: the v bit indicates whether or not the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether or not the entry has been written to in write-back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the tag address is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. in this lsi, the upper three bits of 32 address bits are used as shadow bits (see section 7, bus state controller (bsc)), therefore, the upper three bits of the ta g address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset. the tag address is not initialized by a power-on reset. data array: holds 16-byte instruction and data. entries are registered in the cache in line units (16 bytes). the data array is not initialized by a power-on reset. lru: with the 4-way set associative system, up to fo ur instructions or data with the same entry address can be registered in the cache. when an entry is register ed, lru shows which of the four ways it is registered in. there are six lru bits , controlled by hardware. the least-recently-used (lru) algorithm is used to select the way. when a cache miss occurs, six lru bits indicate the way to be replaced. if a bit pattern other than those listed in table 3.1 is set in the lru bits by software, the cache will not function correctly. when changing the lru bits by software, set one of the patterns listed in table 3.1. the lru bits are initialized to 000000 by a power-on reset. table 3.1 lru and way to be replaced lru (bits 5 to 0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 section 3 cache rev. 5.00 mar. 15, 2007 page 55 of 794 rej09b0237-0500 3.1.2 divided areas and cache a 4-g byte address space is divide d into five areas with the arch itecture of this lsi. the cache access methods can be specified for each area. table 3.2 lists the corresponden ce between the divided areas and cache. table 3.2 correspondence between divided areas and cache address area cacheable cache operating control h'00000000 to h'7fffffff p0 ca cheable wt bit in ccr1 h'80000000 to h'9fffffff p1 ca cheable cb bit in ccr1 h'a0000000 to h'bfffffff p2 non cacheable ? h'c0000000 to h'dfffffff p3 cacheable wt bit in ccr1 h'e0000000 to h'ffffffff p4 n on cacheable (internal i/o) ? section 3 cache rev. 5.00 mar. 15, 2007 page 56 of 794 rej09b0237-0500 3.2 register descriptions the cache has the following registers. for details on register addresses and register states during each process, refer to sectio n 24, list of registers. ? cache control register 1 (ccr1) 3.2.1 cache control register 1 (ccr1) the cache is enabled or disabled by the ce bit in ccr1. ccr1 also has the cf bit (which invalidates all cache entries), and the wt and cb bits (which select either write-through mode or write-back mode). programs that change the cont ents of ccr1 should be placed in the address space that is not cached. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 cf 0 r/w cache flush writing 1 flushes all cache entries meaning that it clears the v, u, and lru bits of all cache entries to 0. this bit is always read as 0. write-back to external memory is not performed when the cache is flushed. 2 cb 0 r/w write-back indicates the cache operating mode for h'80000000 to h'9fffffff. 0: write-through mode 1: write-back mode 1 wt 0 r/w write-through indicates the cache operating mode for h'00000000 to h'7fffffff and h'c0 000000 to h'dfffffff. 0: write-back mode 1: write-through mode section 3 cache rev. 5.00 mar. 15, 2007 page 57 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 ce 0 r/w cache enable indicates whether or not t he cache function is used. 0: cache function is not used. 1: cache function is used. 3.3 operation 3.3.1 searching cache if the cache is enabled (the ce bit in ccr1 is set to 1), whenever an instruction or data in h'00000000 to h'7fffffff, h' 8000000 to h'9fffffff, and h' c0000000 to h'dfffffff is accessed, the cache will be searched to see if the de sired instruction or data is in the cache. figure 3.2 illustrates the method by which the cache is searched. entries are selected using bits 11 to 4 of the memory access addr ess and the tag address of that entry is read. the address comparison is performe d on all four ways. when the comparison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 3.2 shows a hit on way 1. section 3 cache rev. 5.00 mar. 15, 2007 page 58 of 794 rej09b0237-0500 0 1 255 v u tag address lw0 lw1 lw2 lw3 ways 0 to 3 ways 0 to 3 31 12 11 4 3 2 10 address cmp0 cmp1 cmp2 cmp3 cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection figure 3.2 cache search scheme 3.3.2 read access read hit: in a read access, instructions and data are transferred from the cache to the cpu. the lru bits are updated so that they po int to the most recently hit way. read miss: an external bus cycle starts and the entry is updated. the way to be replaced is shown in table 3.1. data is updated in units of 16 bytes by updating the entry. when the desired instruction or data is loaded from external me mory to the cache, the instruction or data is transferred to the cpu in parallel. when it is load ed to the cache, the u b it is cleared to 0, the v bit is set to 1, the lru bits are updated so that they point to the most recently hit way. when the u bit of the entry which is to be replaced by entry updating in write-back mode is 1, the cache- update cycle starts after the entry is transferred to the write-back buffer . after the cache completes its update cycle, the write-back buffer writes the en try back to the memory. transfer is in 16-byte units. section 3 cache rev. 5.00 mar. 15, 2007 page 59 of 794 rej09b0237-0500 3.3.3 write access write hit: in a write access in write-back mode, the data is written to the cache and no external memory write cycle is generated. the u bit of the entry that has been written to is set to 1, and the lru bits are updated to indicate that the hit way is the most recently hit way. in write-through mode, the data is written to the cache and an extern al memory write cycle is generated. the u bit of the entry that has been written to is not updated, and the lru bits are updated to indicate that the hit way is the most recently hit way. write miss: in write-back mode, an external write cycl e starts when a write miss occurs, and the entry is updated. the way to be replaced is shown in table 3.1. when the u bit of the entry which is to be replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to the write-back buffer. data is written to the cache and the u bit and the v bit are set to 1. the lru bits are updated to indicate that the replaced way is the mo st recently updated way. after the cache has completed its update cycle, th e write-back buffer writes the entry back to the memory. transfer is in 16-byte un its. in write-through mode, no wr ite to cache occurs in a write miss; the write is only to the external memory. 3.3.4 write-back buffer when the u bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. to increas e performance, the entry to be re placed is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. after the fetching of new entrie s to the cache completes, the write-back buffer writes the entry back to the external memory. during the write-back cycles, the cache can be accessed. the write-back buffer can hold one line of cache data (16 bytes) and its physical address. figure 3.3 shows the configuration of the write-back buffer. longword 0 longword 1 longword 2 longword 3 pa (31 to 4) pa (31 to 4): longword 0 to 3: physical address to be written to external memory one line of cache data to be written to external memory figure 3.3 write-back buffer configuration 3.3.5 coherency of cach e and external memory coherency between the cache and the external memory must be ensured by software. when memory shared by this lsi and another device is allocated to a cacheable address space, invalidate and write back the cache by accessing the memory -mapped cache, as required. memory that is shared by the cpu, dmac, and e-dmac of this lsi should also be handled in this way. section 3 cache rev. 5.00 mar. 15, 2007 page 60 of 794 rej09b0237-0500 3.4 memory-mapped cache to allow software management of the cache, cache co ntents can be read from or written to by the mov instructions. the address array is allocated to addresses h'f0000000 to h'f0ffffff, and the data array to addresses h'f1000000 to h'f1ffffff. the address array and data array must be accessed in longwords, and instruc tion fetches cannot be performed. 3.4.1 address array the address array is allocated to h'f0000000 to h'f0ffffff. to access an address array, the 32- bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifi es information for se lecting the entry to be accessed; the data field specifies the tag address, v bit, u bit, an d lru bits to be written to the address array. in the address field, specify the entry address for selecting the entry, w for selecting the way, a for enabling or disabling the a ssociative operation, and h'f0 for indicating address array access. as for w, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. in the data field, specify the tag address, lru b its, u bit, and v bit. alwa ys clear the upper three bits (bits 31 to 29) of the tag address to 0. figure 3.4 shows the address and data formats. the following three operations are av ailable in the address array. address-array read: read the tag address, lru bits, u bit, and v bit for the entry that corresponds to the en try address and way specified by the address field of the read instruction. in reading, the associative operation is not performe d, regardless of whether the associa tive bit (a bit) specified in the address is 1 or 0. address-array write (non-associative operation): write the tag address, lru bits, u bit, and v bit, specified by the data field of the write inst ruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. ensure that the associative bit (a bit) in the address field is set to 0. when writing to a cache line for which the u bit = 1 and the v bit =1, write the contents of the cache line back to memory, then write the tag address, lru bits, u bit, and v b it specified by the data field of the write instruction. when 0 is written to the v bit, 0 must also be written to the u bit for that entry. section 3 cache rev. 5.00 mar. 15, 2007 page 61 of 794 rej09b0237-0500 address-array write (associative operation): when writing with the associative bit (a bit) of the address field set to 1, the addresses in the four ways for the entry specified by the address field of the write instruction are compared with the tag ad dress that is specified by the data field of the write instruction. write the u bit and the v bit specified by the data field of the write instruction to the entry of the way that has a hit. however, the tag address and lru bits remain unchanged. when there is no way that has a hit, nothing is written and there is no operation. this function is used to invalidate a specific entry in the cache. when the u bit of the entry that has had a hit is 1 at this time, writing back should be performed. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. 3.4.2 data array the data array is allocated to h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write acce sses) must be specified. the address field specifies info rmation for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. in the address field, specify the entry address for selecting the entry, l for indicating the longword position within the (16-byte) line, w for selecting the way, and h'f1 for indicating data array access. as for l, 00 indicates longword 0, 01 indi cates longword 1, 10 in dicates longword 2, and 11 indicates longword 3. as for w, 00 indi cates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3. since access size of the data array is fixed at longwo rd, bits 1 and 0 of the address field should be set to 00. figure 3.4 shows the address and data formats. the following two operations on the data array ar e available. the information in the address array is not affected by these operations. data-array read: read the data specified by l of the address field, from the entry that corresponds to th e entry address and the way that is specified by the address field. data-array write: write the longword data specified by the data field, to the position specified by l of the address field, in th e entry that corresponds to the en try address and the way specified by the address field. section 3 cache rev. 5.00 mar. 15, 2007 page 62 of 794 rej09b0237-0500 (1) address array access (a) address specification read access write access (b) data specification (both read and write accesses) (2) data array access (both read and write accesses) (a) address specification 1111 0000 * -------- * w entry address 1111 0000 * -------- * w entry address a 31 30 29 10 4 3 0 lru 2 x 00 0 x 9 tag address (28 to 10) u v 1 31 24 23 14 13 12 11 4 3 0 1111 0001 * -------- * w entry address 1 2 l (b) data specification 31 0 longword [legend] * : don't care x: 0 for read, don't care for write 0 00 28 * 0 0 31 24 23 14 13 12 11 4 3 0 1 2 31 24 23 14 13 12 11 4 3 0 1 2 * 00 figure 3.4 specifying a ddress and data for memo ry-mapped cache access section 3 cache rev. 5.00 mar. 15, 2007 page 63 of 794 rej09b0237-0500 3.4.3 usage examples invalidating specific entries: specific cache entries can be invalidated by writing 0 to the entry's v bit in the memory-mapped cache access. when the a bit is 1, the tag address specified by the write data is compared to the tag address within the cache selected by the entry address, and the v bit and u bit specified by the write data are written when a match is found. if no match is found, there is no operation. when the v bit of an entry in the address array is set to 0, the entry is written back if the entry's u bit is 1. in the example shown below, r0 specifies the write data and r1 specifies the address. ; r0=h'01100010; vpn=b'0000 0001 0001 0000 0000 00, u=0, v=0 ; r1=h'f0000088; address array access, entry=b'00001000, a=1 ; mov.l r0,@r1 reading data of specific entry: the data section of a specific entry can be read from by the memory-mapped cache access. the longword indicated in the data field of the data array in figure 3.4 is read into the register. in the exam ple shown below, r0 specifies the address and r1 shows what is read. ; r0=h'f100004c; data array access, entry=b'00000100 ; way = 0, longword address = 3 ; mov.l @r0,r1 ; longword 3 is read. section 3 cache rev. 5.00 mar. 15, 2007 page 64 of 794 rej09b0237-0500 section 4 u memory rev. 5.00 mar. 15, 2007 page 65 of 794 rej09b0237-0500 section 4 u memory this lsi has on-chip u memory which can be used to store instructions and data. 4.1 features features of the u memory are shown below. ? size 16 kbytes ? address h'e55f_c000 to h'e55f_ffff ? priority the u memory can be accessed from the i bu s by the dmac and e-dmac and from the l bus by the cpu. in the event of simultaneous accesses from di fferent buses, the accesses are processed according to the priority. the priority is: i bus > l bus. 4.2 usage notes in sleep mode, the u memory cannot be accessed by the dmac and e-dmac. section 4 u memory rev. 5.00 mar. 15, 2007 page 66 of 794 rej09b0237-0500 section 5 exception handling rev. 5.00 mar. 15, 2007 page 67 of 794 rej09b0237-0500 section 5 exception handling 5.1 overview 5.1.1 types of exception handling and priority exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. when se veral exceptions are detected at once, they are processed according to the priority. table 5.1 types of exceptions and priority exception exception source priority reset power-on reset high h-udi reset interrupt user break (break bef ore instruction execution) address error cpu address error (instruction fetch) instruction general illegal inst ructions (undefined code) illegal slot instruction (undefined code placed immediately after a delayed branch instruction * 1 or instruction that changes the pc value * 2 ) trap instruction (trapa instruction) address error cpu address error (data access) interrupt user break (break after in struction execution or operand break) nmi h-udi irq watchdog timer (wdt) ether controller (etherc and e-dmac) on-chip peripheral modules compare match timer 0 and 1 (cmt0 and cmt1) serial communication interface with fifo (scif0, scif1, and scif2) host interface (hif) low section 5 exception handling rev. 5.00 mar. 15, 2007 page 68 of 794 rej09b0237-0500 exception exception source priority interrupt direct memory access controller (dmac0, dmac1 dmac2, and dmac3) high on-chip peripheral modules serial i/o with fifo (siof) low notes: 1. delayed branch instructions: jmp, js r, bra, bsr, rts, rte, bf/s, bt/s, bsrf, and braf. 2. instructions that change the pc value: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf, ldc rm,sr, ldc.l @rm+,sr. 5.1.2 exception handling operations the exceptions are detected and the exception ha ndling starts according to the timing shown in table 5.2. table 5.2 timing for exception detect ion and start of exception handling exception timing of source detect ion and start of exception handling reset power-on reset started when the res pin changes from low to high or when the wdt overflows. h-udi reset started when the reset assert command and the reset negate command are input to the h-udi in this order. address error interrupt detected during the instruction decode stage and started after the execution of the current in struction is completed. instruction trap instruction started by the ex ecution of the tr apa instruction. general illegal instructions started when an undefined code pl aced at other than a delay slot (immediately after a delayed branch instruction) is decoded. illegal slot instructions started when an undefined code placed at a delay slot (immediately after a delayed branch instruction) or an instruction that changes the pc value is detected. when exception handling starts, the cpu operates exception handling triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched fr om the exception handling vector table (pc from the address h'a0000000 and sp from the address h'a0000004). for details, see section 5.1.3, exception handling vector table. h'00000000 is then written to the vector base register (vbr), and h'f (b'1111) is written to the interrupt mask bits (i 3 to i0) in the status register (sr). the program starts from the pc address fetched from the exception handling vector table. section 5 exception handling rev. 5.00 mar. 15, 2007 page 69 of 794 rej09b0237-0500 exception handling triggered by addres s error, interrupt, and instruction: sr and pc are saved to the stack indicated by r15. for interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (i3 to i0) in sr. for address error and instruction exception handling, bits i3 to i0 are not affected. the start address is then fetched from the exception handling vector table and the program starts from that address. 5.1.3 exception handling vector table before exception handling starts, the exception handling vector table must be set in memory. the exception handling vector table stores the start addresses of exception handling routines. (the reset exception handling table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector tabl e address offsets. the vector table addresses are calculated from these v ector numbers and vector table address offsets. during exception handling, the start addresses of the exception handling routines are fetched from the exception handling vector table that is indicated by this vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 vector numbers and vector table address offsets exception handling source vector numb er vector table address offset power-on reset pc 0 h'00000000 to h'00000003 h-udi reset sp 1 h'00000004 to h'00000007 (reserved by system) 2 h'00000008 to h'0000000b 3 h'0000000c to h'0000000f general illegal instructio n 4 h'00000010 to h'00000013 (reserved by system) 5 h'00000014 to h'00000017 illegal slot instruction 6 h'00000018 to h'0000001b (reserved by system) 7 h'0000001c to h'0000001f 8 h'00000020 to h'00000023 cpu address error 9 h'00000024 to h'00000027 (reserved by system) 10 h'00000028 to h'0000002b interrupt nmi 11 h'0000002c to h'0000002f user break 12 h'00000030 to h'00000033 h-udi 13 h'00000034 to h'00000037 section 5 exception handling rev. 5.00 mar. 15, 2007 page 70 of 794 rej09b0237-0500 exception handling source vector numb er vector table address offset (reserved by system) 14 h'00000038 to h'0000003b : : 31 h'0000007c to h'0000007f trap instruction (user vect or) 32 h'00000080 to h'00000083 : : 63 h'000000fc to h'000000ff interrupt irq0 64 h'00000100 to h'00000103 irq1 65 h'00000104 to h'00000107 irq2 66 h'00000108 to h'0000010b irq3 67 h'0000010c to h'0000010f (reserved by system) 68 h'00000110 to h'00000113 : : 79 h'0000013c to h'0000013f irq4 80 h'00000140 to h'00000143 irq5 81 h'00000144 to h'00000147 irq6 82 h'00000148 to h'0000014b irq7 83 h'0000014c to h'0000014f on-chip peripheral module * 84 h'00000120 to h'00000124 : : 255 h'000003fc to h'000003ff note: * for details on the vector numbers and vector table address offsets of on-chip peripheral module interrupts, see table 6.2, interr upt exception handling sources, vector addresses and priorities in section 6, interrupt controller (intc). table 5.4 calculating exception handling vector table addresses exception source vector table address calculation resets vector table address = h'a0000000 + (vector table address offset) = h'a0000000 + (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3. section 5 exception handling rev. 5.00 mar. 15, 2007 page 71 of 794 rej09b0237-0500 5.2 resets 5.2.1 types of resets resets have priority over any exception source. as table 5.5 shows, a power-on reset initializes all modules in this lsi. table 5.5 reset status conditions for transition to reset state internal state type res wdt overflow h-udi command cpu, intc on-chip peripheral module pfc, i/o port low ? ? initialized initialized initialized power-on reset high overflow ? initialized initialized initialized h-udi reset high not overflowed reset assert command initialized initialized initialized 5.2.2 power-on reset power-on reset by res pin: when the res pin is driven low, this lsi enters the power-on reset state. to reliably reset this lsi, the res pin should be kept low for at least the oscillation settling time when applying the power or when in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. during the power-on reset state, cpu internal states and all registers of on-chip peripheral modules are initialized. in the power-on reset state, power-on rese t exception handling starts when driving the res pin high after driving the pin low for the given time. the cpu operates as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception handling vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception handling vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception handling vector table are set in pc and sp, then the program starts. be certain to always perform power-on reset ex ception handling when turning the system power on. section 5 exception handling rev. 5.00 mar. 15, 2007 page 72 of 794 rej09b0237-0500 power-on reset by wdt: when tcnt of the wdt overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the wdt, this lsi enters the power- on reset state. if a reset caused by the signal input on the res pin and a reset caused by a wdt overflow occur simultaneously, the res pin reset has priority, and the wovf bit in rstcsr is cleared to 0. when the power-on reset exception handling caused by the wdt is started, the cpu operates as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception handling vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception handling vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception handling vector table are set in the pc and sp, then the program starts. 5.2.3 h-udi reset the h-udi reset is generated by issuing the h- udi reset assert command . the cpu operation is described below. for details, see sectio n 21, user debuggin g interface (h-udi). 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception handling vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception handling vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) in the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception handli ng vector table are set in pc and sp, then the program starts. section 5 exception handling rev. 5.00 mar. 15, 2007 page 73 of 794 rej09b0237-0500 5.3 address errors 5.3.1 address error sources address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. table 5.6 bus cycles and address errors bus cycle type bus master bus cycl e description address errors cpu instruction fetched from even address none (normal) instruction fetch instruction fetched from odd address address error occurs cpu word data accessed from even address none (normal) data read/write word data accessed from odd address address error occurs longword data accessed from a longword boundary none (normal) longword data accessed from other than a long-word boundary address error occurs 5.3.2 address error exception source when an address error exception is generated, th e bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value to be saved is the start address of the instruction which cause d an address error exception. when the instruction that caused the exception is placed in the delay slot, the address of the delayed branch instruction which is placed immediately befo re the delay slot. 3. the start address of the exception handling routine is fetched from the exception handling vector table that corres ponds to the generated address error, and the program starts executing from that address. this branch is not a delayed branch. section 5 exception handling rev. 5.00 mar. 15, 2007 page 74 of 794 rej09b0237-0500 5.4 interrupts 5.4.1 interrupt sources table 5.7 shows the sources that start the interrupt exception handling. they are nmi, user break, h-udi, irq, and on-chip peripheral modules. table 5.7 interrupt sources type request source number of sources nmi nmi pin (external input) 1 user break user break controller (ubc) 1 h-udi user debug interface (h-udi) 1 irq irq0 to irq7 pins (external input) 8 on-chip peripheral module watchdog timer (wdt) 1 ether controller (etherc and e-dmac) 1 compare match timer (cmt0 and cmt1) 2 serial communication interface with fifo (scif0, scif1, and scif2) 12 host interface (hif) 2 direct memory access controller (dmac0, dmac1, dmac2, and dmac3) 4 serial i/o with fifo (siof) 1 all interrupt sources are given different vector numbers and vector table address offsets. for details on vector numbers and vector table addr ess offsets, see table 6.2, interrupt exception sources, vector addresses and priorities in section 6, interrupt controller (intc). section 5 exception handling rev. 5.00 mar. 15, 2007 page 75 of 794 rej09b0237-0500 5.4.2 interrupt priority the interrupt priority is predetermined. wh en multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (intc) determines their relative priorities and starts the exception handlin g according to the results. the priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has prio rity 16 and cannot be masked, so it is always accepted. the priority level of th e user break interrupt and h-udi is 15. irq interrupt and on-chip peripheral module interrupt priority levels can be set freely using the interrupt priority level setting registers a to g (ipra to iprg) of the intc as shown in table 5.8. the priority levels that can be set are 0 to 15. level 16 cannot be set. for details on ipra to iprg, see section 6.3.4, interrupt priority registers a to g (ipr a to iprg). table 5.8 interrupt priority type priority level comment nmi 16 fixed priority level. cannot be masked. user break 15 fixed priority level. can be masked. h-udi 15 fixed priority level. irq 0 to 15 on-chip peripheral module set with interrupt priority level setting registers a through g (ipra to iprg). 5.4.3 interrupt exception handling when an interrupt occurs, the interrupt controlle r (intc) ascertains its priority level. nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3 to i0) of the status register (sr). when an interrupt is accepted, exception handlin g begins. in interrupt exception handling, the cpu saves sr and the program counter (pc) to the stack. the priority level of the accepted interrupt is written to bits i3 to i0 in sr. although the priority level of the nmi is 16, the value set in bits i3 to i0 is h'f (level 15). next, the start address of the exception handling routine is fetched from the exception handling vector table for the accepted interrupt, and program execution branches to that address and the program starts. fo r details on the interrupt exception handling, see section 6.6, interrupt operation. section 5 exception handling rev. 5.00 mar. 15, 2007 page 76 of 794 rej09b0237-0500 5.5 exceptions triggered by instructions 5.5.1 types of exceptions triggered by instructions exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. table 5.9 types of exceptions triggered by instructions type source instruction comment trap instruction trapa ? illegal slot instructions * undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that changes the pc value delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that changes the pc value: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf, ldc rm,sr, ldc.l @rm+,sr general illegal instructions * undefined code anywhere besides in a delay slot ? note: * the operation is not guaranteed when undef ined instructions other than h'fc00 to h'ffff are decoded. 5.5.2 trap instructions when a trapa instruction is executed, the trap instruction exception handling starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the cpu reads the start address of the exception handling routine from the exception handling vector table that corresponds to the vector number specified in th e trapa instruction, program execution branches to th at address, and then the progra m starts. this branch is not a delayed branch. section 5 exception handling rev. 5.00 mar. 15, 2007 page 77 of 794 rej09b0237-0500 5.5.3 illegal slot instructions an instruction placed imme diately after a delayed branch inst ruction is called ?instruction placed in a delay slot?. when the instruction placed in th e delay slot is an unde fined code, illegal slot exception handling starts after the undefined code is decoded. illegal slot exception handling also starts when an instruction that changes the prog ram counter (pc) value is placed in a delay slot and the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the start address of the exception handling routine is fetched from the exception handling vector table that corres ponds to the exception that occurr ed. program execution branches to that address and the program starts. this branch is not a delayed branch. 5.5.4 general illegal instructions when an undefined code placed anywhere othe r than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception handling starts. the cpu handles the general illegal instructions in the same procedures as in the illegal slot instructions. unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start addr ess of the undefined code. section 5 exception handling rev. 5.00 mar. 15, 2007 page 78 of 794 rej09b0237-0500 5.6 cases when exceptions are accepted when an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an in terrupt disabled instruc tion, it may not be accepted and be held shown in table 5.10. in this case, when an instruction which accepts an in terrupt request is decoded, the exception is accepted. table 5.10 delay slot instructions, interr upt disabled instructions, and exceptions exception occurrence timing address error general illegal instruction slot illegal instruction trap instruction interrupt instruction in delay slot * 2 ? * 2 ? * 3 immediately after interrupt disabled instruction * 1 * 4 [legend] : accepted : not accepted ? : does not occur notes: 1. interrupt disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, and sts.l 2. an exception is accepted before the execution of a delayed branch instruction. however, when an address error or a slot illegal instruction exception occurs in the delay slot of the rte instruction, correct operation is not guaranteed. 3. an exception is accepted after a delayed br anch (between instructions in the delay slot and the branch destination). 4. an exception is accepted after the exec ution of the next instru ction of an interrupt disabled instruction (before the execution two instructions after an interrupt disabled instruction). section 5 exception handling rev. 5.00 mar. 15, 2007 page 79 of 794 rej09b0237-0500 5.7 stack states after exception handling ends the stack states after exception hand ling ends are shown in table 5.11. table 5.11 stack status a fter exception handling ends types stack state address error (when the instruction that caused an exception is placed in the delay slot) sp address of delayed branch instruction sr 32 bits 32 bits address error (other than above) sp sr 32 bits 32 bits address of instruction that caused exception interrupt sp sr 32 bits 32 bits address of instruction after executed instruction trap instruction sp sr 32 bits 32 bits address of instruction after trapa instruction section 5 exception handling rev. 5.00 mar. 15, 2007 page 80 of 794 rej09b0237-0500 types stack state illegal slot instruction sp address of delayed branch instruction sr 32 bits 32 bits general illegal instruction sp sr 32 bits 32 bits address of general illegal instruction section 5 exception handling rev. 5.00 mar. 15, 2007 page 81 of 794 rej09b0237-0500 5.8 usage notes 5.8.1 value of stack pointer (sp) the sp value must always be a mul tiple of 4. if it is not, an address error will occur when the stack is accessed during exception handling. 5.8.2 value of vector base register (vbr) the vbr value must always be a multiple of 4. if it is not, an address error will occur when the stack is accessed during exception handling. 5.8.3 address errors caused by stacking for address error exception handling when the sp value is not a multiple of 4, an address error will occur when stacking for exception handling (interrupts, etc.) and address error exception handling will start after the first exception handling is ended. address errors will also occur in the stacking for this address error exception handling. to ensure that address error exception handling does not go into an endless loop, no address errors are accepted at that point. this allows program cont rol to be passed to the handling routine for address error exceptio n and enables error processing. when an address error occurs during exception handling stacking, the stacking bus cycle (write) is executed. when stacking the sr and pc values , the sp values for both are subtracted by 4, therefore, the sp value is still not a multiple of 4 after the stacking. the address value output during stacking is the sp value whose lower two bits are cleared to 0. so th e write data stacked is undefined. 5.8.4 notes on slot illegal instruction exception handling some specifications on slot illegal instruction exception handling in this lsi differ from those of the conventional sh2. ? conventional sh2: instructions ldc rm,sr and ldc.l @rm + ,sr are not subject to the slot illegal instructions. ? this lsi: instructions ldc rm,sr and ldc.l @rm + ,sr are subject to the slot illegal instructions. the supporting status on our software products regarding this note is as follows: section 5 exception handling rev. 5.00 mar. 15, 2007 page 82 of 794 rej09b0237-0500 compiler this instruction is not allocated in the delay slot in the compiler v.4 and its subsequent versions. real-time os for itron specifications 1. hi7000/4, hi-sh7 this instruction does not exist in the delay slot within the os. 2. hi7000 this instruction is in part allocated to the delay slot within the os, which may cause the slot illegal instruction exception handling in this lsi. 3. others the slot illegal instruction exception handling may be generated in this lsi in a case where the instruction is described in assembler or when the middleware of the object is introduced. note that a check-up program (checker) to pick up this instruction is available on our website. download and utilize this checker as needed. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 83 of 794 rej09b0237-0500 section 6 interrupt controller (intc) the interrupt controller (intc) ascertains the prior ity of interrupt sources and controls interrupt requests to the cpu. 6.1 features ? 16 levels of interrupt priority figure 6.1 shows a block diagram of the intc. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 84 of 794 rej09b0237-0500 nmi irq0 irq7 ubc h-udi wdt e-dmac cmt0 cmt1 scif0 scif1 scif2 hif dmac siof (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) input control com- parator interrupt request sr cpu i3 i2 i1 i0 internal bus bus interface ipra to ipre icr0 irqsr irqcr module bus intc hif: host interface dmac: direct memory access controller icr0: interrupt control register 0 irqcr: irq control register irqsr: irq status register ipra to iprg: interrupt priority registers a to g sr: status register ipr dter dtc [legend] ubc: user break controller h-udi: user debugging interface wdt: watchdog timer e-dmac: dmac for ethernet controller cmt: compare match timer scif: serial communications interface with fifo priority determination . . . . . . figure 6.1 intc block diagram section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 85 of 794 rej09b0237-0500 6.2 input/output pins table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbr. i/o function non-maskable interrupt input pin nmi input input of non-maskable interrupt request signal interrupt request input pins irq0 to irq7 input input of maskable interrupt request signals 6.3 register descriptions the interrupt controller has the following registers. for details on the addresses of these registers and the states of these registers in each processi ng state, see section 24, list of registers. ? interrupt control register 0 (icr0) ? irq control register (irqcr) ? irq status register (irqsr) ? interrupt priority register a (ipra) ? interrupt priority register b (iprb) ? interrupt priority register c (iprc) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 86 of 794 rej09b0237-0500 6.3.1 interrupt contro l register 0 (icr0) icr0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin nmi and indicates the input signal level on the nmi pin. bit bit name initial value r/w description 15 nmil 1/0 r nmi input level indicates the state of the si gnal input to the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. 0: state of the nmi input is low 1: state of the nmi input is high 14 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select 0: interrupt request is det ected on the falling edge of the nmi input 1: interrupt request is detec ted on the rising edge of the nmi input 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 87 of 794 rej09b0237-0500 6.3.2 irq control register (irqcr) irqcr is a 16-bit register that sets the input signal detection mode of the external interrupt input pins irq0 to irq7. bit bit name initial value r/w description 15 14 irq71s irq70s 0 0 r/w r/w irq7 sense select set the interrupt request detection mode for pin irq7. 00: interrupt request is det ected at the low level of pin irq7 01: interrupt request is detected at the falling edge of pin irq7 10: interrupt request is detected at the rising edge of pin irq7 11: interrupt request is det ected at both the falling and rising edges of pin irq7 13 12 irq61s irq60s 0 0 r/w r/w irq6 sense select set the interrupt request detection mode for pin irq6. 00: interrupt request is det ected at the low level of pin irq6 01: interrupt request is detected at the falling edge of pin irq6 10: interrupt request is detected at the rising edge of pin irq6 11: interrupt request is det ected at both the falling and rising edges of pin irq6 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 88 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 irq51s irq50s 0 0 r/w r/w irq5 sense select set the interrupt request detection mode for pin irq5. 00: interrupt request is det ected at the low level of pin irq5 01: interrupt request is detected at the falling edge of pin irq5 10: interrupt request is detected at the rising edge of pin irq5 11: interrupt request is det ected at both the falling and rising edges of pin irq5 9 8 irq41s irq40s 0 0 r/w r/w irq4 sense select set the interrupt request detection mode for pin irq4. 00: interrupt request is det ected at the low level of pin irq4 01: interrupt request is detected at the falling edge of pin irq4 10: interrupt request is detected at the rising edge of pin irq4 11: interrupt request is det ected at both the falling and rising edges of pin irq4 7 6 irq31s irq30s 0 0 r/w r/w irq3 sense select set the interrupt request detection mode for pin irq3. 00: interrupt request is det ected at the low level of pin irq3 01: interrupt request is detected at the falling edge of pin irq3 10: interrupt request is detected at the rising edge of pin irq3 11: interrupt request is det ected at both the falling and rising edges of pin irq3 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 89 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 4 irq21s irq20s 0 0 r/w r/w irq2 sense select set the interrupt request detection mode for pin irq2. 00: interrupt request is det ected at the low level of pin irq2 01: interrupt request is detected at the falling edge of pin irq2 10: interrupt request is detected at the rising edge of pin irq2 11: interrupt request is det ected at both the falling and rising edges of pin irq2 3 2 irq11s irq10s 0 0 r/w r/w irq1 sense select set the interrupt request detection mode for pin irq1. 00: interrupt request is det ected at the low level of pin irq1 01: interrupt request is detected at the falling edge of pin irq1 10: interrupt request is detected at the rising edge of pin irq1 11: interrupt request is det ected at both the falling and rising edges of pin irq1 1 0 irq01s irq00s 0 0 r/w r/w irq0 sense select set the interrupt request detection mode for pin irq0. 00: interrupt request is det ected at the low level of pin irq0 01: interrupt request is detected at the falling edge of pin irq0 10: interrupt request is detected at the rising edge of pin irq0 11: interrupt request is det ected at both the falling and rising edges of pin irq0 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 90 of 794 rej09b0237-0500 6.3.3 irq status register (irqsr) irqsr is a 16-bit register that indicates the states of the external interrupt input pins irq0 to irq7 and the status of interrupt request. bit bit name initial value r/w description 15 irq7l 0/1 r indicates the state of pin irq7. 0: state of pin irq7 is low 1: state of pin irq7 is high 14 irq6l 0/1 r indicates the state of pin irq6. 0: state of pin irq6 is low 1: state of pin irq6 is high 13 irq5l 0/1 r indicates the state of pin irq5. 0: state of pin irq5 is low 1: state of pin irq5 is high 12 irq4l 0 or 1 r indicates the state of pin irq4. 0: state of pin irq4 is low 1: state of pin irq4 is high 11 irq3l 0 or 1 r indicates the state of pin irq3. 0: state of pin irq3 is low 1: state of pin irq3 is high 10 irq2l 0 or 1 r indicates the state of pin irq2. 0: state of pin irq2 is low 1: state of pin irq2 is high 9 irq1l 0 or 1 r indicates the state of pin irq1. 0: state of pin irq1 is low 1: state of pin irq1 is high 8 irq0l 0 or 1 r indicates the state of pin irq0. 0: state of pin irq0 is low 1: state of pin irq0 is high section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 91 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 irq7f 0 r/w indicates the status of an irq7 interrupt request. ? when level detection mode is selected 0: an irq7 interrupt has not been detected [clearing condition] driving pin irq7 high 1: an irq7 interrupt has been detected [setting condition] driving pin irq7 low ? when edge detection mode is selected 0: an irq7 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq7f = 1 ? accepting an irq7 interrupt 1: an irq7 interrupt request has been detected [setting condition] detecting the specified edge of pin irq7 6 irq6f 0 r/w indicates the status of an irq6 interrupt request. ? when level detection mode is selected 0: an irq6 interrupt has not been detected [clearing condition] driving pin irq6 high 1: an irq6 interrupt has been detected [setting condition] driving pin irq6 low ? when edge detection mode is selected 0: an irq6 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq6f = 1 ? accepting an irq6 interrupt 1: an irq6 interrupt request has been detected [setting condition] detecting the specified edge of pin irq6 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 92 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 irq5f 0 r/w indicates the status of an irq5 interrupt request. ? when level detection mode is selected 0: an irq5 interrupt has not been detected [clearing condition] driving pin irq5 high 1: an irq5 interrupt has been detected [setting condition] driving pin irq5 low ? when edge detection mode is selected 0: an irq5 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq5f = 1 ? accepting an irq5 interrupt 1: an irq5 interrupt request has been detected [setting condition] detecting the specified edge of pin irq5 4 irq4f 0 r/w indicates the status of an irq4 interrupt request. ? when level detection mode is selected 0: an irq4 interrupt has not been detected [clearing condition] driving pin irq4 high 1: an irq4 interrupt has been detected [setting condition] driving pin irq4 low ? when edge detection mode is selected 0: an irq4 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq4f = 1 ? accepting an irq4 interrupt 1: an irq4 interrupt request has been detected [setting condition] detecting the specified edge of pin irq4 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 93 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 irq3f 0 r/w indicates the status of an irq3 interrupt request. ? when level detection mode is selected 0: an irq3 interrupt has not been detected [clearing condition] driving pin irq3 high 1: an irq3 interrupt has been detected [setting condition] driving pin irq3 low ? when edge detection mode is selected 0: an irq3 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq3f = 1 ? accepting an irq3 interrupt 1: an irq3 interrupt request has been detected [setting condition] detecting the specified edge of pin irq3 2 irq2f 0 r/w indicates the status of an irq2 interrupt request. ? when level detection mode is selected 0: an irq2 interrupt has not been detected [clearing condition] driving pin irq2 high 1: an irq2 interrupt has been detected [setting condition] driving pin irq2 low ? when edge detection mode is selected 0: an irq2 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq2f = 1 ? accepting an irq2 interrupt 1: an irq2 interrupt request has been detected [setting condition] detecting the specified edge of pin irq2 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 94 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 irq1f 0 r/w indicates the status of an irq1 interrupt request. ? when level detection mode is selected 0: an irq1 interrupt has not been detected [clearing condition] driving pin irq1 high 1: an irq1 interrupt has been detected [setting condition] driving pin irq1 low ? when edge detection mode is selected 0: an irq1 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq1f = 1 ? accepting an irq1 interrupt 1: an irq1 interrupt request has been detected [setting condition] detecting the specified edge of pin irq1 0 irq0f 0 r/w indicates the status of an irq0 interrupt request. ? when level detection mode is selected 0: an irq0 interrupt has not been detected [clearing condition] driving pin irq0 high 1: an irq0 interrupt has been detected [setting condition] driving pin irq0 low ? when edge detection mode is selected 0: an irq0 interrupt has not been detected [clearing conditions] ? writing 0 after reading irq0f = 1 ? accepting an irq0 interrupt 1: an irq0 interrupt request has been detected [setting condition] detecting the specified edge of pin irq0 section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 95 of 794 rej09b0237-0500 6.3.4 interrupt prio rity registers a to g (ipra to iprg) interrupt priority registers are seven 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except nmi. for the correspondence between interrupt request sources and ipr, refer to table 6.2 interrupt request sources, vector address, and interrupt priority level. each of the corresponding interrupt priority ranks are established by setting a value from h'0 to h'f in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. reserved bits that are not assigned should be set h'0 (b'0000). bit bit name initial value r/w description 15 14 13 12 ipr15 ipr14 ipr13 ipr12 0 0 0 0 r/w r/w r/w r/w set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 96 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 9 8 ipr11 ipr10 ipr9 ipr8 0 0 0 0 r/w r/w r/w r/w set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) 7 6 5 4 ipr7 ipr6 ipr5 ipr4 0 0 0 0 r/w r/w r/w r/w set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 97 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 2 1 0 ipr3 ipr2 ipr1 ipr0 0 0 0 0 r/w r/w r/w r/w set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) note: name in the tables above is represented by a general name. name in the list of register is, on the other hand, represent ed by a module name. 6.4 interrupt sources 6.4.1 external interrupts there are five types of interrupt sources: user break, nmi, h-udi, irq, and on-chip peripheral modules. individual interrupts are given priority levels (0 to 16, with 0 the lowest and 15 the highest). giving an interrupt a priority level of 0 masks it. nmi interrupt: the nmi interrupt is given a priority leve l of 16 and is always accepted. an nmi interrupt is detected at the edge of the pins. use the nmi edge select bit (nmie) in interrupt control register 0 (icr0) to select either the ri sing or falling edge. in the nmi interrupt exception handler, the interrupt mask level bits (i3 to i0) in the status register (sr) are set to level 15. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 98 of 794 rej09b0237-0500 irq7 to irq0 interrupts: irq interrupts are requested by input from pins irq0 to irq7. use the irq sense select bits (irq71s to irq 01s and irq70s to irq00s) in the irq control register (irqcr) to select the detection mode from low level detection, falling edge detection, rising edge detection, and both edge detection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority registers a and b (ipra and iprb). in the case that the low level detection is selected, an interrupt request signal is sent to the intc while the irq pin is driven low. the interrupt request signal stops to be sent to the intc when the irq pin becomes high. it is possible to confirm that an interrupt is requested by reading the irq flags (irq7f to irq0f) in the irq status register (irqsr). in the case that the edge detection is selected, an interrupt request signal is sent to the intc when the following change on the irq pin is detected: from high to low in falling edge detection mode, from low to high in rising edge detection mode, and from low to high or from high to low in both edge detection mode. the irq interrupt request by detecting the change on the pin is held until the interrupt request is accepted. it is possible to confirm that an irq interrupt request has been detected by reading the irq flags (irq7f to irq0f) in the irq status register (irqsr). an irq interrupt request by detecting the change on the pin can be withdrawn by writing 0 to an irq flag after reading 1. in the irq interrupt exception handling, the interrup t mask bits (i3 to i0) in the status register (sr) are set to the prio rity level value of the accepted irq in terrupt. figure 6.2 shows the block diagram of the irq7 to irq0 interrupts. irqcr.irqn1s irqcr.irqn0s irqsr.irqnf irqsr.irqnl irqn pins resirqn level detection edge detection sq r selection cpu interrupt request (acceptance of irqn interrupt/ writing 0 after reading irqnf = 1) n = 7 to 0 figure 6.2 block diagram of irq7 to irq0 interrupts control section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 99 of 794 rej09b0237-0500 6.4.2 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. since a different interrupt vector is allocated to each interrup t source, the exception handling routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be allocated to individual on-chip peripheral modules in interrupt priority registers c to g (iprc to iprg). on-chip peripheral module interrupt exception handling sets the interrupt mask level bits (i3 to i0) in the status register (sr) to the priority level value of th e on-chip peripheral module interrupt that was accepted. 6.4.3 user break interrupt a user break interrupt has a priority level of 15, and occurs when the break condition set in the user break controller (ubc) is satisfied. user break interrupt requests are detected by edge and are held until accepted. user br eak interrupt exception handling sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. for more details on the user break interrupt, see section 20, user break controller (ubc). 6.4.4 h-udi interrupt user debugging interface (h -udi) interrupt has a priority level of 15, and occurs when an h-udi interrupt instruction is serially input. h-udi interrupt requests are detected by edge and are held until accepted. h-udi exceptio n handling sets the interrupt mask level bits (i3-i0) in the status register (sr) to level 15. for more details on the h-udi interrupt, see section 21, user debugging interface (h-udi). section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 100 of 794 rej09b0237-0500 6.5 interrupt exception handling vector table table 6.2 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. individual interrupt sources are allocated to different vector numbers and vector table address offsets. vector table addresses are calculated fr om the vector numbers and vector table address offsets. for interrupt exception handling, the start address of the exception handling routine is fetched from the vector table addres s in the vector table. for the de tails on calculation of vector table addresses, see table 5.4, calculating exception handling vector table addresses in section 5, exception handling. irq interrupts and on-chip peripheral module in terrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers a to g (ipra to iprg). however, when interrupt sources whose priority levels are allocated with the same ipr are requested, the interrupt of the smaller vector number has priority. this priority cannot be changed. priority levels of irq interrupts and on-chip peripheral module interrupts are initialized to level 0 at a power-on reset. if the same priority level is allocated to two or mo re interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order shown in table 6.2. table 6.2 interrupt exception ha ndling vectors and priorities interrupt source name vector no. vector table starting address ipr default priority user break 12 h'00000030 ? high external pin nmi 11 h'0000002c ? h-udi 13 h'00000034 ? external pin irq0 64 h'00000100 ipra15 to ipra12 irq1 65 h'00000104 ipra11 to ipra8 irq2 66 h'00000108 ipra7 to ipra4 irq3 67 h'0000010c ipra3 to ipra0 irq4 80 h'00000140 iprb15 to iprb12 irq5 81 h'00000144 iprb11 to iprb8 irq6 82 h'00000148 iprb7 to iprb4 irq7 83 h'0000014c iprb3 to iprb0 low section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 101 of 794 rej09b0237-0500 interrupt source name vector no. vector table starting address ipr default priority wdt iti 84 h'00000150 iprc15 to iprc12 hight e-dmac eint0 85 h'00000154 iprc11 to iprc8 cmt channel 0 cmi0 86 h'00000158 iprc7 to iprc4 cmt channel 1 cmi1 87 h'0000015c iprc3 to iprc0 eri_0 88 h'00000160 iprd15 to iprd12 rxi_0 89 h'00000164 bri_0 90 h'00000168 scif channel 0 txi_0 91 h'0000016c eri_1 92 h'00000170 iprd11 to iprd8 rxi_1 93 h'00000174 bri_1 94 h'00000178 scif channel 1 txi_1 95 h'0000017c eri_2 96 h'00000180 iprd7 to iprd4 rxi_2 97 h'00000184 bri_2 98 h'00000188 scif channel 2 txi_2 99 h'0000018c hif hifi 100 h'00000190 ipre15 to ipre12 hifbi 101 h'00000194 ipre11 to ipre8 dmac dei0 104 h'000001a0 iprf15 to iprf12 dei1 105 h'000001a4 iprf11 to iprf8 dei2 106 h'000001a8 iprf7 to iprf4 dei3 107 h'000001ac iprf3 to iprf0 siof siofi 108 h'000001b0 iprg15 to iprg12 low section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 102 of 794 rej09b0237-0500 6.6 interrupt operation 6.6.1 interrupt sequence the sequence of interrupt operations is explained below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest pr iority interrupt from interrupt requests sent, according to the priority levels se t in interrupt priority level se tting registers a to g (ipra to iprg). interrupts that have lower-priority than that of the selected interrupt are ignored*. if interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest pr iority is selected acco rding to the priority shown in table 6.2. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3 to i0) in the status regist er (sr) of the cpu. if the priority level of the selected request is equal to or less than the level set in bits i3 to i0, the request is ignored. if the priority level of the selected request is higher than the level in bits i3 to i0, the interrupt controller accepts the request and sends an interrupt request signal to the cpu. 4. the cpu detects the interrupt request sent from the interrupt controller in the decode stage of an instruction to be executed. instead of exec uting the decoded instruction, the cpu starts interrupt exception handling (see figure 6.5). 5. sr and pc are saved onto the stack. 6. the priority level of the accepted interr upt is copied to bits (i3 to i0) in sr. 7. the cpu reads the start address of the excepti on handling routine from the exception vector table for the accepted interrupt, branches to that address, and starts executing the program. this branch is not a delayed branch. note: * interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. irq interrupt s, however, can be cancelled by accessing the irq status register (irqsr). interrupts held pending due to edge detection are cleared by a power-on rese t or an h-udi reset. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 103 of 794 rej09b0237-0500 program execution state interrupt? user break? i3 to i0 level 14? level 14 interrupt? level 1 interrupt? i3 to i0 level 13? i3 to i0 = level 0? no yes no no no no no no no no yes yes yes yes yes yes yes yes save sr to stack save pc to stack copy interrupt level to i3 to i0 read exception vector table branch to exception handling routine h-udi interrupt? no yes level 15 interrupt? note: i3 to i0 are interrupt mask bits in the status register (sr) of the cpu nmi? i3 to i0 level 14? no yes figure 6.3 interrupt sequence flowchart section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 104 of 794 rej09b0237-0500 6.6.2 stack after interru pt exception handling figure 6.4 shows the stack after interrupt exception handling. 32 bits 32 bits pc * 1 sr address 4n ? 8 4n ? 4 4n sp * 2 notes: 1. pc is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. always make sure that sp is a multiple of 4 figure 6.4 stack after interrupt exception handling 6.7 interrupt response time table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. figure 6.5 shows an example of the pipeline operation when an irq interrupt is accepted. section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 105 of 794 rej09b0237-0500 table 6.3 interrupt response time number of cycles item nmi, h-udi irq, peripheral modules remarks interrupt priority decision and comparison with mask bits in sr 1 icyc + 2 pcyc 1 icyc + 3 pcyc wait for completion of sequence currently being executed by cpu x ( 0) x ( 0) the longest sequence is for interrupt or address- error exception handling (x = 7 icyc + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception handling until fetch of first instruction of exception handling routine starts 8 icyc + m1 + m2 + m3 8 icyc + m1 + m2 + m3 performs the saving pc and sr, and vector address fetch. interrupt response time total: 9 icyc + 2 pcyc + m1 + m2 + m3 + x 9 icyc + 3 pcyc + m1 + m2 + m3 + x minimum * : 12 icyc + 2 pcyc 12 icyc + 3 pcyc sr, pc, and vector table are all in on-chip ram, or cache hit occurs (in write back mode). maximum: 16 icyc + 2 pcyc + 2 (m1 + m2 + m3) + m4 16 icyc + 3 pcyc + 2 (m1 + m2 + m3) + m4 notes: * in the case that m1 = m2 = m3 = m4 = 1 icyc. m1 to m4 are the number of cycles needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine section 6 interrupt controller (intc) rev. 5.00 mar. 15, 2007 page 106 of 794 rej09b0237-0500 section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 107 of 794 rej09b0237-0500 section 7 bus state controller (bsc) the bus state controller (bsc) outputs control si gnals for various types of memory that is connected to the external addre ss space and external devices. the bsc functions enable this lsi to connect directly with sram, sdram, and other memory storage devices, and external devices. 7.1 features the bsc has the following features. ? external address space ? a maximum 32 or 64 mbytes for each of the areas, cs0, cs3, cs4, cs5b, and cs6b, totally 256 mbytes (divided into five areas) ? a maximum 64 mbytes for each of the six areas, cs0, cs3, cs4, cs5, and cs6, totally 320 mbytes (divided into five areas) ? can specify the normal space interface, byte- selection sram, sdram, pcmcia for each address space ? can select the data bus width (8, 16, or 32 bits) for each address space. (the cs0 data bus width can only be selected from 8 or 16 bits.) ? can control the insertion of wa it cycles for each address space ? can control the insertion of wait cycl es for each read access and write access ? can control the insertion of idle cycles in the consecutive access for five cases independently: read-write (in same sp ace/different space), read-read (in same space/different space), or the first cycle is a write access ? normal space interface ? supports the interface that can directly connect to the sram ? sdram interface ? can connect directly to sdram in area 3 ? multiplex output for row address/column address ? efficient access by single read/single write ? high-speed access by bank-active mode ? supports auto-refreshing and self-refreshing section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 108 of 794 rej09b0237-0500 ? byte-selection sram interface ? can connect directly to byte-selection sram ? pcmcia direct interface ? supports ic memory cards and i/o card inte rfaces defined in the jeida specifications ver 4.2 (pcmcia2.1 rev 2.1) ? controls the insertion of wait cycles by software ? supports the bus sizing function of the i/o bus width (only in little endian mode) ? refresh function ? supports the auto-refreshing and self-refreshing functions ? specifies the refresh interval by setting the refresh counter and clock selection ? can execute consecutive refresh cycles by specify ing the refresh counts (1, 2, 4, 6, or 8) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 109 of 794 rej09b0237-0500 the block diagram of the bsc is shown in figure 7.1. cmncr cs0wcr cs6bwcr cs0bcr cs6bbcr sdcr rtcsr rtcnt rtcor comparator bus mastership controller wait controller area controller internal master module internal slave module internal b us memory controller refresh controller module bus bsc cs0 , cs3 , cs4 , cs5b ( ce1a ), cs6b ( ce1b ) wait md5 iois16 a25 to a0, d31 to d0, bs , rd/ wr , rd , we3 ( be3 , dqmuu), we2 ( be2 , dqmuu), we1 ( be1 , dqmuu, we ), we0 ( be0 , dqmll), iciowr , iciord , ras , cas , cke, ce2a , ce2b [legend] cmncr: common control register csnwcr: csn space wait control register (n = 0, 3, 4, 5b, 6b) rwtcnt: reset wait counter csnbcr: csn space bus control register (n = 0, 3, 4, 5b, 6b) sdcr: sdram control register rtcsr: refresh timer control/status register rtcnt: refresh timer counter rtcor: refresh time constant register . . . . . . . . . . . . . . . rwtcnt figure 7.1 block diagram of bsc section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 110 of 794 rej09b0237-0500 7.2 input/output pins table 7.1 lists the pin configuration of the bsc. table 7.1 pin configuration abbreviation i/o function a25 to a0 output address bus * d31 to d0 i/o data bus bs output bus cycle start asserted when a normal space, burst rom (clock synchronous /asynchronous), or pcmcia is acce ssed. asserted at the same timing as cas assertion in sdram access. cs0 , cs3 , cs4 output chip select cs5b / ce1a output chip select chip enable for pcmcia allocated to area 5 when pcmcia is in use ce2a output chip enable for pcmcia alloca ted to area 5 when pcmcia is in use cs6b / ce1b output chip select chip enable for pcmcia allocated to area 6 when pcmcia is in use ce2b output chip enable for pcmcia alloca ted to area 6 when pcmcia is in use rd/ wr output read/write connects to we pins when sdram or byte-selection sram is used. rd output read pulse signal (read data output enable signal) strobe signal to indicate a memory read cycle when pcmcia is in use. iciowr output strobe signal to indicate i/o write when pcmcia is in use. iciord output strobe signal to indicate i/o read when pcmcia is in use. we3(be3) output indicates that d31 to d24 are being written to. connected to the byte select signal when byte-selection sram is in use. we2(be2) output indicates that d23 to d16 are being written to. connected to the byte select signal when byte-selection sram is in use. we1(be1) / we output indicates that d15 to d8 are being written to. connected to the byte select signal when byte-selection sram is in use. strove signal to indicate a memory write cycle when pcmcia is in use. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 111 of 794 rej09b0237-0500 abbreviation i/o function we0(be0) output indicates that d7 to d0 are being written to. connected to the byte select signal when a byte-selection sram is in use. ras output connected to ras pin when sdram is in use. cas output connected to cas pin when sdram is in use. cke output connected to cke pin when sdram is in use. iois16 input pcmcia 16-bit i/o signal enabled only in little endian mode. drive this signal low in big endian mode. dqmuu, dqmul, dqmlu, dqmll output connected to the dqm xx pin when sdram is in use. dqmuu: select signal for d31 to d24 dqmul: select signal for d23 to d16 dqmlu: select signal for d15 to d8 dqmll: select signal for d7 to d0 wait input external wait input md5, md3 input md5: selects data alignment (big endian or little endian) md3: specifies area 0 bus width (8/16 bits) note: * as pins a25 to a16 act as general i/o por ts immediately after a power-on reset, pull-up or pull-down these pins outside the lsi as needed. 7.3 area overview 7.3.1 area division the architecture of this lsi has 32-bit address space. the upper thr ee address bits divide the space into areas p0 to p4, and the c ache access methods can be specified for each area. for details, see section 3, cache. each area indicat ed by the remaining 29 bits is divided into ten areas (five areas are reserved) when address map 1 is selected or eight areas (three areas are reserved) when address map 2 is selected. the address ma p is selected by the map bit in cmncr. the bsc controls the areas indicated by the 29 bits. as listed in tables 7.2 and 7.3, memory can be connected directly to five physical areas of this lsi, and the chip select signals ( cs0 , cs3 , cs4 , cs5b , and cs6b ) are output for each area. cs0 is asserted during area 0 access. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 112 of 794 rej09b0237-0500 7.3.2 shadow area areas 0, 3, 4, 5b, and 6b are divided by decoding physical address bits a28 to a25, which correspond to areas 000 to 111. address bits 31 to 29 are ignore d. this means that the range of area 0 addresses, for example, is h'00000000 to h'03f fffff, and its corresp onding shadow space is the address space in p1 to p3 areas obtained by adding to it h'20000000 n (n = 1 to 6). the address range for area 7 is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n (n = 0 to 6) corresponding to the area 7 shadow spaces are reserv ed, so do not use it. area p4 (h'e0000000 to h'efffffff) is an i/o area and is allocated to internal register addresses. therefore, area p4 does not become shadow space. area 0 (cs0) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 area 1 (reserved) area 2 (reserved) area 3 (cs3) area 4 (cs4) area 5a (reserved) area 6a (reserved) area 7 (reserved) physical address space address space p0 p1 p2 p3 p4 area 5b (cs5b) area 6b (cs6b) figure 7.2 address space 7.3.3 address map the external address space has a ca pacity of 256 mbytes and is divided into five areas. types of memory to be connected and the data bus widt h are specified for indi vidual areas. the address map for the external address space is shown in table 7.2. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 113 of 794 rej09b0237-0500 table 7.2 address map 1 (cmncr.map = 0) physical address area memory to be connected capacity h'00000000 to h'03ffffff area 0 normal memory 64 mbytes h'04000000 to h'07ffffff area 1 reserved area * 64 mbytes h'08000000 to h'0bffffff area 2 reserved area * 64 mbytes h'0c000000 to h'0fffffff area 3 normal memory byte-selection sram sdram 64 mbytes h'10000000 to h'13ffffff area 4 normal memory byte-selection sram 64 mbytes h'14000000 to h'15ffffff area 5a reserved area * 32 mbytes h'16000000 to h'17ffffff area 5b normal memory byte-selection sram 32 mbytes h'18000000 to h'19ffffff area 6a reserved area * 32 mbytes h'1a000000 to h'1bffffff area 6b normal memory byte-selection sram 32 mbytes h'1c000000 to h'1fffffff area 7 reserved area * 64 mbytes note: * do not access the reserved area. if the reserved area is accessed, the correct operation cannot be guaranteed. table 7.3 address map 2 (cmncr.map = 1) physical address area memory to be connected capacity h'00000000 to h'03ffffff area 0 normal memory 64 mbytes h'04000000 to h'07ffffff area 1 reserved area * 1 64 mbytes h'08000000 to h'0bffffff area 2 reserved area * 1 64 mbytes h'0c000000 to h'0fffffff area 3 normal memory byte-selection sram sdram 64 mbytes h'10000000 to h'13ffffff area 4 normal memory byte-selection sram 64 mbytes h'14000000 to h'17ffffff area 5 * 2 normal memory byte-selection sram pcmcia 64 mbytes section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 114 of 794 rej09b0237-0500 physical address area memory to be connected capacity h'18000000 to h'1bffffff area 6 * 2 normal memory byte-selection sram pcmcia 64 mbytes h'1c000000 to h'1fffffff area 7 reserved area * 1 64 mbytes notes: 1. do not access the reserved area. if the reserved area is accessed, the correct operation cannot be guaranteed. 2. for area 5, cs5bbcr and cs5bwcr are enabled. for area 6, cs6bbcr and cs6bwcr are enabled. 7.3.4 area 0 memory type and memory bus width the memory bus width in this lsi can be set for each area. in area 0, the bus width is selected from 8 bits and 16 bits at a power-on reset by the external pin setting. the bus width of other areas is set by the register. the corr espondence between the memory type , external pin (md3), and bus width is listed in table 7.4. table 7.4 correspondence betw een external pin (md3), memory type, and bus width for cs0 md3 memory type bus width 1 normal memory 8 bits 0 16 bits 7.3.5 data alignment this lsi supports the big endian and little endian methods of data alignment. the data alignment is specified using the external pin (md5) at a power-on reset as shown in table 7.5. table 7.5 correspondence between external pin (md5) and endians md5 endian 0 big endian 1 little endian section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 115 of 794 rej09b0237-0500 7.4 register descriptions the bsc has the following regist ers. for the addresses and access size for these registers, see section 24, list of registers. do not access spaces other than cs0 until se tting the memory interfaces is complete. ? common control register (cmncr) ? cs0 space bus control register for area 0 (cs0bcr) ? cs3 space bus control register for area 3 (cs3bcr) ? cs4 space bus control register for area 4 (cs4bcr) ? cs5b space bus control register for area 5b (cs5bbcr) ? cs6b space bus control register for area 6b (cs6bbcr) ? cs0 space wait control register for area 0 (cs0wcr) ? cs3 space wait control register for area 3 (cs3wcr) ? cs4 space wait control register for area 4 (cs4wcr) ? cs5b space wait control regist er for area 5b (cs5bwcr) ? cs6b space wait control regist er for area 6b (cs6bwcr) ? sdram control register (sdcr) ? refresh timer control/status register (rtcsr) ? refresh timer counter (rtcnt) ? refresh time constant register (rtcor) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 116 of 794 rej09b0237-0500 7.4.1 common control register (cmncr) cmncr is a 32-bit register that controls the co mmon items for each area . do not access external memory other than area 0 until setting cmncr is complete. bit bit name initial value r/w description 31 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 map 0 r/w space specification selects the address map for the external address space. the address maps to be selected are shown in tables 7.2 and 7.3. 0: selects address map 1 1: selects address map 2 11 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 3 endian 0/1 * r endian flag fetches the external pin (md5) state for specifying endian at a power-on reset. the endian setting for all the address spaces are set by this bit. this is a read-only bit. 0: external pin (md5) for specifying endian was driven low at a power-on reset. this lsi is operated as big endian. 1: external pin (md5) for specifying endian was driven high at a power-on reset. this lsi is being operated as little endian. 2 ? 1 r reserved this bit is always read as 1. the write value should always be 1. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 117 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 hizmem 0 r/w hi-z memory control specifies the pin state in st andby mode for pins a25 to a0, bs , csn , rd/ wr , wen ( ben )/dqmxx, and rd . 0: high impedance in standby mode 1: driven in standby mode 0 hizcnt 0 r/w hi-z control specifies the pin state in standby mode for the ckio, cke, ras , and cas pins. 0: high impedance in standby mode 1: driven in standby mode note: * the external pin (md5) state for specifyi ng endian is sampled at a power-on reset. when big endian is specified, this bit is r ead as 0 and when little endian is specified, this bit is read as 1. 7.4.2 csn space bus control register (csnbcr) (n = 0, 2, 3, 4, 5b, 6b) csnbcr specifies the type of me mory connected to each space, da ta-bus width of each space, and the number of wait cycles between access cycles. do not access external memory other than area 0 until setting csnbcr is completed. bit bit name initial value r/w description 31, 30 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 29 28 iww1 iww0 1 1 r/w r/w idle cycles between write-read cycles and write-write cycles specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. the write and read cycles or write and write cycles performed consecutively are the target cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 118 of 794 rej09b0237-0500 bit bit name initial value r/w description 27 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 26 25 iwrwd1 iwrwd0 1 1 r/w r/w idle cycles for another space read-write specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. the read and write cycles which are performed consecutively and are accessed to different areas are the target cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 24 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 23 22 iwrws1 iwrws0 1 1 r/w r/w idle cycles for read-write in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. the read and write cycles which are performed consecutively and are accessed to the same area are the target cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 21 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 119 of 794 rej09b0237-0500 bit bit name initial value r/w description 20 19 iwrrd1 iwrrd0 1 1 r/w r/w idle cycles for read-read in another space specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. the read and read cycles which are performed consecutively and are accessed to different areas are the target cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 18 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 17 16 iwrrs1 iwrrs0 1 1 r/w r/w idle cycles for read-read in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the area. the read and read cycles which are performed consecutively and are accessed to the same area are the target cycle. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 120 of 794 rej09b0237-0500 bit bit name initial value r/w description 15 14 13 12 type3 type2 type1 type0 0 0 0 0 r/w r/w r/w r/w memory type specify the type of memory connected to the area. 0000: normal space 0001: reserved (setting prohibited) 0010: reserved (setting prohibited) 0011: byte-selection sram 0100: sdram 0101: pcmcia 0110: reserved (setting prohibited) 0111: reserved (setting prohibited) 1000: reserved (setting prohibited) 1001: reserved (setting prohibited) 1010: reserved (setting prohibited) 1011: reserved (setting prohibited) 1100: reserved (setting prohibited) 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) for details on memory type in each area, see tables 7.2 and 7.3. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 121 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 bsz1 bsz0 1 * 1 * r/w r/w data bus size specify the data bus width of each area. 00: reserved (setting prohibited) 01: 8 bits 10: 16 bits 11: 32 bits notes: 1. the data bus width for area 0 is specified by the external pin. these bits are ignored. 2. when area 5 or 6 is specified as pcmcia space, the bus width can be specified as either 8 bits or 16 bits. 3. if area 3 is specified as sdram space, the bus width cannot be specified as 8 bits. 4. these bits must be specified to either 01 or 11 before accessing to memory in other than area 0. 8 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * cs0bcr fetches the external pin state (md3) that specify the bus width at a power-on reset. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 122 of 794 rej09b0237-0500 7.4.3 csn space wait control register (csnwcr) (n = 0, 3, 4, 5b, 6b) csnwcr specifies various wait cycles for memory accesses. the bit c onfiguration of this register varies as shown below according to the memory type (type3, type2, type1, or type0) specified by the csn space bus control register (csnbcr). specify csnwcr before accessing the target area. specify csnbcr first, then specify csnwcr. normal space, byte-selection sram: ? cs0wcr bit bit name initial value r/w description 31 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 123 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd, wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 124 of 794 rej09b0237-0500 ? cs3wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing (signal used as strobe) and asserts the rd/ wr signal during the write access cycle (signal used as status) 1: asserts the wen ( ben ) signal during the read/write access cycle (used as status) and asserts the rd/ wr signal at the write timing (used as strobe) 19 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 125 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? cs4wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing (signal used as strobe) and asserts the rd/ wr signal during the write access cycle (signal used as status) 1: asserts the wen ( ben ) signal during the read/write access cycle (signal used as status)and asserts the rd/ wr signal at the write timing (signal used as strobe) 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 126 of 794 rej09b0237-0500 bit bit name initial value r/w description 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: same number of cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 127 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 128 of 794 rej09b0237-0500 ? cs5bwcr bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: same number of cycles as wr3 to wr0 setting (read access wait) 001: 0 cycle 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 129 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 130 of 794 rej09b0237-0500 ? cs6bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing (signal used as strobe) and asserts the rd/ wr signal during the write access cycle (signal used as status) 1: asserts the wen ( ben ) signal during the read/write access cycle (used as status) and asserts the rd/ wr signal at the write timing (used as strobe) 19 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 131 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd, wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycles 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 132 of 794 rej09b0237-0500 sdram: ? cs3wcr bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 13 wtrp1 wtrp0 0 0 r/w r/w wait cycle number for precharge completion specify the number of minimu m wait cycles inserted to wait for the completion of precharge in the following cases. ? from the start of auto-prec harge to the issuing of the actv command for the same bank. ? from the issuing of the pre/pall command to the issuing of the actv command for the same bank. ? from the issuing of the pall command during auto- refreshing to the issuing of the ref command. ? from the issuing of the pall command during self- refreshing to the issuing of the self command. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 10 wtrcd1 wtrcd0 0 1 r/w r/w wait cycle number from actv command to read(a)/writ(a) command specify the number of minimu m wait cycles from issuing the actv command to issuing the read(a)/writ(a) command. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 133 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 7 a3cl1 a3cl0 1 0 r/w r/w cas latency for area 3. specify the cas latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: reserved (setting prohibited) 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 trwl1 trwl0 0 0 r/w r/w wait cycle number for precharge start wait specify the number of minimu m wait cycles inserted to wait for the start of prechar ge in the following cases. ? from the issuing of the writa command by this lsi to the start of the auto- precharge in the sdram. the actv command for the same bank is issued after issuing the writa command in non-bank active mode. to confirm how many cycles should be needed in the sdram between receiving the writa command and the auto-precharge start, re fer to the data sheets for each sdram. set this bit so that the cycle number in that data sheets should not exceed the cycle number set by this bit. ? from the issuing of the writ command by this lsi to the issuing of the pre command. a different row address in the same bank is accessed in bank active mode. 00: 0 cycle (no wait cycle) 01: 1 cycle 10: 2 cycles 11: 3 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 134 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 wtrc1 wtrc0 0 0 r/w r/w idle cycle number from ref command/self-refreshing release to actv/ref/mrs command specify the number of mi nimum idle cycles in the following cases. ? from the issuing of the ref command to the issuing of the actv/ref/mrs command. ? from the self-refreshing rele ase to the issuing of the actv/ref/mrs command. 00: 2 cycles 01: 3 cycles 10: 5 cycles 11: 8 cycles pcmcia: ? cs5bwcr, cs6bwcr bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 20 sa1 sa0 0 0 r/w r/w space attribute specification specify memory card interfac e or i/o card interface when the pcmcia interface is selected. ? sa1 0: specifies memory card interface when a25 = 1 1: specifies i/o card interface when a25 = 1 ? sa0 0: specifies memory card interface when a25 = 0 1: specifies i/o card interface when a25 = 0 section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 135 of 794 rej09b0237-0500 bit bit name initial value r/w description 19 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 13 12 11 ted3 ted2 ted1 ted0 0 0 0 0 r/w r/w r/w r/w delay from address to rd or we assert specify the delay time from address output to rd or we assertion in pcmcia interface. 0000: 0.5 cycles 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: reserved (setting prohibited) 1001: reserved (setting prohibited) 1010: reserved (setting prohibited) 1011: reserved (setting prohibited) 1100: reserved (setting prohibited) 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 136 of 794 rej09b0237-0500 bit bit name initial value r/w description 10 9 8 7 pcw3 pcw2 pcw1 pcw0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 137 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 2 1 0 teh3 teh2 teh1 teh0 0 0 0 0 r/w r/w r/w r/w delay from rd or we negate to address specify the address hold time from rd or we negation in the pcmcia interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 138 of 794 rej09b0237-0500 7.4.4 sdram control register (sdcr) sdcr specifies the method to refresh and acce ss sdram, and the types of sdrams to be connected. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 rfsh 0 r/w refresh control specifies whether or not the refreshing sdram is performed. 0: refreshing is not performed 1: refreshing is performed 10 rmode 0 r/w refresh control specifies whether to perform auto-refreshing or self- refreshing when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 1, self-refreshing starts immediately. when the rfsh bit is 1 and this bit is 0, auto-refreshing starts according to the conten ts that are set in rtcsr, rtcnt, and rtcor. 0: auto-refreshing is performed 1: self-refreshing is performed 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 bactv 0 r/w bank active mode specifies whether to access in auto-precharge mode (using reada and writa commands) or in bank active mode (using read and writ commands). 0: auto-precharge mode (using reada and writa commands) 1: bank active mode (using read and writ commands) 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 139 of 794 rej09b0237-0500 bit bit name initial value r/w description 4 3 a3row1 a3row0 0 0 r/w r/w number of bits of row address for area 3 specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: reserved (setting prohibited) 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 a3col1 a3col0 0 0 r/w r/w number of bits of column address for area 3 specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: reserved (setting prohibited) 7.4.5 refresh timer contro l/status register (rtcsr) rtcsr specifies various items about refresh for sdram. when rtcsr is written to, the upper 16 bits of the write data must be h'a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 140 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 cmf 0 r/w compare match flag indicates that a compare matc h occurs between the refresh timer counter (rtcnt) and refres h time constant register (rtcor). [clearing condition] when 0 is written to this bit after reading rtcsr with cmf = 1. [setting condition] when rtcnt value matches rtcor value 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select select the clock input to coun t-up the refresh timer counter (rtcnt). 000: stop the counting-up 001: b /4 010: b /16 011: b /64 100: b /256 101: b /1024 110: b /2048 111: b /4096 section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 141 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 1 0 rrc2 rrc1 rrc0 0 0 0 r/w r/w r/w refresh count specify the number of consecut ive refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (rtcnt) and the refresh time constant register (rtcor). using consecutive refresh cycles can prolong cycles between refreshing. 000: once 001: twice 010: 4 times 011: 6 times 100: 8 times 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) 7.4.6 refresh time r counter (rtcnt) rtcnt is an 8-bit counter that increments using the clock selected by bi ts cks2 to cks0 in rtcsr. when rtcnt matches rtcor, rtcnt is cleared to 0. the value in rtcnt returns to 0 after counting up to 255. when rtcnt is writte n to, the upper 16 bits of the write data must be h'a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 142 of 794 rej09b0237-0500 7.4.7 refresh time constant register (rtcor) rtcor is an 8-bit register. when rtcor matche s rtcnt, the cmf bit in rtcsr is set to 1 and rtcnt is cleared to 0. when the rfsh bit in sdcr is 1, a memory refresh request is issued. the request is maintained until the refresh operatio n is performed. if the request is not processed when the next matching occurs, the previous request is ignored. when the rtcor is written to, the upper 16 bits of the write data must be h'a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 143 of 794 rej09b0237-0500 7.5 operation 7.5.1 endian/access size and data alignment this lsi supports big endian, in which the most significant byte (msbyte) of multiple byte data is stored in the lower address, and little endian, in which the least significant byte (lsbyte) of multiple byte data is stored in the lower address. endian is specified at a power-on reset by the external pin (md5). when pin md5 is driven low at a power-on reset, the endian will become big endian and when pin md5 is driven high at a power-on reset, the endian will become little endian. three data bus widths (8, 16, and 32 bits) are available for normal memory and byte-selection sram. two data bus widths (16 and 32 bits) are available for sdram. two data bus widths (8 and 16 bits) are available for pcmcia interface. data alignment is performed in accordance with the data bus width of the device and endian. this also means that when longword data is read from a byte-width device, the read operation must be done four times. in this lsi, data alignment and conversion of data length is performed au tomatically between th e respective interfaces. tables 7.6 to 7.11 show the relationship between endian, devi ce data width, and access unit. table 7.6 32-bit external device/bi g endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 data 7 to 0 ? ? ? assert ? ? ? byte access at 1 ? data 7 to 0 ? ? ? assert ? ? byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 data 15 to 8 data 7 to 0 ? ? assert assert ? ? word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 144 of 794 rej09b0237-0500 table 7.7 16-bit external device/bi g endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? data 7 to 0 ? ? ? assert ? byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 15 to 8 ? ? assert assert longword access at 0 1st time at 0 ? ? data 31 to 24 data 23 to 16 ? ? assert assert 2nd time at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 145 of 794 rej09b0237-0500 table 7.8 8-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 15 to 8 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 7 to 0 ? ? ? assert 1st time at 2 ? ? ? data 15 to 8 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 31 to 24 ? ? ? assert 2nd time at 1 ? ? ? data 23 to 16 ? ? ? assert 3rd time at 2 ? ? ? data 15 to 8 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 7 to 0 ? ? ? assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 146 of 794 rej09b0237-0500 table 7.9 32-bit external device/bi g endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? data 7 to 0 ? ? ? assert ? ? byte access at 3 data 7 to 0 ? ? ? assert ? ? ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 data 15 to 8 data 7 to 0 ? ? assert assert ? ? longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 147 of 794 rej09b0237-0500 table 7.10 16-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? data 7 to 0 ? ? ? assert ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 1st time at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert 2nd time at 2 ? ? data 31 to 24 data 23 to 16 ? ? assert assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 148 of 794 rej09b0237-0500 table 7.11 8-bit external device/little endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d 15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 1st time at 2 ? ? ? data 7 to 0 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 15 to 8 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 3rd time at 2 ? ? ? data 23 to 16 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 31 to 24 ? ? ? assert section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 149 of 794 rej09b0237-0500 7.5.2 normal space interface basic timing: for access to a normal space, this lsi uses strobe signal output in consideration of the fact that mainly static ram will be directly connected. when using sram with a byte- selection pin, see section 7.5. 6, byte-selection sram interf ace. figure 7.3 shows the basic timings of normal space access. a no-wait norm al access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. ckio a rd/ wr rd/ wr d csn t1 t2 rd wen ( ben ) bs d read write figure 7.3 normal space basic access timing (no-wait access) there is no output signal wh ich informs external devices of the access size when reading. although the least significant bit of the address indicates the correct address when the access starts, 16-bit data is always read from a 16-bit device. when writing, only the wen ( ben ) signal for the byte to be written to is asserted. when buffers ar e placed on the data bus, the rd signal should be used to control the buffers. the rd/ wr signal indicates the same state as a read cycle (driven high) when no access has been section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 150 of 794 rej09b0237-0500 carried out. therefore, care must be taken when controlling the buffers with the rd/ wr signal, to avoid data conflict. figures 7.4 and 7.5 show the basic timings of normal sp ace consecutive access. if the wm bit in csnwcr is cleared to 0, a tnop cycle is inserted to check the external wait (figure 7.4). if the wm bit in csnwcr is set to 1, an external wait request is ignored and no tnop cycle is inserted (figure 7.5). ckio a25 to a0 rd rd/ wr d wen ( ben ) d bs wait csn t1 t2 tnop t1 t2 read write figure 7.4 consecutive access to norm al space (1): bus width = 16 bits, longword access, csnwcr.wm = 0 (a ccess wait = 0, cycle wait = 0) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 151 of 794 rej09b0237-0500 t1 t2 t1 t2 ckio a25 to a0 rd/ wr d csn rd wen ( ben ) bs wait d read write figure 7.5 consecutive access to norm al space (2): bus width = 16 bits, longword access, csnwcr.wm = 1 (a ccess wait = 0, cycle wait = 0) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 152 of 794 rej09b0237-0500 a16 a0 cs oe i/o7 i/o0 we a18 a2 csn rd d31 d24 we3 ( be3 ) d23 d16 we2 ( be2 ) d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128 kwords 8 bits sram a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we .... .... .... .... .... .... .... .... .... .... .... .... .... figure 7.6 example of 32-bit data-width sram connection section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 153 of 794 rej09b0237-0500 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128 kwords 8 bits sram a16 a0 cs oe i/o7 i/o0 we figure 7.7 example of 16-bit data-width sram connection this lsi 128 kwords x 8 bits sram a16 a0 cs oe i/o7 i/o0 we . . . a16 a0 csn rd d7 d0 we0 ( be0 ) . . . . . . . . . . . . . . . figure 7.8 example of 8-bit data-width sram connection section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 154 of 794 rej09b0237-0500 7.5.3 access wait control wait cycle insertion on a normal space access can be controlled by the settings of bits wr3 to wr0 in csnwcr. it is possible for areas 4, 5a, and 5b to insert wait cycles independently in read access and in write access. the areas other than 4, 5a, and 5b have the same access wait for read cycle and write cycle. the specified number of tw cycles is inserted as wait cycles in a normal space access shown in figure 7.9. t1 ckio a25 to a0 csn rd/ wr rd d d wen ( ben ) bs tw read write t2 figure 7.9 wait timing for normal space access (software wait only) when the wm bit in csnwcr is cleared to 0, the external wait signal ( wait ) is also sampled. the wait pin sampling is shown in figure 7.10. in this example, two wait cycles are inserted as software wait. the wait signal is sampled at the falling e dge of the ckio signal in the cycle immediately before the t2 cycle (t1 or tw cycle). section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 155 of 794 rej09b0237-0500 t1 ckio a25 to a0 csn rd/ wr rd d wen ( ben ) d wait tw tw twx t2 read write bs wait cycles inserted by wait signal figure 7.10 wait cycle ti ming for normal space access (wait cycle insertion using wait ) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 156 of 794 rej09b0237-0500 7.5.4 extension of chip select ( csn ) assertion period the number of cycles from csn assertion to rd and wen ( ben ) assertion can be specified by setting bits sw1 and sw0 in csnwcr. the number of cycles from rd and wen ( ben ) negation to csn negation can be specified by setting bits hw1 and hw0. therefore, a flexible interface to an external device can be obtained. figure 7.11 sh ows an example. a th cycle and a tf cycle are added before and after a normal cycl e, respectively. in these cycles, rd and wen ( ben ) are not asserted, while other signals are asserted. the data output is prolonged to the tf cycle, and this prolongation is useful for devices with slow writing operations. t1 ckio a25 to a0 csn rd/ wr rd d d wen ( ben ) bs th read write t2 tf figure 7.11 example of timing when csn assertion period is extended section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 157 of 794 rej09b0237-0500 7.5.5 sdram interface sdram direct connection: the sdram that can be connected to this lsi is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the a10 pin for setting precharge mode in read and write command cycles. the control signals for dir ect connection of sdram are ras , cas , rd/ wr , dqmuu, dqmul, dqmlu, dqmll, cke, and cs3 . signals other than cke are valid when cs3 is asserted. sdram can be connected to area 2. the da ta bus width of the area that is connected to sdram can be set to 16 bits or 32 bits. burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as the sdram operating mode. commands for sdram can be specified by ras , cas , rd/ wr , and specific address signals. these commands are shown below. ? nop ? auto-refreshing (ref) ? self-refreshing (self) ? all banks precharge (pall) ? specified bank precharge (pre) ? bank active (actv) ? read (read) ? read with precharge (reada) ? write (writ) ? write with precharge (writa) ? write mode register (mrs) the byte to be accessed is specified by dqmuu, dqmul, dqmlu and dqmll. reading or writing is performed for a byte whose corresponding dqmxx is low. for details on the relationship between dqmxx and the byte to be accessed, refer to sectio n 7.5.1, endian/access size and data alignment. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 158 of 794 rej09b0237-0500 figures 7.12 and 7.13 show an example of the connection of the sdram with the lsi. a15 a2 cke ckio csn ras cas rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml .... .... .... .... .... .... .... this lsi 64-mbit sdram (1 mword x 16 bits x 4 banks) figure 7.12 example of 32-bit data-width sdram connection section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 159 of 794 rej09b0237-0500 a14 a1 cke ckio csn ras cas rd/ wr d15 d0 dqmlu dqmll 64-mbit sdram (1 mword x 16 bits x 4 banks) . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . . . . this lsi figure 7.13 example of 16-bit data-width sdram connection address multiplexing: an address multiplexing is specified so that sdram can be connected without external multiplexing circuitry according to the setting of bits bsz1 and bsz0 in csnbcr, anrow1 and anrow0 and ancol1 ancol0 in sdcr. tables 7.12 to 7.17 show the relationship between those settings and the bits output on the address pins. do not specify those bits in the manner other than this table, ot herwise the operation of this lsi is not guaranteed. a25 to a18 are not multiplexed and the original valu es of address are always output on these pins. when the data bus width is 16 bits (bsz[1:0] = b'10), pin a0 of sdram specifies a word address. therefore, connect this a0 pin of sdram to pin a1 of this lsi; pin a1 pin of sdram to pin a2 of this lsi, and so on. when the data bus width is 32 bits (bsz[1:0] = b'11), pin a0 of sdram specifies a long word addr ess. therefore, connect this a0 pin of sdram to pin a2 of this lsi; pin a1 pin of sdram to pin a3 of this lsi, and so on. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 160 of 794 rej09b0237-0500 table 7.12 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (1) setting setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) 11 (32 bits) 01 (12 bits) 00 (8 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a17 a25 a17 a17 a24 a17 a16 a24 a16 a16 a23 a16 unused a15 a23 a15 unused a15 a23 * 2 a23 * 2 a13 (ba1) a14 a22 * 2 * 3 a22 * 2 * 3 a12 (ba1) a14 a22 * 2 a22 * 2 a12 (ba0) specifies bank a13 a21 * 2 a21 * 2 a11 (ba0) specifies bank a13 a21 a13 a11 address a12 a20 l/h * 1 a10/ap specifies address/ precharge a12 a20 l/h * 1 a10/ap specifies address/ precharge a11 a19 a11 a9 a11 a19 a11 a9 a10 a18 a10 a8 a10 a18 a10 a8 a9 a17 a9 a7 a9 a17 a9 a7 a8 a16 a8 a6 a8 a16 a8 a6 a7 a15 a7 a5 a7 a15 a7 a5 a6 a14 a6 a4 a6 a14 a6 a4 a5 a13 a5 a3 a5 a13 a5 a3 a4 a12 a4 a2 a4 a12 a4 a2 a3 a11 a3 a1 a3 a11 a3 a1 a2 a10 a2 a0 address a2 a10 a2 a0 address section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 161 of 794 rej09b0237-0500 setting setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) 11 (32 bits) 01 (12 bits) 00 (8 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a1 a9 a1 a1 a9 a1 a0 a8 a0 unused a0 a8 a0 unused example of memory connection example of memory connection one 64-mbit product (512 kwords x 32 bits x 4 banks, 8- bit column product) two 16-mbit products (512 kwords x 16 bits x 2 banks, 8- bit column product) one 128-mbit product (1 mword x 32 bits x 4 banks, 8-bit column product) two 64-mbit product (1 mword x 16 bits x 4 banks, 8-bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification 3. applicable only to a 64-mbit product table 7.13 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (2) setting setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) 11 (32 bits) 01 (12 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a17 a26 a17 a17 a27 a17 a16 a25 a16 unused a16 a26 a16 unused a15 a24 * 2 a24 * 2 a13 (ba1) a15 a25 * 2 a25 * 2 a13 (ba1) a14 a23 * 2 a23 * 2 a12 (ba0) specifies bank a14 a24 * 2 a24 * 2 a12 (ba0) specifies bank section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 162 of 794 rej09b0237-0500 setting setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) 11 (32 bits) 01 (12 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a13 a22 a13 a11 address a13 a23 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/ precharge a12 a22 l/h * 1 a10/ap specifies address/ precharge a11 a20 a11 a9 a11 a21 a11 a9 a10 a19 a10 a8 a10 a20 a10 a8 a9 a18 a9 a7 a9 a19 a9 a7 a8 a17 a8 a6 a8 a18 a8 a6 a7 a16 a7 a5 a7 a17 a7 a5 a6 a15 a6 a4 a6 a16 a6 a4 a5 a14 a5 a3 a5 a15 a5 a3 a4 a13 a4 a2 a4 a14 a4 a2 a3 a12 a3 a1 a3 a13 a3 a1 a2 a11 a2 a0 address a2 a12 a2 a0 address a1 a10 a1 a1 a11 a1 a0 a9 a0 unused a0 a10 a0 unused example of memory connection example of memory connection one 256-mbit product (2 mwords x 32 bits x 4 banks, 9- bit column product) two 128-mbit products (2 mwords x 16 bits x 4 banks, 9- bit column product) one 512-mbit product (4 mwords x 32 bits x 4 banks, 10- bit column product) two 256-mbit product (4 mwords x 16 bits x 4 banks, 10- bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 163 of 794 rej09b0237-0500 table 7.14 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (3) setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) output pins of this lsi output row address output column address pins of sdram function a17 a26 a17 unused a16 a25 * 2 a25 * 2 a14 (ba1) a15 a24 * 2 a24 * 2 a13 (ba0) specifies bank a14 a23 a14 a12 a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of memory connection one 512-mbit product (4 mwords x 32 bits x 4 banks, 9-bit column product) two 256-mbit products (4 mwords x 16 bits x 4 banks, 9-bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 164 of 794 rej09b0237-0500 table 7.15 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (4) setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) 10 (16 bits) 01 (12 bits) 00 (8 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a17 a25 a17 a17 a25 a17 a16 a24 a16 a16 a24 a16 a15 a23 a15 a15 a23 a15 unused a14 a22 a14 a14 a22 * 2 a22 * 2 a13 (ba1) a13 a21 a21 unused a13 a21 * 2 a21 * 2 a12 (ba0) specifies bank a12 a20 * 2 a20 * 2 a11 (ba0) specifies bank a12 a20 a12 a11 address a11 a19 l/h * 1 a10/ap specifies address/ precharge a11 a19 l/h * 1 a10/ap specifies address/ precharge a10 a18 a10 a9 address a10 a18 a10 a9 a9 a17 a9 a8 a9 a17 a9 a8 a8 a16 a8 a7 a8 a16 a8 a7 a7 a15 a7 a6 a7 a15 a7 a6 a6 a14 a6 a5 a6 a14 a6 a5 a5 a13 a5 a4 a5 a13 a5 a4 a4 a12 a4 a3 a4 a12 a4 a3 a3 a11 a3 a2 a3 a11 a3 a2 a2 a10 a2 a1 a2 a10 a2 a1 a1 a9 a1 a0 a1 a9 a1 a0 address a0 a8 a0 unused a0 a8 a0 unused section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 165 of 794 rej09b0237-0500 setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) 10 (16 bits) 01 (12 bits) 00 (8 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function example of memory connection example of memory connection one 16-mbit product (512 kwords x 16 bits x 2 banks, 8- bit column product) one 64-mbit products (1 mword x 16 bits x 4 banks, 8-bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification table 7.16 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (5) setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) 10 (16 bits) 01 (12 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a17 a26 a17 a17 a27 a17 a16 a25 a16 a16 a26 a16 a15 a24 a15 unused a15 a25 a15 unused a14 a23 * 2 a23 * 2 a13 (ba1) a14 a24 * 2 a24 * 2 a13 (ba1) a13 a22 * 2 a22 * 2 a12 (ba0) specifies bank a13 a23 * 2 a23 * 2 a12 (ba0) specifies bank a12 a21 a12 a11 address a12 a22 a12 a11 address section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 166 of 794 rej09b0237-0500 setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) 10 (16 bits) 01 (12 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a11 a20 l/h * 1 a10/ap specifies address/ precharge a11 a21 l/h * 1 a10/ap specifies address/ precharge a10 a19 a10 a9 a10 a20 a10 a9 a9 a18 a9 a8 a9 a19 a9 a8 a8 a17 a8 a7 a8 a18 a8 a7 a7 a16 a7 a6 a7 a17 a7 a6 a6 a15 a6 a5 a6 a16 a6 a5 a5 a14 a5 a4 a5 a15 a5 a4 a4 a13 a4 a3 a4 a14 a4 a3 a3 a12 a3 a2 a3 a13 a3 a2 a2 a11 a2 a1 a2 a12 a2 a1 a1 a10 a1 a0 address a1 a11 a1 a0 address a0 a9 a0 unused a0 a10 a0 unused example of memory connection example of memory connection one 128-mbit product (2 mwords x 16 bits x 4 banks, 9- bit column product) one 256-mbit product (4 mwords x 16 bits x 4 banks, 10- bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 167 of 794 rej09b0237-0500 table 7.17 relationship between register settings (a3bsz[1:0], a3row[1:0], and a3col[1:0]) and address multiplex output (6) setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) 10 (16 bits) 10 (13 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function a17 a26 a17 a17 a27 a17 a16 a25 a16 unused a16 a26 a16 unused a15 a24 * 2 a24 * 2 a14 (ba1) a15 a25 * 2 a25 * 2 a14 (ba1) a14 a23 * 2 a23 * 2 a13 (ba0) specifies bank a14 a24 * 2 a24 * 2 a13 (ba0) specifies bank a13 a22 a13 a12 a13 a23 a13 a12 a12 a21 a12 a11 address a12 a22 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/ precharge a11 a21 l/h * 1 a10/ap specifies address/ precharge a10 a19 a10 a9 a10 a20 a10 a9 a9 a18 a9 a8 a9 a19 a9 a8 a8 a17 a8 a7 a8 a18 a8 a7 a7 a16 a7 a6 a7 a17 a7 a6 a6 a15 a6 a5 a6 a16 a6 a5 a5 a14 a5 a4 a5 a15 a5 a4 a4 a13 a4 a3 a4 a14 a4 a3 a3 a12 a3 a2 a3 a13 a3 a2 a2 a11 a2 a1 a2 a12 a2 a1 a1 a10 a1 a0 address a1 a11 a1 a0 address a0 a9 a0 unused a0 a10 a0 unused section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 168 of 794 rej09b0237-0500 setting setting a3 bsz [1:0] a3 row [1:0] a3 col [1:0] a3 bsz [1:0] a3 row [1:0] a3 col [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) 10 (16 bits) 10 (13 bits) 10 (10 bits) output pins of this lsi output row address output column address pins of sdram function output pins of this lsi output row address output column address pins of sdram function example of memory connection example of memory connection one 256-mbit product (4 mwords x 16 bits x 4 banks, 9- bit column product) one 512-mbit product (8 mwords x 16 bits x 4 banks, 10- bit column product) notes: 1. l/h is a bit used in the command specific ation; it is fixed low or high according to the access mode. 2. bank address specification burst read: a burst read occurs in the fo llowing cases with this lsi. 1. access size in reading is larger than data bus width. 2. 16-byte transf er in cache miss. 3. 16-byte transfer by dmac and e-dmac (access to non-cacheable area) this lsi always accesses the sdram with burst length 1. for example, read access of burst length 1 is performed consecutively four times to read 16-byte consecutive data from the sdram that is connected to a 32-bit data bus. th e number of bursts in this access is four. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 169 of 794 rej09b0237-0500 table 7.18 shows the relationship between the access size and the number of bursts. table 7.18 relationship between access size and number of bursts bus width access size number of bursts 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 32 bits 8 bits 1 16 bits 1 32 bits 1 16 bytes 4 figures 7.14 and 7.15 show timing charts in burst read. in burst read, the actv command is output in the tr cycle, the read command is issued in the tc1, tc2, and tc3 cycles, the reada command is issued in the tc4 cycle, and the read data is latched at the rising edge of the external clock (ckio) in the td1 to td4 cycles. the tap cycle is used to wait for the completion of an auto-precharge induced by the read comman d in the sdram. in the tap cycle, a new command will not be issued to the same bank. ho wever, other banks can be accessed. the number of tap cycles is specified by bits wtrp1 and wtrp0 in cs3wcr. in this lsi, wait cycles can be inserted by specifying bits in csnwcr to connect the sdram with variable frequencies. figure 7.15 shows an example in which wait cycles are inserted. the number of cycles from the tr cycle where the actv command is output to the tc1 cycle where the reada command is output can be specified using bits wtrcd1 and wtrcd0 in cs3wcr. when bits wtrcd1 and wtrcd0 is set to one cycle or more, a trw cycle where the nop command is issued is inserted between the tr cycl e and tc1 cycle. the number of cycles from the tc1 cycle where the reada command is output to the td1 cycle where the read data is latched can be specified by bits a3cl1 and a3cl0 bits in cs3wcr in cs3wcr. this number of cycles corresponds to the synchronous dram cas latency. the cas latency for the synchronous dram is normally defined as up to three cycles . however, the cas latency in this lsi can be specified as one to four cycles . this cas latency can be achieved by connecting a latch circuit between this lsi and the synchronous dram. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 170 of 794 rej09b0237-0500 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d bs tap tr tc2 tc3 tc1 td4 tde td2 td3 td1 a11 * cas note: * address pin to be connected to pin a10 of sdram. figure 7.14 burst read ba sic timing (auto precharge) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 171 of 794 rej09b0237-0500 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx bs tap tr tc2 tc3 tc1 td4 tde td2 td3 td1 cas trw tw d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.15 burst read wait sp ecification timing (auto precharge) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 172 of 794 rej09b0237-0500 single read: a read access ends in one cycle when data exists in non-cacheab le area and the data bus width is larger than or equal to access size. si nce the burst length is set to 1 in synchronous dram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. figure 7.16 shows the single read basic timing. a25 to a0 csn rd/ wr ras dqmxx bs tap tr tc1 tde td1 cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.16 basic timing fo r single read (auto precharge) burst write: a burst write occurs in the fo llowing cases in this lsi. 1. access size in writing is larger than data bus width. 2. write-back of the cache 3. 16-byte transfer by dmac and e-dmac (access to non-cacheable area) this lsi always accesses sdram with burst length 1. for example, write access of burst length 1 is performed consecutively four times to write 16 -byte consecutive data to the sdram that is connected to a 32-bit data bus. the relationship between the access size and the number of bursts is shown in table 7.18. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 173 of 794 rej09b0237-0500 figure 7.17 shows a timing chart for burst writes. in burst write, the actv command is output in the tr cycle, the writ command is issued in the tc1, tc2, and tc3 cycles, and the writa command is issued to execute an auto-precharge in the tc4 cycle. in the write cycle, the write data is output simultaneously with the write comm and. after the write command with the auto- precharge is output, the trw1 cycle that waits for the auto-precharge initiation is followed by the tap cycle that waits for completion of the auto-p recharge induced by the writa command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, other cs areas and other banks can be accessed. the number of tr w1 cycles is specified by bits trwl1 and trwl0 in cs3wcr. the number of tap cycles is specified by bits wtrp1 and wtrp0 in cs3wcr. tc4 ckio a25 to a0 csn rd/ wr ras dqmxx bs tap tr tc2 tc3 tc1 trwl cas d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.17 basic timing fo r burst write (auto precharge) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 174 of 794 rej09b0237-0500 single write: a write access ends in one cycle when data is written in non-cacheable area and the data bus width is larger than or equal to access size. figure 7.18 shows the single write basic timing. a25 to a0 csn rd/ wr ras dqmxx bs tap tr tc1 trwl cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.18 basic timing for single write (auto-precharge) bank active: the synchronous dram bank function is used to support high-speed accesses to the same row address. when the bactv bit in sdcr is 1, accesses are performed using commands without auto-precharge (read or writ). th is function is called bank-active function. when a bank-active function is used, prechargin g is not performed when the access ends. when accessing the same row address in the same bank , it is possible to is sue the read or writ command immediately, without issuing an actv command. since synchronous dram is internally divided into several banks, it is possible to keep one row address in each bank activated. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer becau se of the precharging performed after the access request is issued. the number of cycles between issuance of the pre command and the actv command is determined by bits wtrp1 and wtrp0 in csnwcr. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 175 of 794 rej09b0237-0500 in a write access, when an auto-precharge is perf ormed, a command cannot be issued to the same bank for a period of trwl + tap cycles after i ssuance of the writa comm and. when bank active mode is used, read or writ command can be issued successively if the row address is the same. the number of cycles can thus be re duced by trwl + tap cycles for each write. there is a limit on tras, the time for placing each bank in the active state. if there is no guarantee that another row address will be accessed within the period in which this va lue is maintained by program execution, it is necessary to set auto-refreshing and set the refresh cycle to no more than the maximum value of tras. a burst read cycle without auto-precharge is shown in figure 7.19, a burst read cycle for the same row address in figure 7.20, and a burst read cy cle for different row addresses in figure 7.21. likewise, a single write cycle with out auto-precharge is shown in figure 7.22, a single write cycle for the same row address in figure 7.23, and a si ngle write cycle for different row addresses in figure 7.24. in figure 7.20, a tnop cycle in which no operation is performed is inserted be fore the tc cycle that issues the read command. the tnop cycle is inse rted to secure two cycles of cas latency for the dqmxx signal that specifies which byte data is read from sdram. if the cas latency is specified as two cycles or more, the tnop cycle is not inserted because the two cycles of latency can be secured even if the dqmxx sign al is asserted after the tc cycle. when bank active mode is set, if only acce sses to the respective banks in the area 3 are considered, as long as accesses to the same row address co ntinue, the operation starts with the cycle in figure 7.19 or 7.22, fo llowed by repetition of the cycle in figure 7.20 or 7.23. an access to a different area during this ti me has no effect. when a differe nt row address is accessed in the bank active state, the bus cycle shown in figure 7.21 or 7.24 is executed instead of that in figure 7.20 or 7.23. in bank active mode, too, all banks become inactive after a refresh cycle. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 176 of 794 rej09b0237-0500 tc4 a25 to a0 csn rd/ wr ras dqmxx bs tr tc2 tc3 tc1 td4 td2 td3 td1 tde cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.19 burst read timing (no auto precharge) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 177 of 794 rej09b0237-0500 tc4 a25 to a0 csn rd/ wr ras dqmxx bs tc2 tc3 tc1 tnop td4 tde td2 td3 td1 cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.20 burst read timing (bank active, same row address) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 178 of 794 rej09b0237-0500 tc4 ckio a25 to a0 csn rd/ wr bs tpw tp tc2 tc3 tc1 td4 td2 td3 td1 tde tr ras dqmxx cas d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.21 burst read timing (b ank active, differen t row addresses) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 179 of 794 rej09b0237-0500 a25 to a0 csn rd/ wr bs tr tc1 ras dqmxx cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.22 single write timing (no auto precharge) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 180 of 794 rej09b0237-0500 a25 to a0 csn rd/ wr bs tnop tc1 ras dqmxx cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.23 single write timing (bank active, same row address) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 181 of 794 rej09b0237-0500 a25 to a0 csn rd/ wr bs tpw tp tc1 tr ras dqmxx cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.24 single write timing (bank active, differen t row addresses) refreshing: this lsi has a function for controlling synchronous dram refreshing. auto- refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in sdcr. a consecutive refreshing can be performed by setting bits rrc2 to rrc0 in rtcsr. if synchronous dram is not accessed for a long period, self-refreshing mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. 1. auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks2 to cks0 in rtcsr, and the value set by in rt cor. the value of bits cks[2:0] in rtcor should be set so as to satisfy the given refresh interval for the synchronous dram used. first make the settings for rtcor, rtcnt, and the rmode, then make the cks[2:0] and rrc[2:0] settings. when the clock is selected by bits cks[2:0], rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated and an auto-refreshing is performed for the number of times specified by the rrc[2:0]. at the same time, rtcnt is cleared to 0 and the count-up is restarted. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 182 of 794 rej09b0237-0500 figure 7.25 shows the auto-refreshing cycle timing. after starting the auto-refreshing, pall command is issued in the tp cy cle to make all the banks to pr echarged state from active state when some bank is being precharged. then the ref command is issued in the trr cycle after inserting idle cycles of which number is specified by bits wtrp1 and wtrp0 in csnwcr. a new command is not issued for the duration of the number of cycles specified by bits wtrc1 and wtrc0 in csnwcr after the trr cycle. bits wtrc1 and wtrc0 in csnwcr must be set so as to satisfy the sdram refreshing cycl e time (trc). a tpw cycle is inserted between the tp cycle and trr cycle when the setting of bits wtrp1 and wtrp0 in csnwcr is longer than or equal to two cycles. a25 to a0 csn rd/ wr bs tpw tp trr trc trc trc hi-z ras dqmxx cas ckio d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.25 auto-refreshing timing section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 183 of 794 rej09b0237-0500 2. self-refreshing when self-refreshing mode is selected, the refresh timing and refresh addresses are generated within the synchronous dram. self-refreshing is activated by setting both the rmode bit and the rfsh bit in sdcr to 1. after startin g the self-refreshing, the pall command is issued in the tp cycle after the completion of pre-charging the bank. the self command is then issued after inserting idle cycles of wh ich the number is specified by bits wtrp1 and wtrp0 in csnwsr. sy nchronous dram cannot be accesse d while self-refreshing. self- refreshing mode is cleared by clearing the rmode bit to 0. after self-refreshing mode has been cleared, command issuance is disabled for th e number of cycles sp ecified by bits wtrc1 and wtrc0 in csnwcr. self-refreshing timing is shown in figure 7.26. settings must be made immediately after clearing self-refreshing mode so that auto-refreshing is perform ed at the correct intervals. when self-refreshing is activat ed from the auto-refreshing mode, only clearing the rmode bit to 1 resumes auto-refreshing mode. if it takes lo ng time to start the auto-refreshing, setting rtcnt to the value of rtcor ? 1 starts the auto-re freshing immediately. after self-refreshing has been set, the self-refreshing mode continues even in standby mode, and is maintained even after recovery from standby mode by an interrupt. since the bsc registers are initialized at a power-o n reset, the self-refresh ing mode is cleared. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 184 of 794 rej09b0237-0500 ckio a25 to a0 csn rd/ wr bs tpw tp trr trc trc trc hi-z trc trc cke ras dqmxx cas d a11 * note: * address pin to be connected to pin a10 of sdram. figure 7.26 self-refreshing timing relationship between refresh requests and bus cycles: if a refresh request occurs during bus cycle execution, the refresh cycle must wa it for the bus cycle to be completed. if a new refresh request occurs while the previous refresh request is not performed, the previous refresh request is deleted. to refresh correctly, a bus cycle longer than the refresh interval or the bus busy must be prevented. power-on sequence: in order to use synchronous dram, mode setting must first be performed after turning the power on. to perform synchronous dram initialization correctly, the bsc registers must first be set, followed by writing to the synchronous dram mode register. when writing to the synchronous dram mode register, the address signal value at that time is latched by a combination of the csn , ras , cas , and rd/ wr signals. if the value to be set is x, write to the address of h'f8fd5000 + x in words. in this operation, the data is ignored. to set burst read/single write, burst read/burst write, cas late ncy 2 to 3, wrap type = sequential, and burst length 1 supported by the lsi, arbitrary data is written to the addresses shown in table 7.19 in bytes. in this case, 0s are output at the external address pins of a12 or later. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 185 of 794 rej09b0237-0500 table 7.19 access address for sdram mode register write ? burst read/single write (burst length 1) data bus width cas latency access address external address pin 16 bits 2 h'f8fd5440 h'0000440 3 h'f8fd5460 h'0000460 32 bits 2 h'f8fd50880 h'0000880 3 h'f8fd58c0 h'00008c0 ? burst read/burst write (burst length 1) data bus width cas latency access address external address pin 16 bits 2 h'f8fd5040 h'0000040 3 h'f8fd5060 h'0000060 32 bits 2 h'f8fd5080 h'0000080 3 h'f8fd50c0 h'00000c0 mode register setting timing is shown in figure 7.27. the pall command (all bank precharge command) is firstly issued. the ref command (a uto-refreshing command) is then issued eight times. the mrs command (mode register write command) is finally issued. idle cycles, of which number is specified by bits wtrp1 and wtrp0 in csnwcr, are inserted between the pall and the first ref commands. idle cy cles, of which number is speci fied by bits wtrc1 and wtrc0 in csnwcr, are inserted between the ref an d ref commands, and between the 8th ref and mrs commands. in addition, one or more idle cycles are inserted between the mrs and the next command. it is necessary to keep idle time of certain cy cles for sdram before is suing the pall command after turning the power on. refer the manual of the sdram for the idle time to be needed. when the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be ta ken when the pulse width of the reset signal is shorter than the idle time. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 186 of 794 rej09b0237-0500 ckio a25 to a0 csn rd/ wr ras dqmxx d bs tpw tp trr a11 * cas note: * address pin to be connected to pin a10 of sdram. trc trc tmw hi-z tnop trc trr trc ref ref mrs pall figure 7.27 write timing for sdram mode register (based on jedec) 7.5.6 byte-selection sram interface the byte-selection sram interface is for acce ss to sram which has a byte-selection pin ( wen ( ben )). this interface is used to access to sram wh ich has 16-bit data pi ns and upper and lower byte selection pins, such as ub and lb. when the bas bit in csnwcr is cleared to 0 (i nitial value), the write access timing of the byte- selection sram interface is the same as that fo r the normal space interface. while in read access of a byte-selection sr am interface, the byte-selection signal is output from the wen ( ben ) pin, which is different from that for the normal sp ace interface. the basic access timing is shown in figure 7.28. in write access, data is written to the memory according to the timing of the byte- selection pin ( wen ( ben )). for details, refer to the data sheet for the corresponding memory. if the bas bit in csnwcr is set to 1, the wen ( ben ) pin and rd/ wr pin timings change. the basic access timing is shown in figure 7.29. in write access, data is wr itten to the memory according to the timing of the write enable pin (rd/ wr ). the data hold timing from rd/ wr negation to data write must be secured by setting bits hw1 to hw0 in csnwcr. figure 7.30 shows the access timing when a so ftware wait is specified. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 187 of 794 rej09b0237-0500 ckio a25 to a0 csn wen ( ben ) rd/ wr rd rd d d rd/ wr bs read write t1 t2 high figure 7.28 basic access timing fo r byte-selection sram (bas = 0) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 188 of 794 rej09b0237-0500 ckio a25 to a0 csn wen ( ben ) rd rd d d rd/ wr rd/ wr bs read write t1 t2 high figure 7.29 basic access timing fo r byte-selection sram (bas = 1) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 189 of 794 rej09b0237-0500 t2 ckio a25 to a0 csn rd/ wr wen ( ben ) d bs read write th th t1 tw rd rd/ wr d rd high figure 7.30 wait timing for byte-select ion sram (bas = 1) (software wait only) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 190 of 794 rej09b0237-0500 a15 a0 cs oe we i/o15 i/o0 ub lb a17 a2 csn rd rd/ wr d31 d16 we3 ( be3 ) we2 ( be2 ) d15 d0 we1 ( be1 ) we0 ( be0 ) a15 a0 cs oe we i/o15 i/o0 ub lb .... .... .... .... .... .... .... this lsi 64 kwords x 16 bits sram figure 7.31 example of connection with 32-bit data-width byte-selection sram this lsi a16 a1 csn rd rd/ wr d15 d0 we1 ( be1 ) we0 ( be0 ) a16 a1 cs oe we i/o 15 i/o 0 ub lb 64 kwords x 16 bits sram ... ... ... ... figure 7.32 example of connection with 16-bit data-width byte-selection sram section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 191 of 794 rej09b0237-0500 7.5.7 pcmcia interface with this lsi, if addr ess map 2 is selected using the map bit in cmncr, the pcmcia interface can be specified in areas 5 and 6. areas 5 and 6 in the physical space can be used for the ic memory card and i/o card interface defined in th e jeida specifications ve rsion 4.2 (pcmcia2.1 rev. 2.1) by specifying bits type3 to type0 in csnbcr (n = 5b and 6b) to b'0101. in addition, bits sa1 and sa0 in csnwcr (n = 5b and 6b) assign the upper or lower 32 mbytes of each area to an ic memory card or i/o card interface. for example, if bits sa1 and sa0 in cs5bwcr are set to 1 and cleared to 0, respectively, the upper 32 mbytes and the lowe r 32 mbytes of area 5b are used as an ic memory card interf ace and i/o card interface, respectively. when the pcmcia interface is used, the bus size must be specified as 8 bits or 16 bits using bits bsz1 and bsz0 in cs5bbcr or cs6bbcr. figure 7.33 shows an example of a connection be tween this lsi and the pcmcia card. to enable insertion and removal of the pcmcia card with th e system power turned on , tri-state buffers must be connected between the lsi and the pcmcia card. in the jeida and pcmcia standards, operation in big endian mode is not clearly defined. consequently, the provided pcmcia interface in big endian mode is available only for this lsi. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 192 of 794 rej09b0237-0500 this lsi pc card (memory or i/o) a25 to a0 d7 to d0 ce1 ce2 oe we / pgm iord iowr reg a25 to a0 d7 to d0 d15 to d8 rd/ wr ce1a ce2a rd we iciord iciowr i/o port wait iois16 g g dir g g dir d15 to d8 wait iois16 cd1, cd2 card detection circuit figure 7.33 example of pcmcia interface connection section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 193 of 794 rej09b0237-0500 basic timing for memory card interface: figure 7.34 shows the basic timing of the pcmcia ic memory card interface. if areas 5 and 6 in the physical space are speci fied as the pcmcia interface, accessing the common memory areas in areas 5 and 6 automatical ly accesses with the ic memory card interface. if the external bus frequenc y (ckio) increases, the setup times and hold times for the address pins (a25 to a0), card enable signals ( ce1a , ce2a , ce1b , ce2b ), and write data (d15 to d0) to the rd and we signals become insufficient. to prevent this error, this lsi can specify the setup times and hold ti mes for areas 5 and 6 in the physical space independently, using cs5bwcr and cs6bwcr. in the pcmcia interface, as in the normal space interface, a software wait or hardware wait can be inserted using the wait pin. figure 7.35 shows the pcmcia memory bus wait timing. tpcm1w ckio a25 to a0 cexx rd/ wr rd d we d bs read write tpcm2 tpcm1 tpcm1w tpcm1w figure 7.34 basic access timing fo r pcmcia memory card interface section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 194 of 794 rej09b0237-0500 tpcm1w ckio a25 to a0 cexx rd/ wr rd d we d bs read write tpcm2 tpcm0 tpcm1 tpcm1w tpcm0w tpcm2w tpcm1w tpcm1w wait figure 7.35 wait timing for pcmcia memory card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1) when 32 mbytes of the memory space are used as an ic memory card interf ace, a port is used to generate the reg signal that switches between the common memory and attribute memory. when the memory space used for the ic memory card in terface is 16 mbytes or less, pin a24 can be used as the reg signal by allocating 16-mbyte memory space to each the co mmon memory space and the attribute memory space. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 195 of 794 rej09b0237-0500 pcmcia interface area is 32 mbytes (an i/o port pin is used as the reg ) area 5 : h'14000000 attribute memory/common memory i/o space attribute memory/common memory i/o space area 5 : h'16000000 area 6 : h'18000000 area 6 : h'1a000000 pcmcia interface area is 16 mbytes (a24 is used as the reg ) area 5 : h'14000000 attribute memory i/o space area 5 : h'15000000 area 5 : h'16000000 h'17000000 area 6 : h'18000000 area 6 : h'19000000 area 6 : h'1a000000 h'1b000000 common memory attribute memory i/o space common memory figure 7.36 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b'10, cs6bwcr.sa[1:0] = b'10) basic timing for i/o card interface: figures 7.37 and 7.38 show the basic timings for the pcmcia i/o card interface. the i/o card and ic memory card interfaces are specified by an address to be accessed. when area 5 of the physical space is specified as the pcmcia and both bits sa1 and sa0 in cs5bwcr are set to 1, the i/o card interface can automati cally be specified by accessing the physical addresses from h'16000000 to h'17ffffff and from h'14000000 to h'15ffffff. when area 6 of the physical space is specified as the pcmc ia and both bits sa1 and sa0 in cs6bwcr are set to 1, the i/o card interface can automatically be specified by accessing the physical addresses from h'1a000000 to h'1bffffff and from h'18000000 to h'19ffffff. note that areas to be accessed as the pcmcia i/o card must be non-cached (space p2). if the pcmcia card is accessed as an i/o card in little endian m ode, dynamic bus sizing for the i/o bus can be achieved using the iois16 signal. if the iois16 signal is driven high in a word-size i/o bus cycle while the bus width of area 6 is specifi ed as 16 bits, the bus wi dth is recognized as 8 bits and data is accessed twice in units of eight bits in the i/o bus cycle to be executed. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 196 of 794 rej09b0237-0500 the iois16 signal is sampled at the falling edge of the ckio signal in the tpci0, tpci0w, and tpci1 cycles when bits te d3 to ted0 are specified as 1.5 cycl es or more, and is reflected in the ce2 signal 1.5 cycles after the ckio sampling point. bits ted3 to ted0 must be specified appropriately to satisfy the se tup time of the pc card from iciord and iciowr to cen. figure 7.39 shows the dynamic bus sizing basic timing. note that the iois16 signal is not supported in big endian mode. in the big endian mode, the iois16 signal must be fixed low. tpci1w ckio a25 to a0 cexx rd/ wr iciord d iciowr d bs read write tpci2 tpci1 tpci1w tpci1w figure 7.37 basic timing fo r pcmcia i/o card interface section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 197 of 794 rej09b0237-0500 tpci1w ckio a25 to a0 cexx rd/ wr iciord d iciowr iois16 d bs read write tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait figure 7.38 wait timing fo r pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1) tpci1w ckio a25 to a0 ce1x rd/ wr iciord d iciowr iois16 d bs read write tpci2 ce2x tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait tpci1w tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w figure 7.39 timing for dynamic bus si zing of pcmcia i/ o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software waits = 3) section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 198 of 794 rej09b0237-0500 7.5.8 wait between access cycles data output in the previous cycle may conflict w ith that in the next cycle because the buffer-off timing of devices with slow access speed cannot be operated to satisf y the higher operating frequency of lsis. as a result of these conflic t, the reliability of the device is low and malfunctions may occur. this lsi has a function that avoids data conflicts by inserting wait cycles between consecutive access cycles. the number of wait cycles be tween access cycles can be set by bits iww1 and iww0, bits iwrwd1 and iwrwd0, bits iwrws1 and iwrws0, bits iwrrd1 and iwrrd0, and bits iwrrs1 and iwrrs0 in csnbcr. the conditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. consecutive accesses are write-read or write-write 2. consecutive accesses are read-write for different areas 3. consecutive accesses are read-write for the same area 4. consecutive accesses are re ad-read for different areas 5. consecutive accesses are read-read for the same area 7.5.9 others reset: the bus state controller (bsc) can be initialized completely only by a power-on reset. at power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. all control registers are initialized. in stan dby mode and sleep mode, control registers of the bsc are not initialized. some flash memories may stipul ate a minimum time from reset release to the first access. to ensure this minimum time, the bsc supports a 7-bit counter (rwtcnt). at a power-on reset, the rwtcnt contents are cleared to 0. after a power-on reset, rwtcnt is counted up in synchronization with the ckio signal and an external access will not be generated until rwtcnt is counted up to h'007f. access from the site of th e lsi internal bus master: there are three types of lsi internal buses: a cache bus, internal bus, and peripheral bus. the cpu and cache memory are connected to the cache bus. internal bu s masters other than the cpu and bsc are connected to the internal bus. low-speed peripheral modules are co nnected to the peripheral bus. in ternal memory other than the cache memory and debuggi ng modules such as the ubc are connected to both the cache bus and internal bus. access from the cache bus to the internal bus is enabled but access fr om the internal bus to the cache bus is disabled. this gives rise to the following problems. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 199 of 794 rej09b0237-0500 internal bus masters other th an the cpu such as the dmac and e-dmac can access on-chip memory other than the cache memory but cann ot access the cache memory. if an on-chip bus master other than the cpu writes data to an extern al memory other than th e cache, the contents of the external memory may differ fr om that of the cache memory. to prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the cpu, the corresponding cache memory should be purged by software. if the cpu initiates read access for the cache, the cac he is searched. if th e cache stores data, the cpu latches the data and completes the read access. if the cache does not store data, the cpu performs four consecutive longword read cycles to perform cach e fill operations via the internal bus. if a cache miss occurs in byte or word operan d access or at a branch to an odd word boundary (4n + 2), the cpu performs four consecutive longword accesses to perform a cache fill operation on the external interface. for a cache-through area, the cpu performs access according to the actual access addresses. for an instruction fetch to an even word boundary (4n), the cpu performs longword access. for an instruc tion fetch to an odd word bound ary (4n + 2), the cpu performs word access. for a read cycle of a cache-through area or an on-c hip peripheral module, the read cycle is first accepted and then read cycle is initiated. the read data is sent to the cpu via the cache bus. in a write cycle for the cache area, the write cy cle operation differs accord ing to the cache write methods. in write-back mode, the cache is first searched. if data is detected at the address corresponding to the cache, the data is then re-wr itten to the cache. in the actual me mory, data will not be re-written until data in the corresponding address is re-wr itten. if data is not detected at the address corresponding to the cache, the cache is updated. in this case, data to be updated is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally updated. following these operations, a write-back cycle for the saved 16-byte data is executed. in write-through mode, the cache is first searched . if data is detected at the address corresponding to the cache, the data is re-writt en to the cache simultaneously with the actual write via the internal bus. if data is not detected at the address corresponding to the cache, the cache is not updated but an actual write is performed via the internal bus. since the bsc incorporates a 1-st age write buffer, the bsc can ex ecute an access via the internal bus before the previous external bus cycle is completed in a write cycle. if the on-chip module is read or written after the external low-speed memory is written, the on-chip module can be accessed before the completion of the exte rnal low-speed memo ry write cycle. section 7 bus state controller (bsc) rev. 5.00 mar. 15, 2007 page 200 of 794 rej09b0237-0500 in read cycles, the cpu is placed in the wait cycle until read operation has been completed. to continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. the write buffer of the bsc func tions in the same way for an acces s by a bus master other than the cpu such as the dmac or e-dmac. accordingly, to perfor m dual address dma transfers, the next read cycle is initiated before the previous write cycle is completed. note, however, that if both the dma source and destinati on addresses exist in external memory space, the next write cycle will not be initiated until the previous write cycle is completed. on-chip periphera l module access: to access an on-chip modul e register, two or more peripheral module clock (p ) cycles are required. care must be taken in system design. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 201 of 794 rej09b0237-0500 section 8 clock pulse generator (cpg) this lsi has a clock pulse generator (cpg) that generates an internal clock (i ), a peripheral clock (p ), a bus clock (b ), and a clock (m ) for the on-chip ieee802.3-phy (physical layer device, hereinafter called phy). the cpg consists of an oscillator, pll circuits, and divider circuits. 8.1 features ? four clock modes selection of four clock modes depending on the frequency of a clock source and whether a crystal resonator or external clock input is in use. ? four clocks generated independently an internal clock (i ) for the cpu and cache; a peripheral clock (p ) for the on-chip peripheral modules; a bus clock (b = ckio) for the external bus interface; and a clock (m ) for the on-chip phy. ? frequency change function frequencies of the internal clock, peripheral clock, and clock for the phy can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using the frequency control register (frqcr) and phy clock frequency control register (mclkcr) settings. ? power-down mode control the clock can be stopped in sleep mode and software standby mode and specific modules can be stopped using the module standby function. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 202 of 794 rej09b0237-0500 a block diagram of the cpg is shown in figure 8.1. ckio pll circuit 1 ( 1, 2) pll circuit 2 ( 2, 4) 1 1/2 1/4 1 1/2 1/4 1/5 oscillator unit internal clock (i ) internal bus bus interface [legend] frqcr: frequency control register stbcr: standby control register stbcr2: standby control register 2 stbcr3: standby control register 3 stbcr4: standby control register 4 mclkcr: phy clock frequency control register peripheral clock (p ) bus clock (b = ckio) extal frqcr stbcr stbcr2 stbcr3 stbcr4 cpg control unit phy clock (m ) clock frequency control circuit standby control circuit divider 1 md2 md1 md0 xtal crystal oscillator divider 2 mclkcr figure 8.1 block diagram of cpg section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 203 of 794 rej09b0237-0500 the clock pulse generator blocks function as follows: pll circuit 1: pll circuit 1 leaves the input clock frequency from the pll circuit 2 unchanged or doubles it. the multiplication ratio is set by the frequency control register. the phase of the rising edge of the internal clock is controlled so that it will match the phase of the rising edge of the ckio pin. pll circuit 2: pll circuit 2 doubles or quadruples the clock frequency input from the crystal oscillator or the extal pin. the multiplication ratio is fixed for each clock operating mode. the clock operating mode is set with pins md0, md1, or md2. crystal oscillator: the crystal oscillator is an oscillator circuit when a crystal resonator is connected to the xtal and extal pins. the crysta l oscillator can be used by setting the clock operating mode. divider 1: divider 1 generates clocks with the frequencies used by the internal clock, peripheral clock, and bus clock. the frequency output as the internal clock is always the same as that of the devider1 output. the frequency output as the bus clock is automatically selected so that it is the same as the frequency of the ckio signal according to the multiplication ratio of pll circuit 1. the frequencies can be 1, 1/2, or 1/4 times the ou tput frequency of pll circuit 1, as long as it stays at or above the frequency of the ckio pin. the division ratio is set in the frequency control register. divider 2: divider 2 generates a clock that is supplied to the on-chip phy. divider 2 must output 25-mhz frequency for the on-chip phy that requires 25-mhz clock. the output clock of divider 2 can be 1, 1/2, 1/4, or 1/5 times the output frequency of pll circuit 1. the division ratio is set in the phy clock frequency control register. clock frequency control circuit: the clock frequency control circuit controls the clock frequency using pins md0, md1, and md2, the frequency control register, and phy clock frequency control register. standby control circuit: the standby control circuit controls the state of the on-chip oscillator circuit and other modules during clock switching and in software standby mode. frequency control register: the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the peripheral clock. standby control register: the standby control register has bits for controlling the power-down modes. for details, see section 10, power-down modes. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 204 of 794 rej09b0237-0500 phy clock frequency control register: the phy clock frequency control register sets the frequency division ratio of the phy clock. 8.2 input/output pins table 8.1 shows the cpg pin configuration. table 8.1 pin configuration pin name abbr. i/o description mode control pins * md0 input set the clock operating mode. md1 input set the clock operating mode. md2 input set the clock operating mode. clock input pins xtal output connects a crystal resonator. extal input connects a crystal resonator or an external clock. clock output pin ckio output outputs an external clock. note: * the values of these mode control pins are sampled only at a power-on reset or in a software standby with the mdchg bit in stb cr to 1. this can prevent the erroneous operation of this lsi. 8.3 clock operating modes table 8.2 shows the relationship between the mode control pins (md2 to md0) combinations and the clock operating modes. table 8.3 shows the usable frequency ranges in the clock operating modes and the frequency range of the input clock. table 8.2 mode control pins and clock operating modes pin values clock i/o clock operating mode md2 md1 md0 source output pll2 pll1 ckio frequency 1 0 0 1 extal ckio on ( 4) on ( 1, 2) (extal) 4 2 0 1 0 crystal resonator ckio on ( 4) on ( 1, 2) (crystal resonator) 4 5 1 0 1 extal ckio on ( 2) on ( 1, 2) (extal) 2 6 1 1 0 crystal resonator ckio on ( 2) on ( 1, 2) (crystal resonator) 2 section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 205 of 794 rej09b0237-0500 mode 1: the frequency of the external clock input from the extal pin is quadrupled by pll circuit 2, and then the clock is supplied to this lsi. since the input clock frequency ranging 10 mhz to 15.625 mhz can be used, the ckio frequency ranges from 40 mhz to 62.5 mhz. mode 2: the frequency of the on-chip crystal oscillator output is quadrupled by pll circuit 2, and then the clock is supplied to this lsi. since the crystal resonator frequency ranging 10 mhz to 15.625 mhz can be used, the ckio frequen cy ranges from 40 mhz to 62.5 mhz. mode 5: the frequency of the external clock from the extal pin is doubled by pll circuit 2, and then the clock is supplied to this lsi. since the input clock frequency ranging 10 mhz to 25 mhz, the ckio frequency ranges from 20 mhz to 50 mhz. mode 6: the frequency of the on-chip crystal oscillator output is doubled by pll circuit 2, and then the clock is supplied to the lsi. since the crystal oscillation frequency ranging 10 mhz to 25 mhz can be used, the ckio frequency ranges from 20 mhz to 50 mhz. table 8.3 possible combination of clock modes and frqcr values mode frqcr register value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) input clock frequency range (p must be equal to or lower than 31.25 mhz) ckio pin frequency range h'1000 on ( 1) on ( 4) 4:4:4 1 or 2 h'1001 on ( 1) on ( 4) 4:4:2 10 mhz to 15.625 mhz 40 mhz to 62.5 mhz h'1003 on ( 1) on ( 4) 4:4:1 h'1101 on ( 2) on ( 4) 8:4:4 h'1103 on ( 2) on ( 4) 8:4:2 5 or 6 h'1000 on ( 1) on ( 2) 2:2:2 h'1001 on ( 1) on ( 2) 2:2:1 20 mhz to 50 mhz h'1003 on ( 1) on ( 2) 2:2:1/2 10 mhz to 25 mhz h'1101 on ( 2) on ( 2) 4:2:2 h'1103 on ( 2) on ( 2) 4:2:1 note: * input clock is assumed to be 1. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 206 of 794 rej09b0237-0500 cautions: 1. the internal clock frequency is the product of the frequency of the ckio pin and the frequency multiplication ratio of pll circuit 1. 2. the peripheral clock frequency is the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 1. do not set the peripheral clock frequency lower than the ckio pin frequency. 3. the phy clock frequency is the product of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1, and the division ratio of divider 2. 4. 1, 1/ 2, or 1/ 4 can be used as the division ratio of divider 1. this is set by the frequency control register. 5. the division ratio of divider 2 is selected from 1, 1/ 2, 1/ 4, or 1/ 5. this is set by the phy clock frequency control register. 6. the output frequency of pll circuit 1 is the product of the frequency of the ckio pin and the multiplication ratio of pll circuit 1. it is set by the frequency control register. 7. the bus clock frequency is always set to be equal to the frequency of the ckio pin. 8. the clock mode, the frqcr register value, and the frequency of the input clock should be decided to satisfy the range of operating frequency specified in section 25, electrical characteristics, with referring to table 8.3. 8.4 register descriptions the cpg has the following registers. for details on the addresses of these registers and the states of these regi sters in each processing state, see section 24, list of registers. ? frequency control register (frqcr) ? phy clock frequency control register (mclkcr) 8.4.1 frequency control register (frqcr) frqcr is a 16-bit readable/writable register that specifies whether a clock is output from the ckio pin in standby mode, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the periph eral clock. only word access can be used on frqcr. frqcr is initialized by a power-on reset due to the external input signal. however, it is not initialized by a power-on reset due to a wdt overflow. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 207 of 794 rej09b0237-0500 bit bit name initial value r/w description 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 ckoen 1 r/w clock output enable specifies whether a clock continues to be output from the ckio pin or the output level of the ckio signal is fixed when leaving software standby mode. the ckio output is fixed low when this bit is set to 0. therefore, the malfunction of external circuits because of an unstable ckio clock when leaving software standby mode can be prevented. 0: output level of the ckio signal is fixed low in software standby mode. 1: clock input to the extal pin is output to the ckio pin during software standby mode in clock mode 1 or 5. however, the output level of the ckio pin is fixed low for two cycles of p when changing from the normal mode to the standby mode. this prevents hazard which occurs when the source of the ckio signal is changed from the pll2 output to the extal signal. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 9 8 stc2 stc1 stc0 0 0 0 r/w r/w r/w pll circuit 1 frequency multiplication ratio 000: 1 001: 2 other values: setting prohibited 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 208 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 1 0 pfc2 pfc1 pfc0 0 1 1 r/w r/w r/w peripheral clock frequency division ratio specify the division ratio of the peripheral clock frequency with respect to the output frequency of pll circuit 1. 000: 1 001: 1/2 011: 1/4 other values: setting prohibited 8.4.2 phy clock frequency control register (mclkcr) mclkcr is an 8-bit readable/writable register. this register must be written to in words. the upper byte of the word data must be h'5a and the lower byte is the write data. bit bit name initial value r/w description 7 6 flscs1 flscs0 0 1 r/w r/w source clock select select the source clock. 00: pll1 output clock 01: pll1 output clock 10: setting prohibited 11: setting prohibited 5 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 fldivs2 fldivs1 fldivs0 0 1 1 r/w r/w r/w divider select set the division ratio of pll1 output. 000: 1 001: 1/2 011: 1/4 100: 1/5 other values: setting prohibited section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 209 of 794 rej09b0237-0500 8.4.3 usage notes ? mclkcr is used only to generate clocks for the on-chip phy. however, dedicated clocks input from the ck_phy pin can be used instead of m , which is set by mclkcr as clocks for the on-chip phy. ? when changing the contents of mclkcr or frqcr, make sure that the on-chip phy is in the reset state. otherwise, a hazard may be temporarily generated on m output. to use m as clocks for the on-chip phy, assert the module reset of the on-chip phy after the contents of mclkcr or frqcr have been changed. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 210 of 794 rej09b0237-0500 8.5 changing frequency the internal clock frequency can be changed by ch anging the multiplication ratio of pll circuit 1. the peripheral clock frequency can be changed either by changing the multiplication ratio of pll circuit 1 or by changing the division ratio of divider 1. all of these are controlled by software through the frequency control register. the methods are described below. 8.5.1 changing multiplication ratio the pll lock time must be preserved when the mu ltiplication ratio of pll circuit 1 is changed. the on-chip wdt counts for preserving the pll lock time. 1. in the initial state, the multiplication ratio of pll circuit 1 is 1. 2. set a value that satisfies the given pll lock time in the wdt and stop the wdt. the following must be set. ? tme bit in wtcsr = 0: wdt stops ? bits cks2 to cks0 in wtcsr: division ratio of wdt count clock ? wtcnt: initial counter value 3. set the desired value in bits stc2 to stc0 while the mdchg bit in stbcr is 0. the division ratio can also be set in bits pfc2 to pfc0. 4. this lsi pauses internally and the wdt star ts incrementing. the in ternal and peripheral clocks both stop and only the wdt is supplied with the clock. the clock will continue to be output on the ckio pin. 5. supply of the specified clock starts at a wdt count overflow, and this lsi starts operating again. the wdt stops after it overflows. notes: 1. when the mdchg bit in stbcr is set to 1, changing the frqcr value has no effect on the operation immediately. for details, see section 8.5.3, changing clock operating mode. 2. the multiplication ratio should be changed after completion of the operation, if the on- chip peripheral module is operating. the internal and peripheral clocks are stopped during the multiplication ratio is changed. the communication er ror may occur by the peripheral module communicating to the external ic, and the time error may occur by the timer unit (except the wdt) . the edge detection of external interrupts (nmi and irq7 to irq0) cannot be performed. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 211 of 794 rej09b0237-0500 8.5.2 changing division ratio the wdt will not count unless the multiplication ratio is changed simultaneously. 1. in the initial state, pfc2 to pfc0 = 011. 2. set the desired values in bits pfc2 to pfc0 while the mdchg bit in stbcr is 0. the values that can be set are limited by the clock mode and the multiplication ratio of pll circuit 1. note that if the wrong value is se t, this lsi will malfunction. 3. the clock is immediately changed to the new division ratio. note: when the mdchg bit in stbcr is set to 1, changing the frqcr value has no effect on the operation immediately. for details, see section 8.5.3, changing clock operating mode. 8.5.3 changing clock operating mode the values of the mode control pins (md2 to md0) that define a clock operating mode are fetched at a power-on reset and software standby while the mdchg bit in stbcr is set to 1 register. even if changing the frqcr with the mdchg bit set to 1, the clock mode cannot immediately be changed to the specified clock mode. this change can be reflected as a multiplication ratio or a division ratio after leaving software standby mode to change operating modes. reducing the pll settling time without changing again the multiplication ratio after the operating mode changing is possible by the use of this. the procedures for the mode change using software standby mode are described below. 1. set bits md2 to md0 to the desired clock operating mode. 2. set both the stby and mdchg bits in stbcr to 1. 3. set the adequate value to the wdt so that the given oscillation settling time can be satisfied. then stop the wdt. 4. set frqcr to the desired mode. set bits stc2 to stc0 to the desired multiplication ratio. at this time, a division ratio can be set in bits pfc2 to pfc0. during the operation before the mode change, the clock cannot be changed to the specified clock. 5. enter software standby mode using the sleep instruction. 6. leave software standby mode using an interrupt. 7. after leaving software standby mode, this lsi starts the operation with the value of frqcr that has been set before the mode change. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 212 of 794 rej09b0237-0500 notes: 1. pins md2 to md0 should be set during the operation before the mode change or during software standby mode before requesting an interrupt. 2. clear the stby bit in stbcr in the exception handling routine for the interrupt in step 6. otherwise, software standby mode is entered again. for details, see section 10.5.2, canceling software standby mode. 3. once bits stc2 to stc0 are changed, the clock is not switched to the specified clock even if only bits pfc2 to pfc0 are changed. when bits stc2 to stc0 are changed after the mdchg bit has been set to 1, the frqcr setting must not be made until the clock mode is changed. section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 213 of 794 rej09b0237-0500 8.6 notes on board design note on using an external crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and feedback resistor r1 as close to the xtal and extal pins as possible. in addition, to minimize induction and thus obtain oscillation at the correct frequency, the capacitors to be attached to the resonator must be grounded to the same ground. do not bring wiring patterns close to these components. signal lines prohibited cl1 cl2 extal xtal this lsi rl the values for cl1, cl2, and the damping resistance ri should be determined after consultation with the crystal resonator manufacturer. note: reference value cl1 = 10 to 33 pf cl2 = 10 to 33 pf rl = 1m ? figure 8.2 note on using a crystal resonator notes on using external clocks: when external clocks are inpu t from the extal pin, leave the xtal pin open. in order to prevent a malfunction due to the reflection nois e caused in a signal line which connected to xtal pin, cut this signal line as short as possible. notes on bypass capacitor: a multilayer ceramic capacitor must be inserted for each pair of vss and vcc as a bypass capacitor. the bypass capacito r must be inserted as close as possible to the power supply pins of the lsi. note that th e capacitance and frequency characteristics of the bypass capacitor must be appropriate fo r the operating frequency of the lsi. ? digital power supply pairs for internal logic a7-b7, e2-e1, e13-e12, h4-h3, k12-k13, m10-n10 ? power supply pairs for input and output a1-b1, a9-b9, b15-b14, h14-h15, k1-k2, r7-p7, p13-p14 ? power supply pairs for pll n15-n14, r15-p15 ? analog power supply pairs for phy n4-(n3, ap3), p4-p5 ? no ground available that can be paired with r5 (vcc3a) section 8 clock pulse generator (cpg) rev. 5.00 mar. 15, 2007 page 214 of 794 rej09b0237-0500 notes on using a pll oscillator circuit: in the vcc and vss connection pattern for the pll, signal lines from the board power supply pins must be as short as possible and pattern width must be as wide as possible to reduce inductive interference. since the analog power supply pins of the pll are sensitive to the noise, the system may malfunction due to inductive interference at the other power supply pins. to prevent such malfunction, the analog power supply pin vcc and digital power supply pin vccq should not supply the same resources on th e board if at all possible. vcc(pll2) vss(pll2) vcc(pll1) vss(pll1) vcc vss power supply signal lines prohibited figure 8.3 note on using a pll oscillator circuit section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 215 of 794 rej09b0237-0500 section 9 watchdog timer (wdt) this lsi includes the watchdog timer (wdt) that can reset this lsi by the overflow of the counter when the value of the counter has not been updated because of a system runaway. the wdt is a single-channel timer that uses a peri pheral clock as an input and counts the clock settling time when leaving software standby mode and temporary standby state, such as frequency changes. it can also be used as an interval timer. 9.1 features the wdt has the following features: ? can be used to ensure the clock settling time. the wdt can be used when leaving software standby mode and the temporary standby state which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? internal resets in watchdog timer mode internal resets are generated when the counter overflows. ? interrupts are generated in interval timer mode interval timer interrupts are generated when the counter overflows. ? choice of eight counter input clocks eight clocks ( 1 to 1/4096) that are obtained by dividing the peripheral clock can be chosen. section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 216 of 794 rej09b0237-0500 figures 9.1 is a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock standby mode peripheral clock (p ) standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request wtcsr: wtcnt: [legend] watchdog timer control/status register watchdog timer counter figure 9.1 block diagram of wdt section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 217 of 794 rej09b0237-0500 9.2 register descriptions the wdt has the following two registers. for deta ils on the addresses of these registers and the states of these registers in each processing state, see sect ion 24, list of registers. ? watchdog timer counter (wtcnt) ? watchdog timer control/status register (wtcsr) 9.2.1 watchdog timer counter (wtcnt) wtcnt is an 8-bit readable/writable register that increments on the selected clock. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. wtcnt is not initialized by an internal power-on reset due to the wdt overflow. wtcnt is initialized to h'00 by a power-on reset input to the pin and an h-udi reset. use a word access to write to wt cnt, with h'5a in the upper byte. use a byte access to read wtcnt. note: the writing method for wtcnt differs from other registers so that the wtcnt value cannot be changed accidentally. for details, s ee section 9.2.3, notes on register access. 9.2.2 watchdog timer control/status register (wtcsr) wtcsr is an 8-bit readable/writable register composed of bits to select the clock used for the counting, bits to select the timer mode and overflow flags, and enable bits. wtcsr holds its value in the internal reset state due to the wdt overflow. wtcsr is initialized to h'00 by a power-on reset input to the pin and an h-udi reset. to use it for counting the clock settling time when leaving software standby mode, wtcsr holds its value after a counter overflow. use a word access to write to wt csr, with h'a5 in the upper byte. use a byte access to read wtcsr. note: the writing method for wtcnt differs from other registers so that the wtcnt value cannot be changed accidentally. for details, s ee section 9.2.3, notes on register access. section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 218 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 tme 0 r/w timer enable starts and stops timer operation. clear this bit to 0 when using the wdt in software standby mode or when changing the clock frequency. 0: timer disabled: count-up stops and wtcnt value is retained 1: timer enabled 6 wt/it 0 r/w timer mode select selects whether to use the wdt as a watchdog timer or an interval timer. 0: interval timer mode 1: watchdog timer mode note: if wt/it is modified when the wdt is operating, the up-count may not be performed correctly. 5 ? 0 r reserved this bit is always red as 0. the write value should always be 0. 4 wovf 0 r/w watchdog timer overflow indicates that wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. 0: no overflow 1: wtcnt has overflowed in watchdog timer mode 3 iovf 0 r/w interval timer overflow indicates that wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. 0: no overflow 1: wtcnt has overflowed in interval timer mode section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 219 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock (p ). the overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (p ) is 25 mhz. 000: p (10 s) 001: p /4 (41 s) 010: p /16 (164 s) 011: p /32 (328 s) 100: p /64 (655 s) 101: p /256 (2.62 ms) 110: p /1024 (10.49 ms) 111: p /4096 (41.94 ms) note: if bits cks2 to cks0 are modified when the wdt is operating, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not operating. 9.2.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers is given below. writing to wtcnt and wtcsr: these registers must be written by a word transfer instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 9.2. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 220 of 794 rej09b0237-0500 15 8 7 0 h'5a write data address: h'f815ff84 wtcnt write 15 8 7 0 h'a5 write data address: h'f815ff86 wtcsr write figure 9.2 writing to wtcnt and wtcsr 9.3 wdt operation 9.3.1 canceling software standbys the wdt can be used to cancel software standby mode with an nmi interrupt or external interrupt (irq). the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the res pin low until the clock stabilizes.) 1. before transition to software standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interv al timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in wtcnt. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to software standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecting the change of input levels of the nmi or irq pin. 5. when the wdt count overflows, the cpg st arts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. since the wdt continues counting from h'00, set the stby bit in stbcr to 0 in the interrupt processing program and this will stop the wdt to count. when the stby bit remains 1, the lsi again enters software standby mode when the wdt has counted up to h'80. this software standby mode can be cancel ed by a power-on reset. section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 221 of 794 rej09b0237-0500 9.3.2 changing frequency to change the multiplication ratio of pll circuit 1, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequenc y, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer inte rrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in wtcnt. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when bits stc2 to stc0 in the frequency c ontrol register (frqcr) is written, the processor stops temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg re sumes supplying the cl ock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. wtcnt stops at the value of h'00. 6. before changing wtcnt after the execution of the frequency change instruction, always confirm that the valu e of wtcnt is h'00 by reading wtcnt. 9.3.3 using watchdog timer mode 1. set the wt/it bit in wtcsr to 1, set the type of count clock in bits cks2 to cks0, and set the initial value of the counter in wtcnt. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets the wovf flag in wtcsr to 1 and generates a power-on reset. wtcnt then resumes counting. section 9 watchdog timer (wdt) rev. 5.00 mar. 15, 2007 page 222 of 794 rej09b0237-0500 9.3.4 using interval timer mode when operating in interval timer mode, interval ti mer interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/it bit in wtcsr to 0, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in wtcnt. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the wtcnt overflows, the wdt sets the iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to the intc. the wtcnt then resumes counting. 9.4 usage notes pay attention to the following points when using the wdt. while using the wdt in interval mode, no overflow occurs by the h'00 immediately after writing h'ff to wdtcnt. (iovf in wtcsr is not set.) the overflow occurs at th e point when the count reach es h'00 after one cycle. this phenomenon does not occur when the wdt is used in watchdog timer mode. section 10 power-down modes rev. 5.00 mar. 15, 2007 page 223 of 794 rej09b0237-0500 section 10 power-down modes this lsi supports the following power-down modes: sleep mode, software standby mode, module standby mode. 10.1 features ? supports sleep mode, software standby mode, and module standby 10.1.1 types of power-down modes this lsi has the following power-down modes. ? sleep mode ? software standby mode ? module standby mode (cache, u-memory, ubc, h-ud i, and on-chip peri pheral modules) table 10.1 shows the methods to make a transition from the program execution state, as well as the cpu and peripheral module states in each mode and the procedures for canceling each mode. table 10.1 states of power-down modes state mode transition method cpg cpu cpu register on-chip memory on-chip peripheral modules pins canceling procedure sleep execute sleep instruction with stby bit in stbcr cleared to 0. runs halts held halts (contents remained) run held ? interrupt other than user break ? reset software standby execute sleep instruction with stby bit in stbcr set to 1. halts halts held halts (contents remained) halt held ? nmi, irq ? reset module standby set mstp bits in stbcr2 to stbcr4 to 1. runs runs held specified module halts (contents remained) specified module halts held ? clear mstp bit to 0 ? power-on reset section 10 power-down modes rev. 5.00 mar. 15, 2007 page 224 of 794 rej09b0237-0500 10.2 input/output pins table 10.2 lists the pins used for the power-down modes. table 10.2 pin configuration pin name abbr. i/o description reset input pin res input reset input signal. reset by low level. 10.3 register descriptions there are following registers used for the power-down modes. for details on the addresses of these registers and the states of these registers in each processing state, see section 24, list of registers. ? standby control register (stbcr) ? standby control register 2 (stbcr2) ? standby control register 3 (stbcr3) ? standby control register 4 (stbcr4) section 10 power-down modes rev. 5.00 mar. 15, 2007 page 225 of 794 rej09b0237-0500 10.3.1 standby control register (stbcr) stbcr is an 8-bit readable/writable register that specifies the state of the power-down mode. bit bit name initial value r/w description 7 stby 0 r/w standby specifies transition to software standby mode. 0: executing sleep instruction makes this lsi sleep mode 1: executing sleep instruction makes this lsi software standby mode 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 mdchg 0 r/w md2 to md0 pin control specifies whether or not the values of pins md2 to md0 are reflected in software standby mode. the values of pins md2 to md0 are reflected at returning from software standby mode by an interrupt when the mdchg bit has been set to 1. 0: the values of pins md 2 to mo0 are not reflected in software standby mode. 1: the values of pins md2 to md0 are reflected in software standby mode. 2 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 10 power-down modes rev. 5.00 mar. 15, 2007 page 226 of 794 rej09b0237-0500 10.3.2 standby control register 2 (stbcr2) stbcr2 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 mstp10 0 r/w module stop bit 10 when this bit is set to 1, the supply of the clock to the h-udi is halted. 0: h-udi operates 1: clock supply to h-udi halted 6 mstp9 0 r/w module stop bit 9 when this bit is set to 1, the supply of the clock to the ubc is halted. 0: ubc operates 1: clock supply to ubc halted 5 mstp8 0 r/w module stop bit 8 when this bit is set to 1, the supply of the clock to the dmac is halted. 0: dmac operates 1: clock supply to dmac halted 4, 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 mstp5 0 r/w module stop bit 5 when this bit is set to 1, the supply of the clock to the cache memory is halted. 0: cache memory operates 1: clock supply to cache memory halted 1 mstp4 0 r/w module stop bit 4 when this bit is set to 1, the supply of the clock to the u memory is halted. 0: u memory operates 1: clock supply to the u memory halted section 10 power-down modes rev. 5.00 mar. 15, 2007 page 227 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10.3.3 standby control register 3 (stbcr3) stbcr3 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 mstp15 0 r/w module stop bit 15 when this bit is set to 1, the supply of the clock to the cmt is halted. 0: cmt operates 1: clock supply to cmt halted 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 mstp13 0 r/w module stop bit 13 when this bit is set to 1, the supply of the clock to the scif2 is halted. 0: scif2 operates 1: clock supply to scif2 halted 1 mstp12 0 r/w module stop bit 12 when this bit is set to 1, the supply of the clock to the scif1 is halted. 0: scif1 operates 1: clock supply to scif1 halted section 10 power-down modes rev. 5.00 mar. 15, 2007 page 228 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 mstp11 0 r/w module stop bit 11 when this bit is set to 1, the supply of the clock to the scif0 is halted. 0: scif0 operates 1: clock supply to scif0 halted 10.3.4 standby control register 4 (stbcr4) stbcr4 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 mstp23 0 r/w module stop bit 23 when this bit is set to 1, the supply of the clock to the hif is halted. 0: hif operates 1: clock supply to hif halted 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 mstp21 0 r/w module stop bit 21 when this bit is set to 1, the supply of the clock to the siof is halted. 0: siof operates 1: clock supply to siof halted 1 mstp20 0 r/w module stop bit 20 when this bit is set to 1, the supply of the clock to the phy is halted. 0: phy-if operates 1: clock supply to phy-if halted section 10 power-down modes rev. 5.00 mar. 15, 2007 page 229 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 mstp19 0 r/w module stop bit 19 when this bit is set to 1, the supply of the clock to the etherc and e-dmac is halted. 0: etherc and e-dmac operate 1: clock supply to etherc and e-dmac halted 10.4 sleep mode 10.4.1 transition to sleep mode executing the sleep instruction wh en the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediately after executing the sleep instruction, the contents of its internal registers remain unchanged. the on-chip peripheral modules continue to operate in sleep mode and the clock continues to be output to the ckio pin. 10.4.2 canceling sleep mode sleep mode is canceled by an in terrupt other than a user break (nmi, h-udi, irq, and on-chip peripheral module) or a reset. canceling with interrupt: when a user-break, nmi, h-udi, irq, or on-chip peripheral module interrupt occurs, sleep mode is canceled and inte rrupt exception handling is executed. when the priority level of an irq or on-chip peripheral module interrupt is lower than the interrupt mask level set in the status register (sr) of the cp u, an interrupt request is not accepted preventing sleep mode from being canceled. canceling with reset: s leep mode is canceled by a power-on reset or an h-udi reset. section 10 power-down modes rev. 5.00 mar. 15, 2007 page 230 of 794 rej09b0237-0500 10.5 software standby mode 10.5.1 transition to software standby mode this lsi switches from a prog ram execution state to software standby mode by executing the sleep instruction when the stby bit in stbcr is 1. in softwa re standby mode, not only the cpu but also the clock and on-chip peripheral modules halt. the clock output from the ckio pin also halts. the contents of the cpu and cache registers remain unchanged. some registers of on-chip peripheral modules are, however, initialized. table 10.3 lists the states of on-chip peripheral modules registers in software standby mode. table 10.3 register states in software standby mode module registers initialized registers retaining data interrupt controller (intc) ? all registers clock pulse generator (cpg) ? all registers user break controller (ubc) ? all registers bus state controller (bsc) ? all registers direct memory access controller (dmac) ? all registers ethernet controller (etherc) ? all registers direct memory access controller for ethernet controller (e-dmac) ? all registers i/o port ? all registers user debugging interface (h-udi) ? all registers serial communication interface with fifo (scif0 to scif2) ? all registers compare match timer (cmt0 and cmt1) all registers ? host interface (hif) ? all registers serial io with fifo (siof) ? all registers ethernet physical layer transceiver (phy) some registers * some registers * note: * for details, see section 22, ethernet physical layer transceiver (phy). section 10 power-down modes rev. 5.00 mar. 15, 2007 page 231 of 794 rej09b0237-0500 the procedure for switching to software standby mode is as follows: 1. clear the tme bit in the timer control register (wtcsr) of the wdt to 0 to stop the wdt. 2. set the timer counter (wtcnt) of the wdt to 0 and bits cks2 to cks0 in wtcsr to appropriate values to secure the specified oscillation settling time. 3. after setting the stby bit in stbcr to 1, execute the sleep instruction. 4. software standby mode is entered and the clocks within this lsi are halted. 10.5.2 canceling so ftware standby mode software standby mode is canceled by interrupts (nmi, irq) or a reset. canceling with interrupt: the wdt can be used for hot starts. when an nmi or irq interrupt is detected, the clock will be supplied to the entire lsi and software standby mode will be canceled after the time set in the timer control/status regi ster of the wdt has elap sed. interrupt exception handling is then executed. after the branch to the interrupt handling routine, clear the stby bit in stbcr. wtcnt stops automatically. if the st by bit is not cleared, wtcnt continues operation and a transition is made to software st andby mode* when it reaches h'80. this function prevents data destruction due to the voltage rise by an unstable power supply voltage. irq cancels the software standb y mode when the input condition matches the specified detect condition while the irqn1s and irqn0s bits in irqcr are not b'00 (settings other than the low level detection). when the priority level of an irq interrupt is lower than the interrupt mask level set in the status register (sr) of the cpu, the execution of the instruction following the sleep instruction starts again after the cancellation of software standby mode. when the priority level of an irq interrupt is higher than the interrupt mask level set in the status register (sr) of the cpu, irq interrupt exception handling is executed after the cancellation of software standby mode. note: * this software standby mode can be canceled only by a power-on reset. section 10 power-down modes rev. 5.00 mar. 15, 2007 page 232 of 794 rej09b0237-0500 wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear bit stbcr.stby before wtcnt reaches h'80. when stbcr.stby is cleared, wtcnt halts automatically. figure 10.1 canceling standby mode with stby bit in stbcr canceling with reset: software standby mode is canceled by a power-on reset. keep the res pin low until the clock oscillation settles. the internal clock will continue to be output to the ckio pin. 10.6 module standby mode 10.6.1 transition to module standby mode setting the mstp bits in the standby control registers (stbcr2 to stbcr4) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. this function can be used to reduce the power consumption in normal mode. in module standby mode, the states of the external pins of the on-chip peripheral modules change depending on the on-chip peripheral module and port settings. almost all of the registers retain its previous state. 10.6.2 canceling modul e standby function the module standby function can be canceled by clearing the mstp bits in stbcr2 to stbcr4 to 0, or by a power-on reset. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 233 of 794 rej09b0237-0500 section 11 ethernet controller (etherc) this lsi has an on-chip ethernet controller (etherc) conforming to the ethernet or the ieee802.3 mac (media access control) layer standard. connecting a physical-l ayer lsi (phy-lsi) complying with this standard enables the ethernet controller (etherc) to perform transmission and reception of ethernet/ieee802.3 frames. this lsi has one mac layer interface. the ethernet controller is connect ed to the direct memory access co ntroller for ethernet controller (e-dmac) inside this lsi, and carries out high-speed data transfer to and from the memory. figure 11.1 shows a configuration of the etherc. 11.1 features ? transmission and reception of ethernet/ieee802.3 frames ? supports 10/100 m bps receive/transfer ? supports full-duplex and half-duplex modes ? conforms to ieee 802.3u standard mii (media independent interface) ? magic packet detection and wake-on-lan (wol) signal output ? conforms to ieee802.3x flow control section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 234 of 794 rej09b0237-0500 mac etherc phy e-dmac e-dmac interface receive controller transmit controller command status interface mii figure 11.1 config uration of etherc section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 235 of 794 rej09b0237-0500 11.2 input/output pins table 11.1 lists the pin configuration of the etherc. table 11.1 pin configuration port abbreviation i/o function 0 tx-clk * input transmit clock timing reference signal for the tx-en, mii_txd3 to mii_txd0, tx-er signals 0 rx-clk * input receive clock timing reference signal for the rx-dv, mii_rxd3 to mii_rxd0, rx-er signals 0 tx-en * output transmit enable indicates that transmit data is ready on pins mii_txd3 to mii_txd0. 0 mii_txd3 to mii_txd0 * output transmit data 4-bit transmit data 0 tx-er * output transmit error notifies the phy-lsi of error during transmission 0 rx-dv * input receive data valid indicates that valid receive data is on pins mii_rxd3 to mii_rxd0. 0 mii_rxd3 to mii_rxd0 * input receive data 4-bit receive data 0 rx-er * input receive error identifies error state occu rred during data reception. 0 crs input carrier detection carrier detection signal 0 col input collision detection collision detection signal 0 mdc output management data clock reference clock signal for information transfer via mdio 0 mdio input/ output management data i/o bidirectional signal for exchange of management information between this lsi and phy section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 236 of 794 rej09b0237-0500 port abbreviation i/o function 0 lnksta input link status inputs link status from phy 0 exout output general-p urpose external output signal indicating value of register-bit (ecmr0-elb) 0 wol output wake-on-lan signal indicating reception of magic packet note: * mii signal conforming to ieee802.3u section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 237 of 794 rej09b0237-0500 11.3 register description the etherc has the following registers. for details on addresses and access sizes of registers, see section 24, list of registers. mac layer interface control registers: ? etherc mode register (ecmr) ? etherc status register (ecsr) ? etherc interrupt permission register (ecsipr) ? phy interface register (pir) ? mac address high register (mahr) ? mac address low register (malr) ? receive frame length register (rflr) ? phy status register (psr) ? transmit retry over counter register (trocr) ? delayed collision detect counter register (cdcr) ? lost carrier counter register (lccr) ? carrier not detect coun ter register (cndcr) ? crc error frame counter register (cefcr) ? frame receive error counter register (frecr) ? too-short frame receive counter register (tsfrcr) ? too-long frame receive counter register (tlfrcr) ? residual-bit frame counter register (rfcr) ? multicast address frame counter register (mafcr) ? ipg register (ipgr) ? automatic pause frame set register (apr) ? manual pause frame set register (mpr) ? pause frame retransfer count set register (tpauser) section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 238 of 794 rej09b0237-0500 11.3.1 etherc mode register (ecmr) ecmr is a 32-bit readable/writable register an d specifies the operating mode of the ethernet controller. the settings in this register are norma lly made in the initialization process following a reset. the operating mode setting must not be changed while the transmitting an d receiving functions are enabled. to switch the opera ting mode, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 20 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 19 zpf 0 r/w 0 time parameter pause frame use enable 0: disables pause frame control in which the time parameter is 0. the next frame is transmitted after the time indicated by the timer value has elapsed. when the etherc receives a pause frame with the time indicated by the timer value set to 0, the pause frame is discarded. 1: enables pause frame control in which the time parameter is 0. a pause frame with the timer value set to 0 is transmitted when the number of data in the receive fifo is less than the fcftr value before the time indicated by the timer value has not elapsed. when the etherc receives a pause frame with the time indicated by the timer value set to 0, the transmit wait state is canceled. 18 pfr 0 r/w pause frame receive mode 0: pause frame is not transferred to the e-dmac 1: pause frame is transferred to the e-dmac 17 rxf 0 r/w receive flow control operating mode 0: pause frame detection function is disabled 1: receive flow control function is enabled section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 239 of 794 rej09b0237-0500 bit bit name initial value r/w description 16 txf 0 r/w transmit flow control operating mode 0: transmit flow control function is disabled 1: transmit flow control function is enabled 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 prcef 0 r/w permit receive crc error frame 0: a frame with a crc error is received as a frame with an error. 1: a frame with a crc error is received as a frame without an error. for a frame with an error, a crc error is reflected in the ecsr of the e-dmac and the status of the receive descriptor. for a frame without an error, the frame is received as normal frame. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 mpde 0 r/w magic packet detection enable enables or disables magic packet detection by hardware to allow activation from the ethernet. 0: magic packet detection is not enabled 1: magic packet detection is enabled 8, 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 re 0 r/w reception enable if a frame is being received when this bit is switched from receive function enabled (re = 1) to disabled (re = 0), the receive function will be enabled until reception of the corresponding frame is completed. 0: receive function is disabled 1: receive function is enabled section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 240 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 te 0 r/w transmission enable if a frame is being transmitted when this bit is switched from transmit function enabled (te = 1) to disabled (te = 0), the transmit function will be enabled until transmission of the corresponding frame is completed. 0: transmit function is disabled 1: transmit function is enabled 4 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 3 ilb 0 r/w internal loop back mode specifies loopback mode in the etherc. 0: normal data transmission/reception is performed. 1: when dm = 1, data loopback is performed inside the mac in the etherc. 2 elb 0 r/w external loop back mode this bit value is output directly to this lsi?s general- purpose external output pin (exout). this bit is used for loopback mode directives, etc., in the lsi, using the exout pin. in order for lsi loopback to be implemented using this function, the lsi must have a pin corresponding to the exout pin. 0: low-level output from the exout pin 1: high-level output from the exout pin 1 dm 0 r/w duplex mode specifies the etherc transfer method. 0: half-duplex transfer is specified 1: full-duplex transfer is specified section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 241 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 prm 0 r/w promiscuous mode setting this bit enables all ethernet frames to be received. all ethernet frames means all receivable frames, irrespective of differences or enabled/disabled status (destination address, broadcast address, multicast bit, etc.). 0: etherc performs normal operation 1: etherc performs promiscuous mode operation 11.3.2 etherc status register (ecsr) ecsr is a 32-bit readable/writable register and indi cates the status in the etherc. this status can be notified to the cpu by interrupts. when 1 is written to the psrto, lchng, mpd, and icd, the corresponding flags can be clear ed. writing 0 does not affect the flag. for bits that generate interrupt, the interrupt can be enabled or disabled according to the corresponding bit in ecsipr. the interrupts generated due to this status register are indicated in the eci bit in eesr. bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 psrto 0 r/w pause frame retransfer retry over indicates that during the retransfer of pause frames when the flow control is enabled, the number of retries has exceeded the upper limit set in the automatic pause frame retransfer count set register (tpauser). 0: number of pause frame retransfers has not exceeded the upper limit 1: number of pause frame retransfers has exceeded the upper limit 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 242 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 lchng 0 r/w link signal change indicates that the lnksta signal input from the phy has changed from high to low or low to high. to check the current link state, refer to the lmon bit in the phy status register (psr). 0: changes in the lnksta signal are not detected 1: changes in the lnksta signal are detected (high to low or low to high) 1 mpd 0 r/w magic packet detection indicates that a magic packet has been detected on the line. 0: magic packet has not been detected 1: magic packet has been detected 0 icd 0 r/w illegal carrier detection indicates that the phy has detected an illegal carrier on the line. if a change in the signal input from the phy occurs before the software recognition period, the correct information may not be obtained. refer to the timing specification for the phy used. 0: lsi has not detected an illegal carrier on the line 1: lsi has detected an illegal carrier on the line section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 243 of 794 rej09b0237-0500 11.3.3 etherc interrupt perm ission register (ecsipr) ecsipr is a 32-bit readable/writable register th at enables or disables the interrupt sources indicated by ecsr. each bit can disable or enable interrupts corr esponding to the bits in ecsr. bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 psrtoip 0 r/w pause frame retransfer retry over interrupt enable 0: interrupt notification by the psrto bit is disabled 1: interrupt notification by the psrto bit is enabled 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 lchngip 0 r/w link signal changed interrupt enable 0: interrupt notification by the lchng bit is disabled 1: interrupt notification by the lchng bit is enabled 1 mpdip 0 r/w magic packet detection interrupt enable 0: interrupt notification by the mpd bit is disabled 1: interrupt notification by the mpd bit is enabled 0 icdip 0 r/w illegal carrier detection interrupt enable 0: interrupt notification by the icd bit is disabled 1: interrupt notification by the icd bit is enabled section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 244 of 794 rej09b0237-0500 11.3.4 phy interface register (pir) pir is a 32-bit readable/writable register that pr ovides a means of accessing the phy registers via the mii. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 mdi undefined r mii management data-in indicates the level of the mdio pin. 2 mdo 0 r/w mii management data-out outputs the value set to this bit from the mdio pin, when the mmd bit is 1. 1 mmd 0 r/w mii management mode specifies the data read/writ e direction with respect to the mii. 0: read direction is indicated 1: write direction is indicated 0 mdc 0 r/w mii management data clock outputs the value set to this bit from the mdc pin and supplies the mii with the management data clock. for the method of accessing the mii registers, see section 11.4.4, accessing mii registers. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 245 of 794 rej09b0237-0500 11.3.5 mac address high register (mahr) mahr is a 32 -bit readable/writable register that specifies the upper 32 bits of the 48-bit mac address. the settings in this register are normally made in the initialization process after a reset. the mac address setting must not be changed whil e the transmitting and receiving functions are enabled. to switch the mac address setting, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 0 ma47 to ma16 all 0 r/w mac address bits these bits are used to set the upper 32 bits of the mac address. if the mac address is 01-23-45-67-89-ab (hexadecimal), the value set in this register is h'01234567. 11.3.6 mac address low register (malr) malr is a 32-bit readable/writable register that specifies the lower 16 bits of the 48-bit mac address. the settings in this register are normally made in the initialization process after a reset. the mac address setting must not be changed whil e the transmitting and receiving functions are enabled. to switch the mac address setting, return the etherc and e-dmac to their initial states by means of the swr bit in edmr before making settings again. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 ma15 to ma0 all 0 r/w mac address bits 15 to 0 these bits are used to set the lower 16 bits of the mac address. if the mac address is 01-23-45-67-89-ab (hexadecimal), the value set in this register is h'000089ab. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 246 of 794 rej09b0237-0500 11.3.7 receive frame le ngth register (rflr) rflr is a 32-bit readable/writable register and it specifies the maximum frame length (in bytes) that can be received by this lsi. the settings in this register must not be changed while the receiving function is enabled. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 rfl11 to rfl0 all 0 r/w receive frame length 11 to 0 the frame length described here refers to all fields from the destination address up to and including the crc data. frame contents from the destination address up to and including the data are actually transferred to memory. crc data is not included in the transfer. when data that exceeds the specified value is received, the part of the data that exceeds the specified value is discarded. h'000 to h'5ee: 1,518 bytes h'5ef: 1,519 bytes h'5f0: 1,520 bytes : : h'7ff: 2,047 bytes h'800 to h'fff: 2,048 bytes section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 247 of 794 rej09b0237-0500 11.3.8 phy status register (psr) psr is a read-only regist er that can read interf ace signals from the phy. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 lmon 0 r lnksta pin status the link status can be read by connecting the link signal output from the phy to the lnksta pin. for the polarity, refer to the phy specifications to be connected. 11.3.9 transmit retry ov er counter register (trocr) trocr is a 32-bit counter that indi cates the number of frames that were unable to be transmitted in 16 transmission attempts including the retransf er. when 16 transmission attempts have failed, trocr is incremented by 1. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 troc31 to troc0 all 0 r/w transmit retry over count these bits indicate the number of frames that were unable to be transmitted in 16 transmission attempts including the retransfer. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 248 of 794 rej09b0237-0500 11.3.10 delayed collision detect counter register (cdcr) cdcr is a 32-bit counter that indicates the number of delayed collisions on all lines from a start of transmission. when the value in this regist er reaches h'ffffffff, count-up is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cosdc31 to cosdc0 all 0 r/w delayed collision detect count these bits indicate the number of delayed collisions on all lines from a start of transmission. 11.3.11 lost carrier co unter register (lccr) lccr is a 32-bit counter that indicates the numb er of times the carrier was lost during data transmission. when the value in this register reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by writing to this register with any value. bit bit name initial value r/w description 31 to 0 lcc31 to lcc0 all 0 r/w lost carrier count these bits indicate the number of times the carrier was lost during data transmission. 11.3.12 carrier not detect counter register (cndcr) cndcr is a 32-bit counter that in dicates the number of times the carrier could not be detected while the preamble was being sent. when the valu e in this register reac hes h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cndc31 to cndc0 all 0 r/w carrier not detect count these bits indicate the number of times the carrier was not detected. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 249 of 794 rej09b0237-0500 11.3.13 crc error frame counter register (cefcr) cefcr is a 32-bit counter that indicates the number of times a frame with a crc error was received. when the value in this register reac hes h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 cefc31 to cefc0 all 0 r/w crc error frame count these bits indicate the count of crc error frames received. 11.3.14 frame receive erro r counter register (frecr) frecr is a 32-bit counter that indicates the number of frames input from the phy for which a receive error was indicated by the rx-er pin. frecr is incremented each time the rx-er pin becomes active. when the value in this regist er reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 frec31 to frec0 all 0 r/w frame receive error count these bits indicate the count of errors during frame reception. 11.3.15 too-short frame recei ve counter register (tsfrcr) tsfrcr is a 32-bit counter that indicates the number of frames of fewer than 64 bytes that have been received. when the value in this regist er reaches h'ffffffff, the count is halted. the counter value is cleared to 0 by a wr ite to this register with any value. bit bit name initial value r/w description 31 to 0 tsfc31 to tsfc0 all 0 r/w too-short frame receive count these bits indicate the count of frames received with a length of less than 64 bytes. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 250 of 794 rej09b0237-0500 11.3.16 too-long frame recei ve counter register (tlfrcr) tlfrcr is a 32-bit counter that in dicates the number of frames received with a length exceeding the value specified by the receive frame length register (rflr). when the value in this register reaches h'ffffffff, the count is halted. tlfrcr is not incremented when a frame containing residual bits is received. in this case, the rece ption of the frame is indi cated in the residual-bit frame counter register (rfcr). the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 tlfc31 to tlfc0 all 0 r/w too-long frame receive count these bits indicate the count of frames received with a length exceeding the value in rflr. 11.3.17 residual-bit frame counter register (rfcr) rfcr is a 32-bit counter that indicates the numb er of frames received containing residual bits (less than an 8-bit unit). when the value in this register reaches h'ffffff ff, the count is halted. the counter value is cleared to 0 by a wr ite to this register with any value. bit bit name initial value r/w description 31 to 0 rfc31 to rfc0 all 0 r/w residual-bit frame count these bits indicate the count of frames received containing residual bits. 11.3.18 multicast address fr ame counter register (mafcr) mafcr is a 32-bit counter that in dicates the number of frames r eceived with a specified multicast address. when the value in this register reaches h'ffffffff, th e count is halted. the counter value is cleared to 0 by a write to this register with any value. bit bit name initial value r/w description 31 to 0 mafc31 to mafc0 all 0 r/w multicast address frame count these bits indicate the count of multicast frames received. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 251 of 794 rej09b0237-0500 11.3.19 ipg register (ipgr) ipgr sets the ipg (inter packet gap). this register must not be changed while the transmitting and receiving functions of the et herc mode register (ecmr) are enabled. (for details, refer to section 11.4.6, operation by ipg setting.) bit bit name initial value r/w description 31 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 to 0 ipg4 to ipg0 h'13 r/w inter packet gap sets the ipg value every 4-bit time. h'00: 20-bit time h'01: 24-bit time : : h'13: 96-bit time (initial value) : : h'1f: 144-bit time 11.3.20 automatic pause frame set register (apr) apr sets the time parameter value of the au tomatic pause frame. when transmitting the automatic pause frame, the value set in this re gister is used as the time parameter of the pause frame. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 ap15 to ap0 all 0 r/w automatic pause sets the time parameter value of the automatic pause frame. at this time, 1 bit means 512-bit time. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 252 of 794 rej09b0237-0500 11.3.21 manual pause frame set register (mpr) mpr sets the time parameter value of the manu al pause frame. when transmitting the manual pause frame, the value set to this register is used as the time parameter of the pause frame. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 mp15 to mp0 all 0 r/w manual pause sets the time parameter value of the manual pause frame. at this time, 1 bit means 512-bit time. read values are undefined. 11.3.22 pause frame retransfer count set register (tpauser) tpauser sets the upper limit of the number of times of the pause frame retransfer. tpauser must not be changed while the transmitting function is enabled. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 tpause15 to tpause0 all 0 r/w upper limit of the number of times of pause frame retransfer h'0000: unlimited number of times of retransfer h'0001: retransfer once : : h'ffff: number of times of retransfer is 65535 section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 253 of 794 rej09b0237-0500 11.4 operation the overview of the ethernet controller (ether c) are shown below. the etherc transmits and receives pause frames conforming to the ethernet/ieee802.3 frames. 11.4.1 transmission the etherc transmitter assembles the transmit data on the frame and outputs to mii when there is a transmit request from the e-dmac. the data tran smitted via the mii is transmitted to the lines by phy-lsi. figure 11.3 shows the stat e transition of the et herc transmitter. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 254 of 794 rej09b0237-0500 fdpx fdpx hdpx hdpx collision collision collision * 2 collision * 2 error error error normal transmission notes: 1. transmission retry processing includes both jam transmission that depends on collision detection and the adjustment of transmission intervals based on the back-off algorithm. 2. transmission is retried only when data of 512 bits or less (including the preamble and sfd) is transmitted. when a collision is detected during the transmission of data greater than 512 bits, only jam is transmitted and transmission based on the back-off algorithm is not retried. error notification transmission halted start of transmission (preamble transmission) carrier detection carrier detection sfd transmission crc transmission data transmission carrier detection failure of 15 retransfer attempts or collision after 512-bit time retransfer processing * 1 error detection retransfer initiation carrier non-detection carrier non-detection idle te set te reset reset [legend] fdpx: full duplex hdpx: half duplex sfd: start frame delimiter figure 11.2 etherc tran smitter state transitions 1. when the transmit enable (te) bit is set, th e transmitter enters the transmit idle state. 2. when a transmit request is issued by the transmit e-dmac, the etherc sends the preamble after a transmission delay equivalent to the frame interval time. if full-duplex transfer is selected, which does not require car rier detection, the preamble is sent as soon as a transmit request is issued by the e-dmac. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 255 of 794 rej09b0237-0500 3. the transmitter sends the sfd, data, and crc sequentially. at the end of transmission, the transmit e-dmac generates a transmission comp lete interrupt (tc). if a collision or the carrier-not-detected state occurs during data transmission, thes e are reported as interrupt sources. 4. after waiting for the frame interval time, the tran smitter enters the idle state, and if there is more transmit data, continues transmitting. 11.4.2 reception the etherc receiver separates the frame data (mii into preamble, sfd, da (destination address), sa (source address), type/length, data, and crc da ta) and outputs da, sa, type/length, data to the e-dmac. figure 11.3 shows the stat e transitions of the etherc receiver. illegal carrier detection start of frame reception wait for sfd reception data reception crc reception destination address reception preamble detection reception halted reset error notification * re set [legend] sfd: start frame delimiter note: * the error frame also transmits data to the buffer. end of reception receive error detection receive error detection error detection promiscuous and other station destination address re reset normal reception idle rx-dv negation sfd reception own destination address or broadcast or multicast or promiscuous figure 11.3 etherc r eceiver state transmissions section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 256 of 794 rej09b0237-0500 1. when the receive enable (re) bit is set, the receiver enters the receive idle state. 2. when an sfd (start frame delimiter) is detect ed after a receive packet preamble, the receiver starts receive processing . discards a frame with an invalid pattern. 3. in normal mode, if the destination address matches the receiver?s own address, or if broadcast or multicast transmission or promiscuou s mode is specified, the receive r starts data reception. 4. following data recep tion from the mii, the receiver carries out a crc check. the result is indicated as a status bit in the descriptor after the frame data has been written to memory. reports an error status in the case of an abnormality. 5. after one frame has been receiv ed, if the receive enable bit is set (re = 1) in the etherc mode register, the receiver prepares to receive the next frame. 11.4.3 mii frame timing each mii frame timing is shown in figure 11.4. tx-clk tx-en txd3 to txd0 tx-er crs col sfd preamble data crc figure 11.4 (1) mii frame transmit timing (normal transmission) tx-clk tx-en tx-er crs col preamble jam mii_txd3 to mii_txd0 figure 11.4 (2) mii frame transmit timing (collision) section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 257 of 794 rej09b0237-0500 tx-clk tx-en mii_txd3 to mii_txd0 tx-er crs col sfd preamble data figure 11.4 (3) mii frame tran smit timing (transmit error) rx-clk rx-dv rx-er preamble data crc sfd mii_rxd3 to mii_rxd0 figure 11.4 (4) mii frame r eceive timing (normal reception) rx-clk rx-dv rx-er preamble data xxxx sfd mii_rxd3 to mii_rxd0 figure 11.4 (5) mii frame recei ve timing (reception error (1)) rx-clk rx-dv rx-er xxxx 1110 xxxx mii_rxd3 to mii_rxd0 figure 11.4 (6) mii fame recei ve timing (reception error (2)) section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 258 of 794 rej09b0237-0500 11.4.4 accessing mii registers mii registers in the phy are accessed via this lsi? s phy interface register (pir). connection is made as a serial interface in accordance with the mii frame format specified in ieee802.3u. mii management frame format: the format of an mii management frame is shown in figure 11.8. to access an mii register , a management frame is impl emented by the program in accordance with the proced ures shown in mii register access procedure. access type mii management frame item number of bits read write pre 32 1..1 1..1 st 2 01 01 op 2 10 01 phyad 5 00001 00001 regad 5 rrrrr rrrrr ta 2 z0 10 data 16 d..d d..d idle x pre: st: op: phyad: regad: ta: data: idle: [legend] 32 consecutive 1s write of 01 indicating start of frame write of code indicating access type write of 0001 if the phy address is 1 (sequential write starting with the msb). this bit changes depending on the phy address. write of 0001 if the register address is 1 (sequential write starting with the msb). this bit changes depending on the phy register address. time for switching data transmission source on mii interface (a) write: 10 written (b) read: bus release (notation: z0) performed 16-bit data. sequential write or read from msb (a) write: 16-bit data write (b) read: 16-bit data read wait time until next mii management format input (a) write: independent bus release (notation: x) performed (b) read: bus already released in ta; control unnecessary figure 11.5 mii management frame format section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 259 of 794 rej09b0237-0500 mii register access procedure: the program accesses mii regi sters via the phy interface register (pir). access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus release. figure 11.9 show s the mii register access timing. the timing will differ depending on the phy type. mdc (1) (1) (2) (3) mdo (2) (3) write to phy interface register 1-bit data write timing relationship mmd = 1 mdo = write data mdc = 0 mmd = 1 mdo = write data mdc = 1 write to phy interface register mmd = 1 mdo = write data mdc = 0 write to phy interface register figure 11.6 (1) 1-bit data write flowchart section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 260 of 794 rej09b0237-0500 mdc (1) (1) (2) (3) write to phy interface register mmd = 0 mdc = 0 bus release timing relationship mdo (2) write to phy interface register mmd = 0 mdc = 1 (3) write to phy interface register mmd = 0 mdc = 0 figure 11.6 (2) bus release flowchart (ta in read in figure 11.5) mdc (1) (1) (2) (3) write to phy interface register mmd = 0 mdc = 1 1-bit data read timing relationship (3) write to phy interface register mmd = 0 mdc = 0 (2) read from phy interface register read mmd = 0 mmc = 1 mdi is read data mdi figure 11.6 (3) 1-bit data read flowchart section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 261 of 794 rej09b0237-0500 mdc (1) (1) write to phy interface register mmd = 0 mdc = 0 independent bus release timing relationship mdo figure 11.6 (4) independent bus release flowchart (idle in write in figure 11.5) 11.4.5 magic packet detection the etherc has a magic packet detection function. this function provides a wake-on-lan (wol) facility that activates various peripheral devices connected to a lan from the host device or other source. this makes it possible to constr uct a system in which a peripheral device receives a magic packet sent from the host device or othe r source, and activates itself. when the magic packet is detected, data is stored in the fifo of the e-dmac by the broadcast packet that has received data previously and the etherc is notifie d of the receiving status . to return to normal operation from the interrupt processing, initialize the etherc and e-dmac by using the swr bit in the e-dmac mode register (edmr). with a magic packet, recep tion is performed regardless of the de stination address. as a result, this function is valid, and the wol pin enabled, only in the case of a match with the destination address specified by the format in the magic packet. further information on magic packets can be found in the technical documentation published by amd corporation. the procedure for using the wol func tion with this lsi is as follows. 1. disable interrupt source output by means of the various interrupt enable/mask registers. 2. set the magic packet detection enable bit (mpde) in the etherc mode register (ecmr). 3. set the magic packet detection interrupt enable bit (mpdip) in the etherc interrupt enable register (ecsipr) to the enable setting. 4. if necessary, set the cpu operating mode to sleep mode or set supporting functions to module standby mode. 5. when a magic packet is detected, an interrupt is sent to the cpu. the wol pin notifies peripheral lsis that the magic packet has been detected. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 262 of 794 rej09b0237-0500 11.4.6 operation by ipg setting the etherc has a function to chan ge the non-transmission period ipg (inter packet gap) between transmit frames. by changing the set values of th e ipg setting register (i pgr), the transmission efficiency can be raised and lowered from the st andard value. ipg settings are prescribed in ieee802.3 standards. when changing settings, ad equately check that th e respective devices can operate smoothly on the same network. ipg * [1] [2] [3] [4] [1] [2] [3] [4] [5] ...... ...... packet note: * ipg may be longer than the set value, depending on the state of the circuit and the system bus. case a (short ipg) case b (long ipg) figure 11.7 changing ipg and transmission efficiency 11.4.7 flow control the etherc supports flow control functions conforming to ieee802.3x in full-duplex operations. flow control can be applied to both receive and transmit operations. the me thods for transmitting pause frames when controlling flow are as follows: automatic pause frame transmission: for receive frames, pause frames are automatically transmitted when the number of da ta in the receive fifo (include d in e-dmac) reaches the value set in the flow control fifo threshold register (fcftr) of the e-dmac. the time parameter included in the pause frame at this time is set by the automatic pause frame setting register (apr). the automatic pause frame transmission is repeated until the nu mber of data in the receive fifo becomes less than the fcftr setting as the receive data is read from the fifo. the upper limit of the number of retransfers of the pause frame can also be set by the automatic pause frame retransfer count set register (tpauser). in this case, pause frame transmission is repeated until the number of data becomes fcftr value set or below, or the number of transmits reaches the value se t by tpauser. the automatic pause frame transmission is enabled when the txf bit in the ethe rc mode register (ecmr) is 1. section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 263 of 794 rej09b0237-0500 manual pause frame transmission: pause frames are transmitted by directives from the software. when writing the timer value to the ma nual pause frame set register (mpr), manual pause frame transmission is started. with this method, pause frame transmission is carried out only once. pause frame reception: the next frame is not transmitted until the time indicated by the timer value elapses after receiving a pause fram e. however, the transmission of the current frame is continued. a received pause frame is va lid only when the rxf bit in the etherc mode register (ecmr) is set to 1. 11.5 connection to phy-lsi figure 11.8 shows the example of connection to a dp83846avhg by national semiconductor corporation. tx-er mii_txd3 mii_txd2 mii_txd1 mii_txd0 tx-en tx-clk mdc mdio mii_rxd3 mii_rxd2 mii_rxd1 mii_rxd0 rx-clk crs col rx-dv rx-er txer txd3 txd2 txd1 txd0 txen txclk mdc mdio rxd3 rxd2 rxd1 rxd0 rxclk crs col rxdv rxer dp83846avhg mii (media independent interface) this lsi figure 11.8 example of connection to dp83846avhg section 11 ethernet controller (etherc) rev. 5.00 mar. 15, 2007 page 264 of 794 rej09b0237-0500 11.6 usage notes ? conditions for setting lchng bit even if the level of the signal input to the lnksta pin is not changed, the lchng bit in ecsr may be set. it may happen when the pin function is changed from port to lnksta by pccrh2 of the pfc or when a software reset caused by the swr bit in edmr is cleared while the lnksta pin is being driven high. this is because the lnksta signal is internally fixed low when the pin functions as a port or during the software reset state regardless of the external pin level. clear the lchng bit before setting the lchngip bit in ecsipr not to request a link signal changed interrupt accidentally. ? flow control defect 1 once a pause frame is received while the receiving flow cont rol is enabled in full-duplex mode (the rxf bit in ecmr = 1), each time when the local station receives a normal unicast frame (non-pause frame without a crc error), the time parameter specified by the pause frame that has been previously received is incorr ectly applied. as a result, unnecessary waiting time is generated to slow down the transmis sion throughput. the time parameter value is maintained until another pause frame is received. this defect can be prevented if the destination station supports the function to transmit the 0 time pause frame as the same as this lsi do es. enable the use of 0 time pause frame in this lsi (the zpf bit in ecmr = 1) before the 0 time pause frame is received from the destination station. this clears the time parame ter incorrectly maintained in the etherc and prevents the unnecessary waiting time for transmission to be generated. ? flow control defect 2 when a pause period is generated while the tran smitting/receiving flow control is enabled in full-duplex mode (the txf/rxf bit in ecmr = 1), non-pause frames are waited for transmission (this is a normal operation) wh ereas pause frames are in correctly waited for transmission. the transmission of non-pause frames in a pause period is prohibited, though the transmission of pause frames is enabled in ieee802.3. when a pause period is generated by the request from the destination station (that is, a pause frame is received from the destination sta tion), the load of the destination station is high and that of the local station is not so hi gh. therefore, the transm ission of pause frames during this period is less likely to happen. the ratio that this defect actually affects the operation in this lsi is rather low. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 265 of 794 rej09b0237-0500 section 12 ethernet controller direct memory access controller (e-dmac) this lsi includes a direct memory access controlle r (e-dmac) directly conn ected to the ethernet controller (etherc). a large proportion of buffer management is controlled by the e-dmac itself using descriptors. this lightens the load on the cp u and enables efficient control of data transfer. figure 12.1 shows the configuration of the e-dmac, and the descriptors and transmit/receive buffers in memory. 12.1 features the e-dmac has the following features: ? the load on the cpu is reduced by means of a descriptor management system ? transmit/receive frame status inform ation is indicated in descriptors ? achieves efficient system bus utilization thro ugh the use of block transfer (16-byte units) ? supports single-frame/multi-buffer operation transmit fifo receive fifo transmit descriptor transmit buffer receive buffer receive descriptor external bus interface internal bus internal bus interface this lsi external memory etherc e-dmac descriptor information transmit dmac receive dmac descriptor information figure 12.1 configuration of e- dmac, and descriptors and buffers section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 266 of 794 rej09b0237-0500 12.2 register descriptions the e-dmac has the following registers. for ad dresses and access sizes of these registers, see section 24, list of registers. ? e-dmac mode register (edmr) ? e-dmac transmit request register (edtrr) ? e-dmac receive request register (edrrr) ? transmit descriptor list address register (tdlar) ? receive descriptor list ad dress register (rdlar) ? etherc/e-dmac status register (eesr) ? etherc/e-dmac status interrupt permission register (eesipr) ? transmit/receive status copy enable register (trscer) ? receive missed-frame coun ter register (rmfcr) ? transmit fifo threshold register (tftr) ? fifo depth register (fdr) ? receiving method cont rol register (rmcr) ? e-dmac operation control register (edocr) ? receive buffer write ad dress register (rbwar) ? receive descriptor fetch address register (rdfar) ? transmit buffer read address register (tbrar) ? transmit descriptor fetch address register (tdfar) ? flow control fifo threshold register (fcftr) ? transmit interrupt register (trimd) section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 267 of 794 rej09b0237-0500 12.2.1 e-dmac mode register (edmr) edmr is a 32-bit readable/writable register that specifies the operatin g mode of the e-dmac. the settings in this register are normally made in the initialization process following a reset. if the etherc and e-dmac are initialized by means of th is register during data transmission, abnormal data may be sent onto the line. operating mode settings must not be cha nged while the transmit and receive functions are enabled. to change the operating mode, the etherc and e-dmac modules are got into at their initial state by means of the software reset bit (swr) in this register, then make new settings. it takes 64 cycles of the internal bus clock b to initialize the etherc and e-dmac. therefore, registers of the etherc and e-dmac should be accessed after 64 cycles of the internal bus clock b has elapsed. bit bit name initial value r/w description 31 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 de 0 r/w e-dmac data endian convert selects whether or not the endian format is converted on data transfer by the e-dmac. however, the endian format of the descriptors and e-dmac register values are not converted regardless of this bit setting. 0: endian format not converted (big endian) 1: endian format converted (little endian) 5 4 dl1 dl0 0 0 r/w r/w descriptor length these bits specify the descriptor length. 00: 16 bytes 01: 32 bytes 10: 64 bytes 11: reserved (setting prohibited) 3 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 268 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 swr 0 r/w software reset writing 1 in this bit initializes registers of the e-dmac other than tdlar, rdlar, and rmfcr and registers of the etherc. while a software reset is being executed (64 cycles of the internal bus clock b ), accesses to the all ethernet-related registers are prohibited. software reset period (example): when b = 62.5 mhz: 1.03 s when b = 33 mhz: 1.94 s this bit is always read as 0. 0: writing 0 is ignored (e-dmac operation is not affected) 1: writing 1 resets the etherc and e-dmac and then automatically cleared 12.2.2 e-dmac transmit request register (edtrr) the edtrr is a 32-bit readable/writable register th at issues transmit directives to the e-dmac. when transmission of one frame is completed, the next descriptor is read. if the transmit descriptor active bit in this descriptor has the "active" setting, transmission is continued. if the transmit descriptor active bit has the "inactive" se tting, the tr bit is cleared and operation of the transmit dmac is halted. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tr 0 r/w transmit request 0: transmission-halted state. writing 0 does not stop transmission. termination of transmission is controlled by the active bit in the transmit descriptor 1: start of transmission. the relevant descriptor is read and a frame is sent with the transmit active bit set to 1 section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 269 of 794 rej09b0237-0500 12.2.3 e-dmac receive request register (edrrr) edrrr is a 32-bit readable/writable register that issues receive directives to the e-dmac. when the receive request bit is set, the e-dmac reads the relevant receive descriptor. if the receive descriptor active bit in the descriptor has the " active" setting, the e-dmac prepares for a receive request from the etherc. when one receive buffer of data has been received, the e-dmac reads the next descriptor and prepares to receive the next frame. if the receive de scriptor active bit in the descriptor has the "inactive" setting, the rr bit is cleared and operation of the receive dmac is halted. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rr 0 r/w receive request 0: the receive function is disabled * 1: a receive descriptor is read and the e-dmac is ready to receive note: * if the receive function is disabled during fr ame reception, write-back is not performed successfully to the receive descriptor. follo wing pointers to read a receive descriptor become abnormal and the e-dmac cannot operate successfully. in this case, to make the e-dmac reception enabled again, execute a software reset by the swr bit in edmr. to make the e-dmac reception disabled without executing a software reset, set the re bit in ecmr. next, after the e_dmac has completed the reception and write-back to the receive descriptor has been confirmed, disable t he receive function of this register. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 270 of 794 rej09b0237-0500 12.2.4 transmit descriptor li st address register (tdlar) tdlar is a 32-bit readable/writable register that specifies the start address of the transmit descriptor list. descriptors have a boundary configuration in accordance with the descriptor length indicated by the dl bit in edmr. this register must not be written to during transmission. modifications to this register should only be made while transmission is disabled by the tr bit ( = 0) in the e-dmac transmit request register (edtrr). bit bit name initial value r/w description 31 to 0 tdla31 to tdla0 all 0 r/w transmit descriptor start address the lower bits are set as follows according to the specified descriptor length. 16-byte boundary: tdla3 to tdla0 = 0000 32-byte boundary: tdla4 to tdla0 = 00000 64-byte boundary: tdla5 to tdla0 = 000000 12.2.5 receive descriptor li st address register (rdlar) rdlar is a 32-bit readab le/writable register that specifies the start address of the receive descriptor list. descriptors have a boundary configuration in accordance with the descriptor length indicated by the dl bit in edmr. this register must not be written to during reception. modifications to this register should only be made while reception is disabled by the rr bit ( = 0) in the e-dmac receive request register (edrrr). bit bit name initial value r/w description 31 to 0 rdla31 to rdla0 all 0 r/w receive descriptor start address the lower bits are set as follows according to the specified descriptor length. 16-byte boundary: rdla3 to rdla0 = 0000 32-byte boundary: rdla4 to rdla0 = 00000 64-byte boundary: rdla5 to rdla0 = 000000 section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 271 of 794 rej09b0237-0500 12.2.6 etherc/e-dmac st atus register (eesr) eesr is a 32-bit readable/writable register that shows communications status information on the e-dmac in combination with the etherc. the informat ion in this register is reported in the form of interrupts. individual bits are cleared by writing 1 (however, bit 22 (eci) is a read-only bit and not to be cleared by writing 1) and are not affected by writing 0. each interrupt source can also be masked by means of the corresponding bit in the etherc/e-dmac status interrupt permission register (eesipr). the interrupts generated by this register are eint0. for interrupt priority, see section 6.5, interrupt exception handling vector table. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 twb 0 r/w write-back complete indicates that write-back from the e-dmac to the corresponding descriptor has completed. this operation is enabled when the tis bit in trimd is set to 1. 0: write-back has not completed, or no transmission directive 1: write-back has completed 29 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 26 tabt 0 r/w transmit abort detection indicates that frame transmission by the etherc has been aborted because of an error during transmission. 0: frame transmission has not been aborted or no transmit directive 1: frame transmit has been aborted section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 272 of 794 rej09b0237-0500 bit bit name initial value r/w description 25 rabt 0 r/w receive abort detection indicates that frame recept ion by the etherc has been aborted because of an error during reception. 0: frame reception has not been aborted or no receive directive 1: frame receive has been aborted 24 rfcof 0 r/w receive frame counter overflow indicates that the receiv e fifo frame counter has overflowed. 0: receive frame counter has not overflowed 1: receive frame counter overflows 23 ade 0 r/w address error indicates that the memory address that the e-dmac tried to transfer is found illegal. 0: illegal memory address not detected (normal operation) 1: illegal memory address detected note: when an address error is detected, the e-dmac halts transmitting/receiving. to resume the operation, set the e-dmac again after software reset by means of the swr bit in edmr. 22 eci 0 r etherc status register interrupt source this bit is a read-only bit. when the source of an ecsr interrupt in the etherc is cleared, this bit is also cleared. 0: etherc status interrupt source has not been detected 1: etherc status interrupt source has been detected section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 273 of 794 rej09b0237-0500 bit bit name initial value r/w description 21 tc 0 r/w frame transmit complete indicates that all the data specified by the transmit descriptor has been transmi tted to the etherc. the transfer status is written back to the relevant descriptor. when 1-frame transmission is completed for 1-frame/1-buffer processing, or when the last data in the frame is transmitted and the transmission descriptor valid bit (tact) in the next descriptor is not set for multiple-frame buffe r processing, transmission is completed and this bit is set to 1. after frame transmission, the e-dmac writes the transmission status back to the descriptor. 0: transfer not complete, or no transfer directive 1: transfer complete 20 tde 0 r/w transmit descriptor empty indicates that the transmission descriptor valid bit (tact) in the descriptor is not set when the e-dmac reads the transmission descriptor when the previous descriptor is not the last one of the frame for multiple- buffer frame processing. as a result, an incomplete frame may be transmitted. 0: transmit descriptor active bit tact = 1 detected 1: transmit descriptor active bit tact = 0 detected when transmission descriptor empty (tde = 1) occurs, execute a software reset and initiate transmission. in this case, the address that is stored in the transmit descriptor list address register (tdlar) is transmitted first. 19 tfuf 0 r/w transmit fifo underflow indicates that underflow has occurred in the transmit fifo during frame transmission. incomplete data is sent onto the line. 0: underflow has not occurred 1: underflow has occurred section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 274 of 794 rej09b0237-0500 bit bit name initial value r/w description 18 fr 0 r/w frame reception indicates that a frame has been received and the receive descriptor has been updated. this bit is set to 1 each time a frame is received. 0: frame not received 1: frame received 17 rde 0 r/w receive descriptor empty when receive descriptor empty (rde = 1) occurs, receiving can be restarted by setting ract = 1 in the receive descriptor and initiating receiving. 0: receive descriptor active bit ract = 1 not detected 1: receive descriptor active bit ract = 0 detected 16 rfof 0 r/w receive fifo overflow indicates that the receive fifo has overflowed during frame reception. 0: overflow has not occurred 1: overflow has occurred 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 cnd 0 r/w carrier not detect indicates the carrier detection status. 0: a carrier is detected when transmission starts 1: a carrier is not detected when transmission starts 10 dlc 0 r/w detect loss of carrier indicates that loss of t he carrier has been detected during frame transmission. 0: loss of carrier not detected 1: loss of carrier detected 9 cd 0 r/w delayed collision detect indicates that a delayed collision has been detected during frame transmission. 0: delayed collision not detected 1: delayed collision detected section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 275 of 794 rej09b0237-0500 bit bit name initial value r/w description 8 tro 0 r/w transmit retry over indicates that a retry-over condition has occurred during frame transmission. total 16 transmission retries including 15 retries based on the back-off algorithm are failed after the etherc transmission starts. 0: transmit retry-over condition not detected 1: transmit retry-over condition detected 7 rmaf 0 r/w receive multicast address frame 0: multicast address frame has not been received 1: multicast address frame has been received 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 rrf 0 r/w receive residual-bit frame 0: residual-bit frame has not been received 1: residual-bit frame has been received 3 rtlf 0 r/w rece ive too-long frame indicates that the frame more than the number of receive frame length upper limit set by rflr of the etherc has been received. 0: too-long frame has not been received 1: too-long frame has been received 2 rtsf 0 r/w receive too-short frame indicates that a frame of fewer than 64 bytes has been received. 0: too-short frame has not been received 1: too-short frame has been received 1 pre 0 r/w phy receive error 0: phy receive error not detected 1: phy receive error detected 0 cerf 0 r/w crc error on received frame 0: crc error not detected 1: crc error detected section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 276 of 794 rej09b0237-0500 12.2.7 etherc/e-dmac st atus interrupt permissi on register (eesipr) eesipr is a 32-bit readable/writable register that enables interrupts corresponding to individual bits in the etherc/e-dmac status register (eesr) . an interrupt is enabled by writing 1 to the corresponding bit. in the initial st ate, interrupts are not enabled. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 twbip 0 r/w write-back complete interrupt permission 0: write-back complete interrupt is disabled 1: write-back complete interrupt is enabled 29 to 27 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 26 tabtip 0 r/w transmit abort detection interrupt permission 0: transmit abort detection interrupt is disabled 1: transmit abort detection interrupt is enabled 25 rabtip 0 r/w receive abort detection interrupt permission 0: receive abort detection interrupt is disabled 1: receive abort detection interrupt is enabled 24 rfcofip 0 r/w receive frame count er overflow interrupt permission 0: receive frame counter overflow interrupt is disabled 1: receive frame counter overflow interrupt is enabled 23 adeip 0 r/w address error interrupt permission 0: address error interrupt is disabled 1: address error interrupt is enabled 22 eciip 0 r/w etherc status register interrupt permission 0: etherc status interrupt is disabled 1: etherc status interrupt is enabled 21 tcip 0 r/w frame transmit complete interrupt permission 0: frame transmit complete interrupt is disabled 1: frame transmit complete interrupt is enabled section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 277 of 794 rej09b0237-0500 bit bit name initial value r/w description 20 tdeip 0 r/w transmit descriptor empty interrupt permission 0: transmit descriptor empty interrupt is disabled 1: transmit descriptor empty interrupt is enabled 19 tfufip 0 r/w transmit fifo underflow interrupt permission 0: underflow interrupt is disabled 1: underflow interrupt is enabled 18 frip 0 r/w frame received interrupt permission 0: frame received interrupt is disabled 1: frame received interrupt is enabled 17 rdeip 0 r/w receive descriptor empty interrupt permission 0: receive descriptor empty interrupt is disabled 1: receive descriptor empty interrupt is enabled 16 rfofip 0 r/w receive fifo overflow interrupt permission 0: receive fifo overflow interrupt is disabled 1: receive fifo overflow interrupt is enabled 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 cndip 0 r/w carrier not detect interrupt permission 0: carrier not detect interrupt is disabled 1: carrier not detect interrupt is enabled 10 dlcip 0 r/w detect loss of carrier interrupt permission 0: detect loss of carrier interrupt is disabled 1: detect loss of carrier interrupt is enabled 9 cdip 0 r/w delayed collision detect interrupt permission 0: delayed collision detect interrupt is disabled 1: delayed collision detect interrupt is enabled 8 troip 0 r/w transmit retry over interrupt permission 0: transmit retry over interrupt is disabled 1: transmit retry over interrupt is enabled section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 278 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 rmafip 0 r/w receive multicast address frame interrupt permission 0: receive multicast address frame interrupt is disabled 1: receive multicast address frame interrupt is enabled 6, 5 ? all 0 r reserved this bit is always read as 0. the write value should always be 0. 4 rrfip 0 r/w receive residual-bit frame interrupt permission 0: receive residual-bit frame interrupt is disabled 1: receive residual-bit frame interrupt is enabled 3 rtlfip 0 r/w receive too-l ong frame interrupt permission 0: receive too-long frame interrupt is disabled 1: receive too-long frame interrupt is enabled 2 rtsfip 0 r/w receive too-s hort frame interrupt permission 0: receive too-short frame interrupt is disabled 1: receive too-short frame interrupt is enabled 1 preip 0 r/w phy-lsi receive error interrupt permission 0: phy-lsi receive error interrupt is disabled 1: phy-lsi receive error interrupt is enabled 0 cerfip 0 r/w crc error on received frame 0: crc error on received frame interrupt is disabled 1: crc error on received frame interrupt is enabled section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 279 of 794 rej09b0237-0500 12.2.8 transmit/receive status copy enable register (trscer) trscer specifies whether or not transmit and receive status information reported by bits in the etherc/e-dmac status register is to be indicated in bits tfs26 to tfs0 and rfs26 to rfs0 in the corresponding descriptor. bits in this register correspond to bits 11 to 0 in the etherc/e- dmac status register (eesr). when a bit is clear ed to 0, the transmit st atus (bits 11 to 8 in eesr) is indicated in bits tfs3 to tfs0 in the transmit descriptor , and the receive status (bits 7 to 0 in eesr) is indicated in bits rfs7 to rfs0 of the receive desc riptor. when a bit is set to 1, the occurrence of the corresponding interrupt is no t indicated in the descriptor. after this lsi is reset, all bits are cleared to 0. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 cndce 0 r/w cnd bit copy directive 0: indicates the cnd bit state in bit tfs3 in the transmit descriptor 1: occurrence of the corresponding interrupt is not indicated in bit tfs3 of the transmit descriptor 10 dlcce 0 r/w dlc bit copy directive 0: indicates the dlc bit state in bit tfs2 of the transmit descriptor 1: occurrence of the corresponding interrupt is not indicated in bit tfs2 of the transmit descriptor 9 cdce 0 r/w cd bit copy directive 0: indicates the cd bit state in bit tfs1 of the transmit descriptor 1: occurrence of the corresponding interrupt is not indicated in bit tfs1 of the transmit descriptor 8 troce 0 r/w tro bit copy directive 0: indicates the tro bit state in bit tfs0 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit tfs0 of the receive descriptor section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 280 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 rmafce 0 r/w rmaf bit copy directive 0: indicates the rmaf bit state in bit rfs7 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs7 of the receive descriptor 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 rrfce 0 r/w rrf bit copy directive 0: indicates the rrf bit state in bit rfs4 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs4 of the receive descriptor 3 rtlfce 0 r/w rtlf bit copy directive 0: indicates the rtlf bit stat e in bit rfs3 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs3 of the receive descriptor 2 rtsfce 0 r/w rtsf bit copy directive 0: indicates the rtsf bit state in bit rfs2 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs2 of the receive descriptor 1 prece 0 r/w pre bit copy directive 0: indicates the prf bit state in bit rfs1 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs1 of the receive descriptor 0 cerfce 0 r/w cerf bit copy directive 0: indicates the cerf bit state in bit rfs0 of the receive descriptor 1: occurrence of the corresponding interrupt is not indicated in bit rfs0 of the receive descriptor section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 281 of 794 rej09b0237-0500 12.2.9 receive missed-fram e counter register (rmfcr) rmfcr is a 16-bit counter that indicates the number of frames missed (discarded, and not transferred to the receive buffer) during reception. when the recei ve fifo overflow s, the receive frames in the fifo are discarded. the number of frames discarded at this time is counted. when the value in this register reaches h'ffff, counting-up is halted. wh en this register is read, the counter value is cleared to 0. write operations to this register have no effect. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 mfc15 to mfc0 all 0 r missed-frame counter indicate the number of fr ames that are discarded and not transferred to the receive buffer during reception. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 282 of 794 rej09b0237-0500 12.2.10 transmit fifo threshold register (tftr) tftr is a 32-bit readable/writable register that sp ecifies the transmit fifo threshold at which the first transmission is started. the actual threshol d is 4 times the set value. the etherc starts transmission when the amount of data in the transmit fifo exceeds the number of bytes specified by this register, when the transmit fifo is full, or when 1-frame write is executed. when setting this register, do so in the transmission-halt state. bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 to 0 tft10 to tft0 all 0 r/w transmit fifo threshold when setting a transmit fifo, the fifo must be set to a smaller value than the spec ified value of the fifo capacity by fdr. h'00: store and forward modes h'01 to h'0c: setting prohibited h'0d: 52 bytes h'0e: 56 bytes : : h'1f: 124 bytes h'20: 128 bytes : : h'3f: 252 bytes h'40: 256 bytes : : h'7f: 508 bytes h'80: 512 bytes h'81 to h'200: setting prohibited note: when starting transmission before one frame of data write has completed, take care the generation of the underflow. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 283 of 794 rej09b0237-0500 12.2.11 fifo depth register (fdr) fdr is a 32-bit readable/writable register that specifies the depth of the transmit and receive fifos. bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 to 8 tfd2 to tfd0 b'001 r/w transmit fifo depth these bits specify the dept h of the transmit fifo. after the start of the trans mission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes other than above: setting prohibited 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 rfd2 to rfd0 b'001 r/w receive fifo depth these bits specify the depth of the receive fifo. after the start of the transmission and reception, the setting cannot be changed. 000: 256 bytes 001: 512 bytes other than above: setting prohibited section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 284 of 794 rej09b0237-0500 12.2.12 receiving method control register (rmcr) rmcr is a 32-bit readable/writable register that specifies the control me thod for the rr bit in edrrr when a frame is received. this register must be set during the receiving-halt state. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rnc 0 r/w receive enable control 0: when reception of one frame is completed, the e- dmac writes the receive st atus into the descriptor and clears the rr bit in edrrr 1: when reception of one frame is completed, the e- dmac writes the receive st atus into the descriptor, reads the next descriptor, and prepares to receive the next frame section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 285 of 794 rej09b0237-0500 12.2.13 e-dmac operation control register (edocr) edocr is a 32-bit readable/writable register that specifies the control methods used in e-dmac operation. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 fec 0 r/w fifo error control specifies e-dmac operation when transmit fifo underflow or receive fifo overflow occurs. 0: e-dmac operation continues when underflow or overflow occurs 1: e-dmac operation halts when underflow or overflow occurs 2 aec 0 r/w address error control indicates detection of an illegal memory address in an attempted e-dmac transfer. 0: illegal memory address not detected (normal operation) 1: e-dmac stops its operation due to illegal memory address detection note: to resume the operation, set the e-dmac again after software reset by means of the swr bit in edmr. 1 edh 0 r/w e-dmac halted 0: the e-dmac is operating normally 1: the e-dmac has been halted by nmi pin assertion. e-dmac operation is restarted by writing 0 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 286 of 794 rej09b0237-0500 12.2.14 receiving-buffer writ e address register (rbwar) rbwar stores the address of data to be written in the receiving buffer when the e-dmac writes data to the receiving buffer. which addresses in the receiving buffer are processed by the e- dmac can be recognized by monitoring addresses displayed in this register. the address that the e-dmac is actually processing may be differ ent from the value read from this register. bit bit name initial value r/w description 31 to 0 rbwa31 to rbwa0 all 0 r receiving-buffer write address these bits can only be read. writing is prohibited. 12.2.15 receiving-descriptor fe tch address register (rdfar) rdfar stores the descriptor star t address that is required when the e-dmac fetches descriptor information from the receiving descriptor. which receiving descriptor information is used for processing by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually fetching a descriptor may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 rdfa31 to rdfa0 all 0 r receiving-descriptor fetch address these bits can only be read. writing is prohibited. 12.2.16 transmission-buffer read address register (tbrar) tbrar stores the addres s of the transmission buffer when the e-dmac reads data from the transmission buffer. which addresses in the tran smission buffer are processed by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually reading in the buffer may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 tbra31 to tbra0 all 0 r transmission-buffer read address these bits can only be read. writing is prohibited. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 287 of 794 rej09b0237-0500 12.2.17 transmission-descriptor fetch address register (tdfar) tdfar stores the descriptor start address that is required when the e-dmac fetches descriptor information from the transmission descriptor. which transmission descriptor information is used for processing by the e-dmac can be recognized by monitoring addresses displayed in this register. the address from which the e-dmac is actually fetching a descriptor may be different from the value read from this register. bit bit name initial value r/w description 31 to 0 tdfa31 to tdfa0 all 0 r transmission-descriptor fetch address these bits can only be read. writing is prohibited. 12.2.18 flow control fifo threshold register (fcftr) fcftr is a 32-bit readable/writable register that se ts the flow control of the etherc (setting the threshold on automatic pause transmission). the threshold can be specified by the depth of the receive fifo data (rfd2 to rfd0) and the nu mber of receive frames (rff2 to rff0). the condition to start the flow control is decided by taking or operation on the two thresholds. therefore, the flow control by the two thresholds is independently started. when flow control is performed according to the rfd bits setting, if the setting is the same as the depth of the receive fifo specified by the fifo depth register (fdr), flow control is started when the remaining fifo is (fifo data ? 64) bytes. for instan ce, when rfd in fdr = 1 and rfd in fcftr = 1, flow control is started when (512 ? 64) bytes of data is st ored in the receive fifo. the value set in the rfd bits in this register should be equal to or less than those in fdr. bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 288 of 794 rej09b0237-0500 bit bit name initial value r/w description 18 17 16 rff2 rff1 rff0 1 1 1 r/w r/w r/w receive frame number flow control threshold 000: when one receive frame has been stored in the receive fifo 001: when two receive frames have been stored in the receive fifo : : 110: when seven receive frames have been stored in the receive fifo 111: when eight receive frames have been stored in the receive fifo 15 to 3 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 2 1 0 rfd2 rfd1 rfd0 0 0 0 r/w r/w r/w receive byte flow control threshold 000: when (256 ? 64) bytes of data is stored in the receive fifo 001: when (512 ? 64) bytes of data is stored in the receive fifo other than above: setting prohibited 12.2.19 transmit interrupt register (trimd) trimd is a 32-bit readable/writable register that specifies whether or not to notify write-back completion for each frame using th e twb bit in eesr and an inte rrupt on transmit operations. bit bit name initial value r/w description 31 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tis 0 r/w transmit interrupt setting 0: write-back completion for each frame is not notified 1: write-backed completion for each frame using the twb bit in eesr is notified section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 289 of 794 rej09b0237-0500 12.3 operation the e-dmac is connected to the etherc, and perfor ms efficient transfer of transmit/receive data between the etherc and memory (buffers) without the intervention of the cpu. the e-dmac itself reads control information, including buffer point ers called descriptors, re lating to the buffers. the e-dmac reads transmit data fr om the transmit buffer and writes receive data to the receive buffer in accordance with this control informat ion. by setting up a number of consecutive descriptors (a descriptor list), it is possible to execute transmission and reception continuously. 12.3.1 descriptor list and data buffers before starting transmission/recep tion, the communication program creates transmit and receive descriptor lists in memory. the start addresses of these lists are then set in the transmit and receive descriptor list start address registers. the descriptor start address must be aligned so that it matches the address boundary according to the descriptor length set by the e-dmac mode register (edmr). the transmit buffer start address can be aligned with a byte, a word, and a longword boundary. (1) transmit descriptor figure 12.2 shows the relationship between a transmit descriptor and the transmit buffer. according to the specification in this descriptor, the relationship between the transmit frame and transmit buffer can be defined as one fram e/one buffer or one frame/multi-buffer. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 290 of 794 rej09b0237-0500 transmit descriptor transmit buffer valid transmit data t a c t t d l e t f p 1 t f p 0 tfs26 to tfs0 td0 tdl td1 tba padding (4 bytes) td2 31 30 29 28 27 26 0 t f e 31 16 31 0 figure 12.2 relationship between tr ansmit descriptor and transmit buffer section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 291 of 794 rej09b0237-0500 (a) transmit descriptor 0 (td0) td0 indicates the transmit frame status. the cp u and e-dmac use td0 to report the frame transmission status. bit bit name initial value r/w description 31 tact 0 r/w transmit descriptor active indicates that this descriptor is active. the cpu sets this bit after transmit data has been transferred to the transmit buffer. the e-dmac resets this bit on completion of a frame transfer or when transmission is suspended. 0: the transmit descriptor is invalid. indicates that valid data has not been written to this bit by the cpu, or this bit has been reset by a write- back operation on termination of e-dmac frame transfer processing (completion or suspension of transmission) if this state is recognized in an e-dmac descriptor read, the e-dmac terminates transmit processing and transmit operations cannot be continued (a restart is necessary) 1: the transmit descriptor is valid. indicates that valid data has been written to the transmit buffer by the cpu and frame transfer processing has not yet been executed, or that frame transfer is in progress when this state is recognized in an e-dmac descriptor read, the e-dmac continues with the transmit operation 30 tdle 0 r/w transmit descriptor list end after completion of the co rresponding buffer transfer, the e-dmac references the first descriptor. this specification is used to set a ring configuration for the transmit descriptors. 0: this is not the last transmit descriptor list 1: this is the last transmit descriptor list section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 292 of 794 rej09b0237-0500 bit bit name initial value r/w description 29 28 tfp1 tfp0 0 0 r/w r/w transmit frame position 1, 0 these two bits specify t he relationship between the transmit buffer and transmit frame. in the preceding and following descriptors, a logically positive relationship must be maintained between the settings of this bit and the tdle bit. 00: frame transmission for transmit buffer indicated by this descriptor continues (frame is not concluded) 01: transmit buffer indicated by this descriptor contains end of frame (frame is concluded) 10: transmit buffer indicated by this descriptor is start of frame (frame is not concluded) 11: contents of transmit buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 tfe 0 r/w transmit frame error indicates that one or other bit of the transmit frame status indicated by bits 26 to 0 is set. whether or not the transmit frame status information is copied into this bit is specified by the tr ansmit/receive status copy enable register. 0: no error during transmission 1: an error occurred during transmission 26 to 0 tfs26 to tfs0 all 0 r/w transmit frame status tfs26 to tfs4: reserved (the write value should always be 0.) tfs3: carrier not detect (c orresponds to cnd bit in eesr) tfs2: detect loss of carrier (corresponds to dlc bit in eesr) tfs1: delayed collision detect (corresponds to cd bit in eesr) tfs0: transmit retry over (c orresponds to tro bit in eesr) section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 293 of 794 rej09b0237-0500 (b) transmit descriptor 1 (td1) td1 specifies the transmit buffer length (maximum 64 kbytes). bit bit name initial value r/w description 31 to 16 tdl all 0 r/w transmit buffer data length these bits specify the valid transfer byte length in the corresponding transmit buffer. when the one frame/multi-bu ffer system is specified (td0 and tfp = 10 or 00), the transfer byte length specified in the descriptors at the start and midway can be set in byte units. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. (c) transmit descriptor 2 (td2) td2 specifies the 32-bit transmit buffer start addres s. the transmit buffer start address setting can be aligned with a byte, a word, or a longword boundary. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 294 of 794 rej09b0237-0500 (2) receive descriptor figure 12.3 shows the relationshi p between a receive descriptor an d the receive buffer. in frame reception, the e-dmac performs data rewriti ng up to a receive bu ffer 16-byte boundary, regardless of the receive frame length. finally, the actual receive frame length is reported in the lower 16 bits of rd1 in the descriptor. data transfer to the receive buffer is performed automatically by the e-dmac to give a one frame/one buffer or one frame/multi-buffer configuration according to the size of one received frame. receive descriptor receive buffer valid receive data r a c t r d l e r f p 1 r f e rfs26 to rfs0 rd0 rbl rdl rd1 rba padding (4 bytes) rd2 r f p 0 31 30 29 28 27 26 0 31 16 31 0 15 0 figure 12.3 relationship between receive descriptor and receive buffer section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 295 of 794 rej09b0237-0500 (a) receive descriptor 0 (rd0) rd0 indicates the receive frame status. the cp u and e-dmac use rd0 to report the frame receive status. bit bit name initial value r/w description 31 ract 0 r/w receive descriptor active indicates that this descriptor is active. the e-dmac resets this bit after receive data has been transferred to the receive buffer. on co mpletion of receive frame processing, the cpu sets this bit to prepare for reception. 0: the receive descriptor is invalid. indicates that the receive buffer is not ready (access disabled by e-dmac), or this bit has been reset by a write-back operation on termination of e- dmac frame transfer processing (completion or suspension of reception). if this state is recognized in an e-dmac descriptor read, the e-dmac terminates receive processing and receive operations cannot be continued. reception can be restarted by setting ract to 1 and executing receive initiation. 1: the receive descriptor is valid indicates that the receive buffer is ready (access enabled) and processing for frame transfer from the fifo has not been executed, or that frame transfer is in progress. when this state is recognized in an e-dmac descriptor read, the e-dmac continues with the receive operation. 30 rdle 0 r/w receive descriptor list last after completion of the co rresponding buffer transfer, the e-dmac references the first receive descriptor. this specification is used to set a ring configuration for the receive descriptors. 0: this is not the last receive descriptor list 1: this is the last receive descriptor list section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 296 of 794 rej09b0237-0500 bit bit name initial value r/w description 29 28 rfp1 rfp0 0 0 r/w r/w receive frame position these two bits specify t he relationship between the receive buffer and receive frame. 00: frame reception for receive buffer indicated by this descriptor continues (frame is not concluded) 01: receive buffer indicated by this descriptor contains end of frame (frame is concluded) 10: receive buffer indicated by this descriptor is start of frame (frame is not concluded) 11: contents of receive buffer indicated by this descriptor are equivalent to one frame (one frame/one buffer) 27 rfe 0 r/w receive frame error indicates that one or other bit of the receive frame status indicated by bits 26 to 0 is set. whether or not the receive frame status information is copied into this bit is specified by the tr ansmit/receive status copy enable register. 0: no error during reception 1: a certain kind of error occurred during reception section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 297 of 794 rej09b0237-0500 bit bit name initial value r/w description 26 to 0 rfs26 to rfs0 all 0 r/w receive frame status these bits indicate the error status during frame reception. rfs26 to rfs10: reserved (the write value should always be 0.) rfs9: receive fifo overflow (corresponds to rfof bit in eesr) rfs8: reserved (the write value should always be 0.) rfs7: multicast address frame received (corresponds to rmaf bit in eesr) rfs6: cam entry unregistered frame received (corresponds to the ruaf bit in eesr) rsf5: reserved (the write value should always be 0.) rfs4: receive residual-bit frame error (corresponds to rrf bit in eesr) rfs3: receive too-long frame error (corresponds to rtlf bit in eesr) rfs2: receive too-short frame error (corresponds to rtsf bit in eesr) rfs1: phy-lsi receive error (corresponds to pre bit in eesr) rfs0: crc error on received frame (corresponds to cerf bit in eesr) section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 298 of 794 rej09b0237-0500 (b) receive descriptor 1 (rd1) rd1 specifies the receive buffer length (maximum 64 kbytes). bit bit name initial value r/w description 31 to 16 rbl all 0 r/w receive buffer length these bits specify the maximum reception byte length in the corresponding receive buffer. the transfer byte length must align with a 16-byte boundary (bits 19 to 16 cleared to 0). the maximum receive frame length with one frame per buffer is 1,514 bytes, excluding the crc data. therefore, for the receive buffer length spec ification, a value of 1,520 bytes (h'05f0) that takes account of a 16-byte boundary is set as the maximum receive frame length. 15 to 0 rdl all 0 r/w receive data length these bits specify the data length of a receive frame stored in the receive buffer. the receive data transferred to the receive buffer does not include the 4-byte crc data at the end of the frame. the receive frame length is reported as the number of words (valid data bytes) not including this crc data. (c) receive descriptor 2 (rd2) rd2 specifies the 32-bit receive buffer start address. the re ceive buffer start address must be aligned with a longword boundary. however, when sdram is connected, it must be aligned with a 16-byte boundary. 12.3.2 transmission when the transmit function is enabled and the tran smit request bit (tr) is set in the e-dmac transmit request register (edtrr), the e-dmac re ads the descriptor used last time from the transmit descriptor list (in the initial state, the desc riptor indicated by the transmission descriptor start address register (tdlar)). if the setting of th e tact bit in the read descriptor is active, the e-dmac reads transmit frame data sequentially from the transmit buffer start address specified by td2, and transfers it to the etherc. the etherc creates a transmit frame and starts transmission to the mii. after dma transfer of data equivalent to the buffer length specified in the descriptor, the following processing is carried out according to the tfp value. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 299 of 794 rej09b0237-0500 1. tfp = 00 or 01 (frame continuation): descriptor write-back is performed after dma transfer. 2. tfp = 01 or 11 (frame end): descriptor write-back is performed after completion of frame transmission. the e-dmac continues reading descriptors and transmitting frames as long as the setting of the tact bit in the read descriptors is "active." when a descriptor with an "inactive" tact bit is read, the e-dmac resets the transmit request bit (t r) in the transmit register and ends transmit processing (edtrr). this lsi + memory transmission flowchart e-dmac etherc phy transmit fifo etherc/e-dmac initialization descriptor and transmit buffer setting transmit directive descriptor read descriptor write-back descriptor write-back transmission completed descriptor read transmit data transfer frame transmission transmit data transfer figure 12.4 sample transmission flowchart section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 300 of 794 rej09b0237-0500 12.3.3 reception when the receive function is enabled and the cp u sets the receive request bit (rr) in the e- dmac receive request register (edrrr), the e-dmac reads th e descriptor following the previously used one from the receive descriptor list (in the initial state, the descriptor indicated by the transmission descriptor start address register (tdlar)), and then ente rs the receive-standby state. if the setting of the ract bit is "activ e" and an own-address frame is received, the e- dmac transfers the frame to the receive buffer specified by rd 2. if the data length of the received frame is greater than the buffer length given by rd1, the e-dmac performs write-back to the descriptor when the buffer is full (rfp = 10 or 00), then reads the next descriptor. the e- dmac then continues to transfer data to the receive buffer specified by the new rd2. when frame reception is completed, or if frame reception is suspended because of a certain kind of error, the e-dmac performs write-back to the relevant descriptor (rfp = 11 or 01), and then ends the receive processing. the e-dmac then reads the ne xt descriptor and ente rs the receive-standby state again. to receive frames continuously, the receive enable control bit (rnc) must be set to 1 in the receive control register (rcr). after init ialization, this bit is cleared to 0. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 301 of 794 rej09b0237-0500 this lsi + memory reception flowchart e-dmac etherc receive fifo phy etherc/e-dmac initialization descriptor and receive buffer setting reception completed receive data transfer receive data transfer frame reception start of reception descriptor read descriptor write-back descriptor write-back descriptor read (receive ready for the next frame) descriptor read figure 12.5 sample reception flowchart section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 302 of 794 rej09b0237-0500 12.3.4 multi-buffer frame tr ansmit/receive processing multi-buffer frame transmit processing if an error occurs during multi-buffer frame transmission, the processing shown in figure 12.6 is carried out by the e-dmac. where the transmit descriptor is shown as inactive (tact bit = 0) in the figure, buffer data has already been transmitted normally, and where the tr ansmit descriptor is shown as active (tact bit = 1), buffer data has not been transmitted. if a fr ame transmit error occurs in the first descriptor part where the transmit descriptor is active (tac t bit = 1), transmission is halted, and the tact bit cleared to 0, immediately. the next descriptor is then read, and the position within the transmit frame is determined on the basis of bits tfp1 and tfp0 (continuing [b'00] or end [b'01]). in the case of a continuing descriptor, the tact bit is cleared to 0, only, and the next descriptor is read immediately. if the descriptor is the final descriptor, not only is the tact bit cleared to 0, but write-back is also performed to the tfe and tfs bits at the same time. data in the buffer is not transmitted between the occurrence of an error and write-back to th e final descriptor. if error interrupts are enabled in the etherc/e-dmac status interrupt permission register (eesipr), an interrupt is generated immediately after the final descriptor write-back. 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 e-dmac inactivates tact (change 1 to 0) descriptor read inactivates tact descriptor read inactivates tact descriptor read inactivates tact descriptor read inactivates tact and writes tfe, tfs descriptors untransmitted data is not transmitted after error occurrence descriptor is only processed. one frame buffer transmitted data untransmitted data transmit error occurrence t a c t t d l e t f p 1 t f p 0 figure 12.6 e-dmac oper ation after transmit error section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 303 of 794 rej09b0237-0500 multi-buffer frame receive processing if an error occurs during multi-buffer frame reception, the processing shown in figure 12.7 is carried out by the e-dmac. where the receive descriptor is shown as inactive (ract bit = 0) in the figure, buffer data has already been received normally, and where the recei ve descriptor is shown as active (ract bit = 1), this indicates a buffer for which reception has no t yet been performed. if a frame receive error occurs in the first descriptor part where the ract bit = 1 in the figure, reception is halted immediately and a status write-back to the descriptor is performed. if error interrupts are enabled in the etherc/e -dmac status interrupt permission register (eesipr), an interrupt is generated immediately after the write-back. if there is a new frame receive request, reception is continued from th e buffer after that in which the error occurred. e-dmac inactivates ract and writes rfe, rfs descriptor read write-back descriptors buffer received data unreceived data receive error occurrence . . . . . . . . . start of frame new frame reception continues from buffer 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 r a c t r d l e r f p 1 r f p 0 figure 12.7 e-dmac oper ation after receive error section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 304 of 794 rej09b0237-0500 12.4 usage notes 12.4.1 usage notes on sh-ether ethe rc/e-dmac status register (eesr) when the status bits in eesr of the on-chip e-dm ac of the sh-ether chip are used as interrupt sources, setting of the interrupt source may fail if so ftware writes a 1 to the corresponding status bit in eesr to clear the bit and this coincides w ith setting of the status interrupt source in eesr by the etherc or e-dmac. figure 12.8 shows an example of timing in the case where setting of the interrupt source in eesr has failed. (a) in this example, both the reception interrup t and transmission interr upt sources of eesr are used. firstly, reception interrupt source a from the etherc or e-dmac sets bit a in eesr and an interrupt is generated. (b) the interrupt handler writes 1 to bit a to clear it. (c) if clearing of bit a by writing of a 1 and generation of the transmission-interrupt source b signal by the etherc or e-dm ac take place simultaneously, bit a will be cleared but the status bit for transmission-interrupt source b in eesr might not be set. internal clock (i ) reception interrupt source a generated by etherc/e-dmac transmission interrupt source b generated by etherc/e-dmac : expected operation bit a in eesr h'00000001 bit b in eesr write access to eesr by software data to be written to eesr (a) (b), (c) (c) simultaneous clearing of the bit by writing of a 1 and generation of interrupt source b. failure to generate transmission interrupt source b due to non-setting of bit b. bit clearing by writing a 1 reception interrupt source a is set in bit a of eesr. only bit a of eesr is cleared by software. figure 12.8 timing of the case where setting of the interrupt source bit in eesr by the e- dmac fails section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 305 of 794 rej09b0237-0500 (1) countermeasure this problem does not occur with all of the bits in eesr. the description applies to some bits but not others. table 12.1 shows whether the problem can occur with the individual bits and whether the state of the individual interrupt so urce is reflected in the descriptor. table 12.1 eesr bits for which this prob lem can occur and reflection of interrupt sources in the descriptor bit bit name status possibility of problem reflection in descriptor interrupt source 31 ? reserved ? ? ? 30 twb write-back complete yes ? transmit 29 ? reserved ? ? ? 28 ? reserved ? ? ? 27 ? reserved ? ? ? 26 tabt transmit abort detected yes reflected in td0 bit8 (tfs8) transmit 25 rabt receive abort detected no reflected in rd0 bit8 (rfs8) reception 24 rfcof receive frame counter overflow yes ? reception 23 ade address error no ? others 22 eci etherc status register interrupt source no ? others 21 tc frame transmission complete yes reflected in td0 bit31 (tact) transmit 20 tde transmit descriptor empty no ? transmit 19 tfuf transmit fifo underflow yes ? transmit 18 fr frame received no reflected in rd0 bit31 (ract) reception 17 rde receive descriptor empty no ? reception 16 rfof receive fifo overflow yes reflected in rd0 bit9 (rfs9) reception section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 306 of 794 rej09b0237-0500 bit bit name status possibility of problem reflection in descriptor interrupt source 15 ? reserved ? ? ? 14 ? reserved ? ? ? 13 ? reserved ? ? ? 12 ? transmit frame length error yes reflected in td0 bit4 (tfs4) transmit 11 cnd carrier not detected yes reflected in td0 bit3 (tfs3) transmit 10 dlc loss of carrier detected yes reflected in td0 bit2 (tfs2) transmit 9 cd delayed collision detected yes reflected in td0 bit1 (tfs1) transmit 8 tro transmit retry over yes reflected in td0 bit0 (tfs0) transmit 7 rmaf multicast address frame received no reflected in rd0 bit7 (rfs7) reception 6 ? reserved ? ? ? 5 ? receive frame discard request asserted no reflected in rd0 bit5 (rfs5) reception 4 rrf residual-bit frame received no reflected in rd0 bit4 (rfs4) reception 3 rtlf overly long frame received no reflected in rd0 bit3 (rfs3) reception 2 rtsf overly short frame received no reflected in rd0 bit2 (rfs2) reception 1 pre phy receive error no reflected in rd0 bit1 (rfs1) reception section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 307 of 794 rej09b0237-0500 bit bit name status possibility of problem reflection in descriptor interrupt source 0 cerf crc error in received frame no reflected in rd0 bit0 (rfs0) reception "yes": setting of this interrupt source bit can fail. "no": setting of this interrupt source bit does not fail. take the following countermeasures fo r bits where the problem can arise. ? bit 30 (twb): write-back complete interrupt source bit in eesr may not be set. check the tact bit in the transmit descriptor. tact = 0 indicates that the transmission is complete. ? bit 26 (tabt): transmit abort detection inte rrupt source bit in eesr may not be set. since the state of the interrupt source is writt en back to the relevant descriptor, check the transmit descriptor (td0) to confirm the error status. ? bit 24 (rfcof): receive frame counter overflow interrupt source bit in eesr may not be set. however, even if the software is not notified of the interrupt despite the frame counter having overflowed, the upper layer (e.g. tcp/ip) can rec ognize the error because this lsi discards the frame. after departure from the ov erflow state, storage in the r eceive fifo proceeds normally from the head of the next frame. theref ore, no problem with the system arises. ? bit 21 (tc): frame transmission complete interrupt source bit in eesr may not be set. for transmission-related processing, either procedure (a) or (b) given below is effective. (a) transmission processing without interrup t handling of the frame transmission complete interrupt 1. prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. after setting the transmit descriptors, set bit 0 (tr) in the e-dmac transmit request register (edtrr) to start transmission. 3. before setting the next frame for transmissi on in the descriptor (when a transmission task arises), check the ta ct bit of the corresponding transmit descriptor. 4. if the tact bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the tr bit in edtrr to start transmission. if the tact bit is set to 1, do not set the transmit descriptor until the next timing. (b) for systems where completion of the transmission of each frame must be confirmed (that is, set frame for transmission initiate transmission complete frame transmission set the next frame for transmission ?) 1. check the tact bit in the last descriptor of the frame for transmission and confirm that tact = 0, which means that the transmission was completed. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 308 of 794 rej09b0237-0500 ? bit 19 (tfuf): transmit fifo underflow interrupt source bit in eesr may not be set. when this bit is used as an interrupt source but is not set when it should be, the software is not notified of the interrupt. however, the upper layer will recognize the error in the form of an underflow of the transmit fifo. ? bit 16 (rfof): receive fifo overflow interrupt source b it in eesr may not be set. since the state of the interrupt source is writte n back to the relevant descriptor, check the receive descriptor (rd0) to confirm the error status. ? bit 11 (cnd), bit 10 (dlc), bit 9 (cd), bit 8 (t ro): the interrupt source bits in eesr for the carrier not detected, loss of carri er detected, delayed collision detected, and transmit retry over interrupts may not be set. however, since the states of the interrupt sources are written back to the relevant descriptor, check the transmit descriptor (td0) to confirm the error status. (2) example of a countermeasure when the soft ware configuration is based on the frame transmit complete interrupt the following descriptions are of sample counterm easures for cases when so ftware processing is based on the frame transmit complete interrupt (bit 21 (tc) in eesr). if the tc interrupt source bit (bit 21) in eesr is not set on completion of transmission, the system will continue to wait for the tc interrupt, leading to stoppage of transmission. this situation arises when the interrupt handler writes a 1 to clear th e bit. the sample method given as case (a) below takes the above possibility into account and avoi ds the problem by monitoring the transmit descriptor in interrupt processing for interrupts other than the tc interrupt. the sample method given as case (b) below avoids the above problem by setting a timeout limit for retry processing when multiple transmit descriptors are in use. note: the countermeasure should be the one that best suits the structure of your driver and other software. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 309 of 794 rej09b0237-0500 (a) countermeasure by monitoring of the tr ansmit descriptor in the processing of interrupts other than the frame tr ansmit complete (tc) interrupt 1. prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. provide a "condition flag" for use in step 5 and by interrupt handlers, and then turn off this flag. this flag serves as a condition flag into which the tact bits of transmit descriptors are read out. 3. after setting the frame for transmission in the first descriptor, start transmission by setting bit 0 (tr) in the e-dmac transm it request register (edtrr). 4. before setting the next frame for transmissi on in the transmit descriptor (when another transmission task arises), check the tact b it in the corresponding transmit descriptor. 5. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and start transmission by setting the tr bit in edt rr. if the tact bit is set to 1, turn on the condition flag and make an os service call (e.g. to acquir e the semaphore) to place the transmission task in the waiting state. note: before setting the tr bit in edtrr, always read the tr bit and make sure that tr = 0. 6. wait until the transmission task leaves th e waiting state. there are two conditions for making the os service call (e.g. returning the semaphore) from the interrupt handler to take the task out of the waiting state. ? generation of a tc interrupt ? generation of an interrupt other than the tc interrupt while the condition flag is on and tact = 0. elimination of unwanted processing by checking the tact bit is only possible when the condition flag is on. the condition flag should be turned off after the task has left the waiting state. 7. when the transmission task has left the waiting state and entered execution, set the transmit frame in the corresponding transmit descriptor and then set the tr bit in edtrr to start transmission. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 310 of 794 rej09b0237-0500 ye s ye s ye s ye s ye s ye s ye s next transmission task generated? tact = 0? 1. 2. 3. 4. 5. 7. 5. 6. no no no no no no no prepare multiple transmit descriptors. prepare the condition flag and turn it off. transmission starts transmission task interrupt handler tc interrupt? interrupt other than tc? tc: eesr frame transmission complete : processing added as the countermeasure for the problem is the condition flag on? save eesr and clear the bit by writing a 1. turn off the condition flag. generation of etherc/e-dmac interrupt end end after setting the transmit descriptor, set the tr bit in edtrr to 1. read the tact bit of the corresponding transmit descriptor. after setting the corresponding transmit descriptor, set the tr bit in edtrr to 1. has the transmission task been brought out of the waiting state by the interrupt handler? turn the condition flag on. make an os service call to place the transmission task in a waiting state. make an os service call to bring the transmission task out of the waiting state. make an os service call to bring the transmission task out of the waiting state. read the tact bit of the corresponding transmit descriptor. interrupt processing for interrupts other than tc tact = 0? figure 12.9 countermeasure by monitoring the transmit de scriptor in processing of interrupts other than the frame tr ansmit complete (tc) interrupt section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 311 of 794 rej09b0237-0500 (b) countermeasure by adding timeout processing 1. prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. after setting the descriptors, set bit 0 (tr) in the e-dmac transmit request register (edtrr) to start transmission. 3. before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the tact bit in the corresponding transmit descriptor. 4. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and set the tr bit in edtrr to start transmission. if the tact bit is set to 1, place the transmission task in a waiting state by making an os service call of a routine with a timeout function (e.g. acquire a semaphore that has a timeout). note: before setting the tr bit in edtrr, always read the tr bit and make sure that tr = 0. 5. when the transmission task has left the waiting state and entered the execution state within the time limit, set the frame for transmission in the corresponding transmit descriptor and then set the tr bit in edtrr to start transmission. taki ng the transmission task out of the waiting state should be done by the interrupt handler when the tc interrupt is generated. 6. when the timeout limit is reached, check the tact bit in the corresponding transmit descriptor. if the tact bit is clear, set the frame for transmission in the corresponding transmit descriptor and set the tr bit in edtrr to start transmission. if the tact bit is set to 1, place the transmission task in a waiting state by making an os service call of a routine with a timeout function, or execute a software reset to initialize all of the modules associated with ethernet functionality. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 312 of 794 rej09b0237-0500 ye s ye s ye s ye s ye s next transmission task generated? tact = 0? 1. 2. 3. 4. 4. 5. 6. no no no no ye s no no prepare multiple transmit descriptors. transmission starts. transmission task interrupt handler tc interrupt? interrupt other than tc? save eesr and clear the bit by writing a 1. generation of etherc/e-dmac interrupt end end after setting the transmit descriptor, set the tr bit in edtrr to 1. read the tact bit of the corresponding transmit descriptor. after setting the corresponding transmit descriptor, set the tr bit in edtrr to 1. has the transmission task left the waiting state within the specified time? place the transmission task in a waiting state by calling an os service routine with a timeout function. make an os service call to bring the transmission task out of the waiting state. interrupt processing for interrupts other than tc read the tact bit of the corresponding transmit descriptor. tact = 0? tc: eesr frame transmission complete : processing added as the countermeasure for the problem timeout figure 12.10 method of adding timeout processing section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 313 of 794 rej09b0237-0500 12.4.2 usage notes on sh-ether transmit-fifo underflow in the transmission operation of the on-chip e-dmac of the sh-ether, if the e-dmac cannot acquire bus-mastership due to occupancy of the bus by a bus master other than the e-dmac, data are not writable to the transmit fifo and an underflow occurs. the expected operation from that point is as follows: on obtaining the bus mastership, the e-dmac resumes transmission of the remaining data for transmission; on completi on of the dma transfer, it writes back to the corresponding descriptor, and then fetches the next transmit descriptor. however, if the size of the transmit fifo set by the fifo depth register (fdr) maximum frame length for transmission (1518 bytes), the e-dmac may stop operating even if the transmit request bit (tr) in the e- dmac transmit request register (edtrr) is set to 1, according to the relationship between the length of the remaining frame data and th e value of the transmit fifo pointer. the relationship between the stoppage of e-dmac operation and the state of the transmit fifo is shown below. the data for transmission, which are placed in external memory (trans mit buffer), are dma- transferred by the e-dmac to the transmit fifo and output from the mii pin via the etherc module. the transmit fifo write pointer (wp) is used when the e-dmac writes the data for transmission to the transmit fifo, and the transm it fifo read pointer (rp) is used when the etherc module reads the data for transmission from the transmit fifo. 1. after a software reset, the transmit fifo will have been initialized, and wp and rp will hold the minimum and maximum values, respectiv ely, of the transmit fifo capacity. 2. when the e-dmac starts dma transfer, wp is incremented when the data for transmission are written to the transmit fifo. on the other ha nd, rp is incremented when the data written to the transmit fifo are read out by the etherc module. note: the transmit fifo only stores the data of a single frame that is being processed. it does not store data extending over multiple frames. this means that the e-dmac does not transfer the next frame to th e transmit fifo until the data of the frame being processed are read from the transmit fifo. 3. if the e-dmac fails to get the bus mastership for a system-related reason, the dma transfer does not proceed and a transmit underflow occurs (wp = rp < frame length). read access to the transmit fifo by the etherc is then terminated and rp is initialized (to the maximum value of the size of the transmit fifo). 4. on again acquiring the bus mastership, the e-dmac resumes dma transfer of the remaining data of the frame. however, if the transmit fifo becomes full despite a failure to write all of the remaining frame data from the point when the transmit fifo underflowed, the e-dmac waits for the transmit fifo to become empty before transferring further remaining data. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 314 of 794 rej09b0237-0500 however, as stated in step 3, the read access to the transmit fifo by the etherc module will have been terminated, and the e-dmac thus stops operating with the transmit fifo full. in short, this problem arises when [initial valu e of rp ? wp value < length of remaining frame data] at the point of the transmit underflow. maximum transmit fifo capacity transmit fifo data for transmission is written by the e-dmac. data for transmission is read by etherc 1. initial state after software reset wp minimum transmit fifo capacity rp transmit fifo transmit fifo is full increment increment 2. writing and reading of the data for transmission wp rp: transmit fifo read pointer wp: transmit fifo write pointer rp maximum transmit fifo capacity transmit fifo initial state 3. transmit-fifo underflow has occurred minimum transmit fifo capacity wp rp rp data for transmission is written by the e-dmac. data for transmission is read by etherc transmit fifo 4. point where the problem makes the e-dmac stop wp rp reading of data for transmission by etherc is terminated. figure 12.11 operation when e-dm ac stops and the transmit fifo section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 315 of 794 rej09b0237-0500 (1) countermeasure this problem occurs under this condition: size of transmit fifo set in the fifo depth register (fdr) maximum length of frame for transmission (1518bytes). to release the e-dmac from the stopped state due to this problem, execute a software reset to initialize both the e-dmac and etherc modules. specific countermeasures are given below. an example for the case where the software does not use tc interrupts in transmission processing is gi ven as (2), and an example for the case with tc interrupt-driven software is given as (3). both methods require the addition of timeout processing with a maximum specified time as the timeout limit, and are based on the countermeasures explained in section 12.4.1, usage notes on the sh-ether etherc/e-dmac status register (eesr). the constant specified time corres ponds to the timeout limit stated in section 12.4.1, usage notes on the sh-ether etherc/e-dmac status register (eesr). the maximum specified time should be set with reference to the maximum times taking retry processing into consideration, as given in table 12.2. derive n, the number of repetitions of the constant specified time, from this maximum specified time. if transfer takes more than the ma ximum specified time, this indicates that the e- dmac has stopped due to a transmission underflo w. in this case, execute a software reset to initialize the etherc and e-dmac modules. since the receiving side will also be initialized by the software reset, the receiving side may require pr ocessing in a higher-lev el layer (e.g. tcp/ip). note: the countermeasure should be the one that best suits the structure of your driver and other software. (2) countermeasure for the case where the soft ware handles transmission without the aid of tc interrupts the countermeasure described under (a), processing transmission without handling of the frame transmission complete (tc) interrupt, below, is based on the method explained in the description of bit 21 in (1) of section 12.4.1, usage notes on sh-ether etherc/e-dmac status register (eesr). section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 316 of 794 rej09b0237-0500 (a) processing transmission without handlin g of the frame transmission complete (tc) interrupt 1. make initial settings for the timer. 2. prepare multiple transmit descriptors so that multiple frames can be transmitted. 3. after setting the transmit descriptors, start tr ansmission by setting bit 0 (tr) in the e-dmac transmit request register (edtrr). 4. before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the tact bit in the corresponding transmit descriptor. 5. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and start transmission by setting the tr bit in edt rr. if the tact bit is set to 1, set counter i to 0 (counter i is the variable that indicates th e number of repetitions of the timer operation to measure the specified constant period). 6. start counting by the timer. 7. when the specified constant period has elapsed, stop the timer counter and check the tact bit in the corresponding transmit descriptor. 8. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and set the tr bit in edtrr to start transmissi on. if the tact bit is set to 1, increment counter i. 9. while the tact bit is found to be 1 in step 8 and the value of counter i is less than n, repeat steps 6 to 8 until the maximum specified time is reached (the maximum specified time should be set with reference to the maximum times in consideration of retry processing given in table 12.2, and from this maximum specified time, determine n, the number of repetitions of the specified constant period; n is determined by the user with reference to table 12.2). if counter i reaches or exceeds n, the maximu m specified time has elapsed and we can judge that the e-dmac has stopped due to a transmit underflow. initialize the etherc and e-dmac modules by setting the software-reset bit swr in the e-dmac mode register (edmr). after re-making initial settings for the ethernet modul e, initialize the transmit/receive descriptors and transmit/receive buffers. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 317 of 794 rej09b0237-0500 ye s ye s ye s next transmission task generated? tact = 0? 1. 3. 2. 4. 5. 8. 5. 6. 7. 8. 9. no no ye s ye s no no no prepare multiple transmit descriptors. transmission starts. transmission task end after setting the transmit descriptor, set the tr bit in edtrr to 1. read the tact bit of the corresponding transmit descriptor. after setting the corresponding transmit descriptor, set the tr bit in edtrr to 1. read the tact bit of the corresponding transmit descriptor. tact = 0? specified constant period elapsed? i = 0; start the timer. stop the timer. issue a software reset to initialize the etherc and e-dmac modules. i >= n? i++; make initial settings for the timer. * 2 * 1 make initial settings of the etherc and e-dmac modules. initialize the transmit/receive descriptors and transmit/receive buffers. notes: 1. the specified constant period is the timeout period mentioned in section 12.4.1, usage notes on sh-ether etherc/e-dm ac status register (eesr). 2. set n with reference to the maximum specified time values in table 12.2. : processing added as the countermeasure for the problem figure 12.12 processing transmission without handling of the tc interrupt section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 318 of 794 rej09b0237-0500 (3) countermeasure for the case of tc interrupt-driven software the sample countermeasure for the case of tc interrupt-driven software shown below is the addition of timeout processing within the limit imposed by the maximum specified time. this is based on the method explained in (b) countermeasure by adding timeout processing in section 12.4.1, usage notes on the sh-ether et herc/e-dmac status register (eesr). the maximum specified time should be set with re ference to the maximum times in consideration of retry processing (table 12.2). from this maximum specified time, determine n, the number of calls of the os service routine with a timeout function. (b) countermeasure as the addi tion of timeout processing wi thin the limit imposed by the maximum specified time 1. prepare multiple transmit descriptors so that multiple frames can be transmitted. 2. after setting the transmit descriptors, start tr ansmission by setting bit 0 (tr) in the e-dmac transmit request register (edtrr). 3. before setting the next frame for transmission in the transmit descriptor (when a transmission task arises), check the tact bit in the transmit descriptor. 4. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and start transmission by setting the tr bit in edt rr. if the tact bit is set to 1, set counter i to 0 (counter i is the variable th at indicates the number of calls of the os service routine with a timeout function). then, place the transmission task in a waiting state by calling the os routine (e.g. acquire a semaphore that has a timeout limit). note: before setting the tr bit in edtrr, always read the tr bit and make sure that tr = 0. 5. when the transmission task has left the waiting state and entered the execution state within the specified constant period, set the frame for transmission in the co rresponding transmit descriptor and then set the tr bit in edtrr to start transmission. the transmission task should be taken out of the waiting state by the interrupt handler initiated by generation of the tc interrupt. 6. if the transmission task has not left the waiting state within the specified constant period, increment counter i. then, if i < n, chec k the tact bit in the corresponding transmit descriptor. the value for counting, n, is determined by the user with reference to table 12.2. 7. if the tact bit is clear, set the frame for transm ission in the corresponding transmit descriptor and set the tr bit in edtrr to start transmission. if the tact bit is set to 1, return the transmission task to the waiting state by calling an os service routine that has a timeout function, and then repeat steps 5 and 6. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 319 of 794 rej09b0237-0500 8. if counter i reaches or exceeds n, the maximum specified time has elapsed and we can judge that the e-dmac has stopped due to a transmit underflow. initialize the etherc and e-dmac modules by setting the software-reset bit swr in the e-dmac mode register (edmr). after re-making initial settings for the ethernet module, initialize the transmit/receive descriptors and transmit/receive buffers. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 320 of 794 rej09b0237-0500 notes: 1. the specified constant period is the timeout period mentioned in section 12.4.1, usage notes on sh-ether etherc/e-dm ac status register (eesr). 2. set n with reference to the maximum specified time values in table 12.2. : processing added as the countermeasure for the problem ye s ye s ye s next transmission task generated? tact = 0? 1. 2. 3. 4. 5. 5. 4. 6. 7. 8. no no ye s no no ye s no prepare multiple transmit descriptors. transmission starts. transmission task end after setting the transmit descriptor, set the tr bit in edtrr to 1. read the tact bit of the corresponding transmit descriptor. after setting the corresponding transmit descriptor, set the tr bit in edtrr to 1. call an os service routine with a timeout function to place the transmission task in a waiting state. has the transmission task left the waiting state within he constant specified time? i = 0; timeout read the tact bit of the corresponding transmit descriptor. i < n? tact = 0? i++; * 2 * 1 no no ye s ye s interrupt handler tc interrupt? interrupt other than tc? save eesr and clear the bit by writing 1. generation of etherc/e-dmac interrupt end make an os service call to bring the transmission task out of the waiting state. interrupt processing for interrupts other than tc issue a software reset to initialize the etherc and e-dmac modules. make initial settings of the etherc and e-dmac modules. initialize the transmit/receive descriptors and transmit/receive buffers. figure 12.13 countermeasure fo r the case with tc interrupt-d riven software: addition of timeout processing within the limit im posed by the maximum specified time section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 321 of 794 rej09b0237-0500 table 12.2 reference values for maximum specified time communication rate 10 mbps 100 mbps full-duplex with no flow control 1.3 ms or longer 130 s or longer half-duplex with no flow control 183 ms or longer (max. 366 ms) 18.3 ms or longer (max. 36.6 ms) maximum specified time with flow control 336 ms or longer 33.6 ms or longer note: the maximum specified time refers to the maximum time taken to transmit a single frame or the maximum time for flow control for a single frame. section 12 ethernet controller direct memory access controller (e-dmac) rev. 5.00 mar. 15, 2007 page 322 of 794 rej09b0237-0500 section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 323 of 794 rej09b0237-0500 section 13 direct memory access controller (dmac) this lsi includes the direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devi ces, and on-chip peripheral modules. 13.1 features ? four channels (two channels can receive an external request) ? 4-gbyte physical address space ? data transfer unit is selectable: byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword 4) ? maximum transfer count: 16,777,216 transfers ? address mode: dual address mode or si ngle address mode can be selected. ? transfer requests: external request, on-chip peripheral module re quest, or auto request can be selected. the following modules can issue an on-chip peripheral module request. ? scif0, scif1, scif2, and siof0 ? selectable bus modes: cycle steal mode (normal mode and intermittent mode) or burst mode can be selected. ? selectable channel priority levels: the channel priority levels are selectable between fixed mode and round-robin mode. ? interrupt request: an interrupt request can be generated to the cpu after transfers end by the specified counts. ? external request detection: there are following four types of dreq input detection. ? low level detection ? high level detection ? rising edge detection ? falling edge detection ? transfer request acknowledge signal: active levels for dack and tend can be set independently. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 324 of 794 rej09b0237-0500 figure 13.1 shows the block diagram of the dmac. sarn dmac module iteration control register control start-up control request priority control bus interface darn dmatcrn chcrn dmaor dmasr0, dmasr1 dein peripheral bus internal bus dack0 , dack1 tend0, tend1 dreq0 , dreq1 external rom external ram external i/o (memory mapped) external i/o (with acknowledge- ment) bus state controller on-chip memory on-chip peripheral module sarn: darn: dmatcrn: chcrn: dmaor: dmasr0, dmasr1: dein: n: dma source address register dma destination address register dma transfer count register dma channel control register dma operation register dma extended resource selectors dma transfer-end interrupt request to the cpu 0, 1, 2, 3 [legend] dma transfer request signal dma transfer acknowledge signal interrupt controller figure 13.1 block diagram of dmac section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 325 of 794 rej09b0237-0500 13.2 input/output pins the external pins for the dmac are described below. table 13.1 lists the configuration of the pins that are connected to external bus. the dmac has pins for 2 channels (channels 0 and 1) for external bus use. table 13.1 pin configuration channel name pin name i/o function dma transfer request dreq0 input dma transfer request input from external device to channel 0 dma transfer request acknowledge dack0 output dma transfer request acknowledge output from channel 0 to external device 0 dma transfer end tend0 output dma transfer end of dmac channel 0 output of dma transfer request dreq1 input dma transfer request input from external device to channel 1 dma transfer request acknowledge dack1 output dma transfer request acknowledge output from channel 1 to external device 1 dma transfer end tend1 output dma transfer end of dmac channel 1 output section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 326 of 794 rej09b0237-0500 13.3 register descriptions the dmac has the following registers. see section 24, list of registers, for the addresses of these registers and the state of them in each pro cessing status. the sar fo r channel 0 is expressed such as sar_0. channel 0: ? dma source address register_0 (sar_0) ? dma destination address register_0 (dar_0) ? dma transfer count re gister_0 (dmatcr_0) ? dma channel control register_0 (chcr_0) channel 1: ? dma source address register_1 (sar_1) ? dma destination address register_1 (dar_1) ? dma transfer count regi ster_1 (dmatcr_1) ? dma channel control register _1 (chcr_1) channel 2: ? dma source address register_2 (sar_2) ? dma destination address register_2 (dar_2) ? dma transfer count regi ster_2 (dmatcr_2) ? dma channel control register_2 (chcr_2) channel 3: ? dma source address register_3 (sar_3) ? dma destination address register_3 (dar_3) ? dma transfer count regi ster_3 (dmatcr_3) ? dma channel control register_3 (chcr_3) common: ? dma operation register (dmaor) ? dma extended resource selector 0 (dmars0) ? dma extended resource selector 1 (dmars1) section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 327 of 794 rej09b0237-0500 13.3.1 dma source address regist ers 0 to 3 (sar_0 to sar_3) sar are 32-bit readable/writable registers that specify the source addr ess of a dma transfer. during a dma transfer, these registers indicate the next source address. when the data is transferred from an external de vice with the dack in single address mode, the sar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. the initial value is undefined. 13.3.2 dma destination address registers 0 to 3 (dar_0 to dar_3) dar are 32-bit readable/writable registers that sp ecify the destination address of a dma transfer. during a dma transfer, these regi sters indicate the next destination address. when the data is transferred from an external de vice with the dack in single address mode, the dar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the destination address value. the initial value is undefined. 13.3.3 dma transfer count registers 0 to 3 (dmatcr_0 to dmatcr_3) dmatcr are 32-bit readable/writabl e registers that specify the dm a transfer coun t. the number of transfers is 1 when the setting is h'000000 01, 16,777,215 when h'00ffffff is set, and 16,777,216 (the maximum) when h'00000000 is set. during a dma transfer, these registers indicate the remaining transfer count. the upper eight bits of dmatcr are always read as 0, and the write value should always be 0. to transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. the initial value is undefined. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 328 of 794 rej09b0237-0500 13.3.4 dma channel control registers 0 to 3 (chcr_0 to chcr_3) chcr are 32-bit readable/writable register s that control the dma transfer mode. bit bit name initial value r/w descriptions 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 do 0 r/w dma overrun selects whether dreq is detected by overrun 0 or by overrun 1. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: detects dreq by overrun 0 1: detects dreq by overrun 1 22 tl 0 r/w transfer end level specifies whether the tend signal output is high active or low active. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr2 and chcr_3. the write value should always be 0. 0: low-active output of tend 1: high-active output of tend 21 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 am 0 r/w acknowledge mode selects whether dack is outpu t in data read cycle or in data write cycle in dual address mode. in single address mode, dack is always output regardless of the specification by this bit. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: dack output in read cycle (dual address mode) 1: dack output in write cycle (dual address mode) section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 329 of 794 rej09b0237-0500 bit bit name initial value r/w descriptions 16 al 0 r/w acknowledge level specifies whether the dack signal output is high active or low active. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 and chcr_3. the write value should always be 0. 0: low-active output of dack 1: high-active output of dack 15 14 dm1 dm0 0 0 r/w r/w destination address mode 1, 0 specify whether the dma destination address is incremented, decremented, or left fixed. (in single address mode, the dm1 and dm0 bits are ignored when data is transferred to an external device with dack.) 00: fixed destination address (setting prohibited in 16- byte transfer) 01: destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword- unit transfer, +16 in 16-byte transfer) 10: destination address is decremented (?1 in byte-unit transfer, ?2 in word-unit transfer, ?4 in longword- unit transfer; setting prohibited in 16-byte transfer) 11: setting prohibited 13 12 sm1 sm0 0 0 r/w r/w source address mode 1, 0 specify whether the dma source address is incremented, decremented, or left fixed. (in single address mode, sm1 and sm0 bits are ignored when data is transferred from an external device with dack.) 00: fixed source address (setting prohibited in 16-byte transfer) 01: source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword- unit transfer, +16 in 16-byte transfer) 10: source address is decremented (?1 in byte-unit transfer, ?2 in word-unit transfer, ?4 in longword- unit transfer; setting prohibited in 16-byte transfer) 11: setting prohibited section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 330 of 794 rej09b0237-0500 bit bit name initial value r/w descriptions resource select 3 to 0 specify which transfer requests will be sent to the dmac. the changing of transfer request source should be done in the state that the dma enable bit (de) is set to 0. 0 0 0 0 external request, dual address mode 0 0 0 1 setting prohibited 0 0 1 0 external request, single address mode external address space external device with dack 0 0 1 1 external request, single address mode external device with dack external address space 0 1 0 0 auto request 0 1 0 1 setting prohibited 0 1 1 0 setting prohibited 0 1 1 1 setting prohibited 1 0 0 0 selected by dma extended resource selector 1 0 0 1 setting prohibited 1 0 1 0 setting prohibited 1 0 1 1 setting prohibited 1 1 0 0 setting prohibited 1 1 0 1 setting prohibited 1 1 1 0 setting prohibited 1 1 1 1 setting prohibited 11 10 9 8 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w note: external request specification is valid only in chcr_0 and chcr_1. none of the external request can be selected in chcr_2 and chcr_3. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 331 of 794 rej09b0237-0500 bit bit name initial value r/w descriptions 7 6 dl ds 0 0 r/w r/w dreq level and dreq edge select specify the detecting method of the dreq pin input and the detecting level. these bits are valid only in chcr_0 and chcr_1. these bits are always reserved and read as 0 in chcr_2 and chcr_3. the write value should always be 0. in channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an auto- request is specified, these bits are invalid. 00: dreq detected in low level 01: dreq detected at falling edge 10: dreq detected in high level 11: dreq detected at rising edge 5 tb 0 r/w transfer bus mode specifies the bus mode when dma transfers data. 0: cycle steal mode 1: burst mode 4 3 ts1 ts0 0 0 r/w r/w transfer size 1, 0 specify the size of data to be transferred. select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: byte size 01: word size (2 bytes) 10: longword size (4 bytes) 11: 16-byte unit (four longword transfers) 2 ie 0 r/w interrupt enable specifies whether or not an in terrupt request is generated to the cpu at the end of the dma transfer. setting this bit to 1 generates an interrupt request (dei) to the cpu when the te bit is set to 1. 0: interrupt request is disabled. 1: interrupt request is enabled. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 332 of 794 rej09b0237-0500 bit bit name initial value r/w descriptions 1 te 0 r/(w) * transfer end flag shows that dma transfer ends. the te bit is set to 1 when data transfer ends when dmatcr becomes to 0. the te bit is not set to 1 in the following cases. ? dma transfer ends due to an nmi interrupt or dma address error before dmatcr is cleared to 0. ? dma transfer is ended by clearing the de bit and dme bit in the dma operation register (dmaor). to clear the te bit, the te bit should be written to 0 after reading 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: during the dma transfer or dma transfer has been interrupted [clearing condition] writing 0 after te = 1 read 1: dma transfer ends by the specified count (dmatcr = 0) 0 de 0 r/w dma enable enables or disables the dma transfer. in auto request mode, dma transfer starts by setting the de bit and dme bit in dmaor to 1. in this ti me, all of the bits te, nmif, and ae in dmaor must be 0. in an external request or peripheral module request, dma transfer starts if dma transfer request is generated by the devices or peripheral modules after setting the bits de and dme to 1. in this case, however, all of the bits te, nmif, and ae must be 0, which is the same as in the case of auto request mode. clearing the de bit to 0 can terminate the dma transfer. 0: dma transfer disabled 1: dma transfer enabled note: * writing 0 is possible to clear the flag. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 333 of 794 rej09b0237-0500 13.3.5 dma operation register (dmaor) dmaor is a 16-bit readable/writable register that specifies the priority level of channels at the dma transfer. this register sh ows the dma transfer status. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 cms1 cms0 0 0 r/w r/w cycle steal mode select 1, 0 select either normal mode or intermittent mode in cycle steal mode. it is necessary that all channel's bus modes are set to cycle steal mode to make valid intermittent mode. 00: normal mode 01: setting prohibited 10: intermittent mode 16 executes one dma transfer in each of 16 clocks of an external bus clock. 11: intermittent mode 64 executes one dma transfer in each of 64 clocks of an external bus clock. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pr1 pr0 0 0 r/w r/w priority mode 1, 0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: ch0 > ch1 > ch2 > ch3 01: ch0 > ch2 > ch3 > ch1 10: setting prohibited 11: round-robin mode 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 334 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 ae 0 r/(w) * address error flag indicates that an address error occurred during dma transfer. if this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. 0: no dmac address error [clearing condition] writing ae = 0 after ae = 1 read 1: dmac address error occurs 1 nmif 0 r/(w) * nmi flag indicates that an nmi interrupt occurred. if this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. when the nmi is input, the dma transfer in progress can be done in one transfer unit. when the dmac is not in operational, the nmif bit is set to 1 even if the nmi interrupt was input. 0: no nmi interrupt [clearing condition] writing nmif = 0 after nmif = 1 read 1: nmi interrupt occurs 0 dme 0 r/w dma master enable enables or disables dma transfers on all channels. if the dme bit and the de bit in chcr are set to 1, transfer is enabled. in this time, all of the bits te in chcr, nmif, and ae in dmaor must be 0. if this bit is cleared during transfer, transfers in all channels are terminated. 0: disables dma transfers on all channels 1: enables dma transfers on all channels note: * writing 0 is possible to clear the flag. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 335 of 794 rej09b0237-0500 13.3.6 dma extended resource select ors 0 and 1 (dmars0 and dmars1) dmars are 16-bit readable/writable registers that specify the dma transfer request sources from peripheral modules in each channel. dmars0 speci fies the sources for ch annels 0 and 1, and dmars1 specifies the sour ces for channels 2 and 3. this regist er can set the transfer request of scif0, scif1, scif2, and siof0. when mid/rid other than the values listed in table 13.2 is set, the operation of this lsi is not guaranteed. the transfer request fr om dmars is valid only when the resource select bits (rs3 to rs0) has been set to b'1000 for chcr_0 to chcr_3 registers. otherwise, even if dmars has been set, transfer requ est source is not accepted. ? dmars0 bit bit name initial value r/w description 15 14 13 12 11 10 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 1 (mid) see table 13.2. 9 8 c1rid1 c1rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 1 (rid) see table 13.2. 7 6 5 4 3 2 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 0 (mid) see table 13.2. 1 0 c0rid1 c0rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 0 (rid) see table 13.2. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 336 of 794 rej09b0237-0500 ? dmars1 bit bit name initial value r/w description 15 14 13 12 11 10 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 3 (mid) see table 13.2. 9 8 c3rid1 c3rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 3 (rid) see table 13.2. 7 6 5 4 3 2 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 2 (mid) see table 13.2. 1 0 c2rid1 c2rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 2 (rid) see table 13.2. table 13.2 transfer request sources peripheral module setting value for one channel (mid + rid) mid rid function h'21 01 transmit scif0 h'22 001000 10 receive h'25 01 transmit scif1 h'26 001001 10 receive h'29 01 transmit scif2 h'2a 001010 10 receive h'51 01 transmit siof0 h'52 010100 10 receive section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 337 of 794 rej09b0237-0500 13.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer. transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. in bus mode, burst mode or cycle steal mode can be selected. 13.4.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), dma operation register (dmaor), and dma exte nded resource selector s (dmars) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request occurs while transfer is enabled, the dmac tr ansfers one transfer unit of data (depending on the ts0 and ts1 settings). in auto request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. th e actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfer ha ve been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit in chcr is se t to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit in chcr or the dme bit in dmaor is changed to 0. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 338 of 794 rej09b0237-0500 figure 13.2 shows a flowchart of this procedure. normal end nmif = 1 or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor, dmars) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) te = 1 no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? nmif = 1 or ae = 1 or de = 0 or dme = 0? transfer end notes: 1. in auto-request mode, transfer begins when the nmif, ae, and te bits are all 0 and the de and dme bits are set to 1. 2. dreq = level detection in burst mode (external request) or cycle-steal mode. 3. dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 13.2 dma transfer flowchart section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 339 of 794 rej09b0237-0500 13.4.2 dma transfer requests dma transfer requests are basically generated in e ither the data transfer so urce or destination, but they can also be generated by external devices or on-chip peripheral modules that are neither the source nor the destination. transfers can be requ ested in three modes: au to request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits in dmars0 and dmars 1. auto-request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits in chcr and the dme bit in dmaor are set to 1, the transfer begins so long as th e ae and nmif bits in dmaor are all 0. external request mode: in this mode, a transfer is perfor med at the request signals (dreq0 and dreq1) of an external device. this mode is valid only in channel 0 and channel 1. choose one of the modes shown in table 13.3 accor ding to the application system. wh en this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. table 13.3 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 dual address mode any any 0 external memory, memory-mapped external device external device with dack 0 0 1 1 single address mode external device with dack external memory, memory-mapped external device choose to detect dreq by either the edge or level of the signal input with the dl bit and ds bit in chcr_0 and chcr_1 as shown in table 13.4. the source of the transfer request does not have to be the data transfer source or destination. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 340 of 794 rej09b0237-0500 table 13.4 selecting external request detection with dl, ds bits chcr_0 or chcr_1 dl ds detection of external request 0 low level detection 0 1 falling edge detection 0 high level detection 1 1 rising edge detection when dreq is accepted, the dreq pin becomes request accept disabled state. after issuing acknowledge signal dack for the accepted dreq, the dreq pin again becomes request accept enabled state. when dreq is used by level detection, there ar e following two cases by th e timing to detect the next dreq after outputting dack. ? overrun 0: transfer is aborted after the same number of transfer has been performed as requests. ? overrun 1: transfer is aborted after transfers have been performed for (the number of requests plus 1) times. the do bit in chcr selects this overrun 0 or overrun 1. table 13.5 selecting external request detection with do bit chcr_0 or chcr_1 do external request 0 overrun 0 1 overrun 1 on-chip peripheral module request mode: in this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module. tran sfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the scif0, scif1, scif2, and siof0 set by dmars0 and dmars 1. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon the input of a transfer request signal. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 341 of 794 rej09b0237-0500 when a transmit data empty transfer request of the scif0 is set as the transf er request, the transfer destination must be the scif0's transmit data register. likewise, when receive data full transfer request of the scif0 is set as the transfer request , the transfer source must be the scif0's receive data register. these conditions also apply to the scif1, scif2, and siof0. the number of the r eceive fifo triggers can be set as a tr ansfer request depending on an on-chip peripheral module. data needs to be read after th e dma transfer is ended, because data may be remained in the receive fifo when the recei ve fifo trigger condition is not satisfied. table 13.6 selecting on-chip peripheral modu le request modes with rs3 to rs0 bits chcr dmars rs[3:0] mid rid dma transfer request source dma transfer request signal source destination bus mode 01 scif0 transmitter txi0 (transmit fifo data empty interrupt) any scftdr0 cycle steal 001000 10 scif0 receiver rxi0 (receive fifo data full interrupt) scfrdr0 any cycle steal 01 scif1 transmitter txi1 (transmit fifo data empty interrupt) any scftdr0 cycle steal 001001 10 scif1 receiver rxi1 (receive fifo data full interrupt) scfrdr1 any cycle steal 01 scif2 transmitter txi2 (transmit fifo data empty interrupt) any scftdr2 cycle steal 001010 10 scif2 receiver rxi2 (receive fifo data full interrupt) scfrdr2 any cycle steal 01 siof0 transmitter txi0 (transmit fifo data empty interrupt) any sitdr0 cycle steal 1000 010100 10 siof0 receiver rxi0 (receive fifo data full interrupt) sirdr0 any cycle steal 13.4.3 channel priority when the dmac receives simultaneous transfer re quests on two or more channels, it transfers data according to a predetermined priority. two modes (fixed mode and round-robin mode) are selected by the pr1 and pr0 bits in dmaor. fixed mode: in this mode, the priority levels among the channels remain fixed. there are two kinds of fixed modes as follows: ? ch0 > ch1 > ch2 > ch3 ? ch0 > ch2 > ch3 > ch1 these are selected by the pr1 and the pr0 bits in dmaor. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 342 of 794 rej09b0237-0500 round-robin mode: in round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is transferred on one ch annel, the priority is rotated. the channel on which the transfer was just finished rotates to the bottom of the priority. the round-robin mode operation is shown in figure 13.3. the priority of round-robin mode is ch0 > ch1 > ch2 > ch3 immediately after a reset. when round-robin mode is specified, th e same bus mode, either cycle steal mode or burst mode, must be specified for all of the channels. ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 (1) when channel 0 is transferred initial priority order initial priority order initial priority order initial priority order priority order after transfer priority order does not change. channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were higher than channel 1, are also shifted. channel 1 becomes bottom priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes bottom priority priority order after transfer priority order after transfer priority order after transfer post-transfer priority order when there is an immediate transfer request to channel 1 only (2) when channel 1 is transferred (3) when channel 2 is transferred (4) when a channel 3 is transferred figure 13.3 round-robin mode section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 343 of 794 rej09b0237-0500 figure 13.4 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 (2) channel 0 transfer starts (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 13.4 changes in channe l priority in round-robin mode section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 344 of 794 rej09b0237-0500 13.4.4 dma transfer types dma transfer has two types; single address mode transfer and dual address mode transfer. they depend on the number of bus cycl es of access to source and dest ination. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. the dmac supports the transfers shown in table 13.7. table 13.7 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module x/y memory u memory external device with dack not available dual, single dual, single not available not available external memory dual, single dual dual dual dual memory-mapped external device dual, single dual dual dual dual on-chip periphera l module not available dual dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. for on-chip peripheral modules, 16-byte transfer is available only by registers which can be accessed in longword units. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 345 of 794 rej09b0237-0500 address modes: ? dual address mode in dual address mode, both the transfer source and destination are accessed by an address. the source and destination can be located externally or internally. dma transfer requires two bus cycl es because data is read from the transfer source in a data read cycle and written to the tran sfer destination in a data write cycle. at this time, transfer data is temporarily stored in the dmac. in th e transfer between extern al memories as shown in figure 13.5, data is read to the dmac from one external memo ry in a data read cycle, and then that data is written to the other external memory in a write cycle. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. first bus cycle second bus cycle the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 13.5 data flow of dual address mode auto request, external request, and on-chip pe ripheral module request are available for the transfer request. dack can be ou tput in read cycle or write cy cle in dual address mode. the channel control register (chcr) can specify whether the dack is output in read cycle or write cycle. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 346 of 794 rej09b0237-0500 figure 13.6 shows an example of dma transfer timing in dual address mode. ckio a25 to a0 note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn . d31 to d0 wen rd dackn (active-low) csn transfer source address transfer destination address data read cycle data write cycle (1st cycle) (2nd cycle) figure 13.6 example of dma tr ansfer timing in dual mode (source: ordinary memory, dest ination: ordinary memory) section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 347 of 794 rej09b0237-0500 ? single address mode in single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack si gnal, and the other device is accessed by an address. in this mode, the dm ac performs one dma transfer in one bus cycle, accessing one of the external devices by outputting the dack tr ansfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between extern al memory and an exte rnal device with dack shown in figure 13.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. dmac this lsi dack dreq external address bus external data bus external memory external device with dack data flow figure 13.7 data flow in single address mode two kinds of transfer are possib le in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack an d external memory. in both cas es, only the external request signal (dreq) is used for transfer requests. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 348 of 794 rej09b0237-0500 figure 13.8 shows an example of dma transfer timing in single address mode. address output to external memory space select signal to external memory space select signal to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space (ordinary memory) external device with dack ckio a25 to a0 d31 to d0 dackn csn we ckio a25 to a0 d31 to d0 dackn csn rd figure 13.8 example of dma transf er timing in single address mode bus modes: there are two bus modes: cycle steal mode and burst mode. select the mode in the tb bits in the channel control register (chcr). ? cycle-steal mode ? normal mode in cycle-steal normal mode, th e bus mastership is given to another bus master after a one- transfer-unit (byte, word, longword, or 16-byte unit) dma transfer. when another transfer request occurs, the bus mastership is obtained from the other bus mast er and a transfer is performed for one transfer unit. when that transfer ends, the bus mastership is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. in cycle-steal normal mode, tr ansfer areas are not affected regardless of settings of the transfer request source, transfer source, and tr ansfer destination. figure 13.9 shows an example of dma transfer timing in cycl e-steal normal mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 349 of 794 rej09b0237-0500 cpu cpu cpu dmac dmac cpu dmac dmac cpu dreq bus cycle bus mastership returned to cpu once read/write read/write figure 13.9 dma transfer exampl e in cycle-steal normal mode (dual address, dreq low level detection) ? intermittent mode 16 and intermittent mode 64 in intermittent mode of cycle steal, the dmac returns the bus mastership to other bus master whenever a unit of transfer (byte, word , longword, or 16-byte unit) is complete. if the next transfer request occurs after that, the dmac gets the bus mastership from other bus master after waiting for 16 or 64 clocks in b count. the dmac then transfers data of one unit and returns the bus mastership to othe r bus master. these oper ations are repeated until the transfer end condition is satisfied. it is thus possible to make lower the ratio of bus occupation by dma transfer than cycle-steal normal mode. when the dmac gets again the bus mastership , dma transfer can be postponed in case of entry updating due to cache miss. this intermittent mode can be used for all transf er section; transfer re quest source, transfer source, and transfer destination. the bus mode s, however, must be cycle steal mode in all channels. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 350 of 794 rej09b0237-0500 figure 13.10 shows an example of dma transf er timing in cycle steal intermittent mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection dreq cpu cpu bus cycle cpu more than 16 or 64 b (change by the cpu, lcdc, and usbh states of using bus) dmac dmac cpu cpu dmac dmac cpu read/write read/write figure 13.10 example of dma transfer in cycle steal in termittent mode (dual address, dreq low level detection) ? burst mode in burst mode, once the dmac obtains the bu s mastership, the transfer is performed continuously without releasing the bus mastership until the transfer end condition is satisfied. in external request mode with level detection of the dreq pin, however, when the dreq pin is not active, the bus mastership passes to th e other bus master after the dmac transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. burst mode cannot be used when the on-chip peripheral module is the transfer request source. figure 13.11 shows dma transfer timing in burst mode. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 13.11 dma transfer example in burst mode (dual address, dreq low level detection) section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 351 of 794 rej09b0237-0500 relationship between request modes and bus modes by dma transfer category: table 13.8 shows the relationship between request modes and bus modes by dma transfer category. table 13.8 relationship between request modes and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels external device with dack and external memory external b/c 8/16/32/128 0,1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory all * 1 b/c 8/16/32/128 0 to 5 * 4 external memory and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 5 * 4 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 5 * 4 external memory and on-chip peripheral module all * 2 c 8/16/32/128 * 3 0 to 5 * 4 memory-mapped external device and on-chip peripheral module all * 2 c 8/16/32/128 * 3 0 to 5 * 4 dual on-chip peripheral module and on-chip peripheral module all * 2 c 8/16/32/128 * 3 0 to 5 * 4 external device with dack and external memory external b/c 8/16/32 0, 1 single external device with dack and memory- mapped external device external b/c 8/16/32 0, 1 b: burst mode, c: cycle steal mode notes: 1. external requests and auto requests are all available. 2. external requests, auto requests, and on-chip peripheral module requests are all available. however, for on-chip peripheral module requests, the request source register must be designated as the transfer s ource or the transfer destination. 3. access size permitted for the on-chip perip heral module register functioning as the transfer source or transfer destination. 4. if the transfer request is an external request, channels 0 and 1 are only available. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 352 of 794 rej09b0237-0500 bus mode and channel priority: when the priority is set in fixed mode (ch0 > ch1), even though channel 1 is transferring in burst mode, if there is a transfer reques t to channel 0 which has a higher priority, the transfer of channel 0 will begin immediately. at this time, if channel 0 is also operating in bu rst mode, the channel 1 transfer will continue when the channel 0 transfer with a higher priority has completely finished. if channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority completes the transfer of one transfer unit, the channel 1 transfer will begin again without releasing the bus mastership. tran sfer will then switch between the two in the order of channel 0, channel 1, channel 0, and channel 1. for the bu s state, the cpu cycle after cycle steal mode transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode high-priority execution). this example is illustrated in figure 13.12. if th ere are channels with conf licting burst transfers, transfer for the channel with the hi ghest priority is performed first. in dma transfer for more than one channel, the dmac does not give the bus mastership to the bus master until all conflicting burst transfers have finished. cpu dma ch1 dma ch1 dma ch0 dma ch1 dma ch0 dma ch1 dma ch1 cpu ch0 ch1 ch0 dmac ch0 and ch1 cycle-steal mode dmac ch1 burst mode cpu cpu priority: ch0 > ch1 ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 13.12 bus state when mu ltiple channels are operating in round-robin mode, the priority changes according to the specifications shown in figure 13.3. note that a channel operating in cycle steal mo de cannot be handled together with a channel operating in burst mode. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 353 of 794 rej09b0237-0500 13.4.5 number of bus cycle states and dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 7, bus state controller (bsc). dreq pin sampling timing: figures 13.13, 13.14, 13.15, and 13.16 show the sample timing of the dreq input in each bus mode, respectively. ckio bus cycle dreq (rising edge) dack (high-active) cpu non-sensitive period 1st acceptance 2nd acceptance acceptance started cpu cpu dmac figure 13.13 example of dreq input det ection in cycle steal mode edge detection ckio bus cycle dreq (overrun 0, high-level) bus cycle dreq (overrun 1, high-level) dack (high-active) cpu cpu cpu dmac ckio dackn (high-active) cpu cpu cpu dmac non-sensitive period non-sensitive period non-sensitive period 1st acceptance 2nd acceptance 1st acceptance 2nd acceptance acceptance started acceptance started figure 13.14 example of dreq input det ection in cycle steal mode level detection section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 354 of 794 rej09b0237-0500 ckio dreq (rising edge) dack (high-active) cpu cpu dmac dmac bus cycle non-sensitive period burst acceptance figure 13.15 example of dreq input de tection in burst mode edge detection ckio dack (high-active) cpu cpu dmac ckio dack (high-active) cpu cpu dmac dmac bus cycle dreq (overrun 0, high-level) bus cycle dreq (overrun 1, high-level) non-sensitive period non-sensitive period 1st acceptance 1st acceptance 3rd acceptance 2nd acceptance acceptance started acceptance started acceptance started 2nd acceptance figure 13.16 example of dreq input detection in burst mode level detection section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 355 of 794 rej09b0237-0500 dmac cpu cpu cpu dmac ckio dreq dack tend bus cycle last dma transfer figure 13.17 example of dma transfer end in cycle steal mode level detection when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, th e dack output is divided because of the data alignment. this example is illustrated in figure 13.18. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 356 of 794 rej09b0237-0500 ckio cs wen wait rd address data t1 t2 taw t1 t2 note: the dack is asserted for the last transfer unit of the dma transfer. when the transfer unit is divided into several bus cycles and the cs is negated between bus cycles, the dack is also divided. dackn (active-low) figure 13.18 example of bsc ordinary memory access (no wait, idle cycle 1, longwo rd access to 16-bit device) section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 357 of 794 rej09b0237-0500 13.5 usage notes pay attentions to the following notes when the dmac is used. 13.5.1 notes on dack pin output when burst mode and cycle steal mode are simultaneously set in two or more channels, an additional dack may be asserted at the end of bu rst transfer. this phenomenon will occur when all of the conditions described below are satisfied. 1. when the dma transfer is simultaneously performed in two or more channels support both burst mode and cycle steal mode 2. when the channel to be used in burst mode is set to dual address mode, and dack is output in data write cycle 3. when the dmac cannot obtain the bus master ship consecutively even though a transfer demand of cycle steal has been received after the completion of burst transfer this phenomenon is avoided by taking either of three measures shown below. ? measure 1 after confirming the completion of burst transfer ( te bit = 1), perform the dma transfer of other cycle steal mode ? measure 2 the channel to be used in burst mode should not be set to output dack in data write cycle ? measure 3 when the dma transfer is simultaneously performed in two or more channels, set all of the channels to burst mode or cycle steal mode section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 358 of 794 rej09b0237-0500 13.5.2 notes on dreq sampling when dack is divided in external access (1) error phenomenon when the dack output is divided in an exte rnal access, dreq may be sampled twice at maximum in the external access. (2) error conditions and phenomenon conditions: the dack output is divided in an external access when: ? 16-byte access, ? 32-bit access to the 8-bit space, ? 16-bit access to the 8-bit space, or ? 32-bit access to the 16-bit space is performed with either of the following idle cycle settings made: ? idle cycles between write-write cycles (iww = 01 or more) ? idle cycles between read-read cycles in the same spaces (iwrrs = 01 or more) ? external wait mask specification (wm = 0). in addition to the above conditions, the following conditions are included depending on the detection method of dreq. ? for dreq level detection: only write access ? for dreq edge detection: both write access and read access phenomenon: the detection timings of the dreq pin in the abov e access are shown in figures 13.19 to 13.22. ckio cpu dmac write or read bus cycle non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible non-sensitive period dreq (rising edge) dack (high-active) figure 13.19 example of dreq input det ection in cycle steal mode edge detection when dack is divided to 4 by idle cycles section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 359 of 794 rej09b0237-0500 cpu dmac write or read non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance is after the next dack assertion non-sensitive period ckio bus cycle dreq (rising edge) dack (high-active) figure 13.20 example of dreq input det ection in cycle steal mode edge detection when dack is divided to 2 by idle cycles cpu dmac write non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible non-sensitive period cpu dmac write non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible non-sensitive period ckio bus cycle dreq (overrun 0, high-level) dack (high-active) dreq (overrun 1, high-level) dack (high-active) ckio bus cycle figure 13.21 example of dreq input det ection in cycle steal mode level detection when dack is divided to 4 by idle cycles section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 360 of 794 rej09b0237-0500 cpu cpu dmac write dmac write non-sensitive period 1st acceptance 2nd acceptance 3rd acceptance possible 3rd acceptance possible non-sensitive period non-sensitive period 1st acceptance 2nd acceptance non-sensitive period dreq (overrun 1, high-level) dack (high-active) ckio bus cycle dreq (overrun 0, high-level) dack (high-active) ckio bus cycle figure 13.22 example of dreq input det ection in cycle steal mode level detection when dack is divided to 2 by idle cycles (3) notes for the external access described in (2) above, note the following. 1. when the dreq edge is detected, input on e dreq edge at maximum in the bus cycle. 2. when the dreq level is detected in overrun 0, negate the dreq input in the bus cycle after the detection of the first dack output negation and before the second dack output negation. 3. when the dreq level is detected in overrun 1, negate dreq input after the detection of the first dack output assertion and before the second dack output assertion. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 361 of 794 rej09b0237-0500 13.5.3 other notes 1. before making a transition to standby mode, either wait until dma transfer finishes or suspend dma transfer. 2. if an on-chip peripheral module whose clock supply is to be stopped by the module standby function is performing dma transfer, either wa it until dma transfer finishes or suspend dma transfer before making a transition to module standby mode. 3. do not write to sar, dar, dmatcr, or dmars during dma transfer. concerning above notes 1 and 2: dma transfer end can be confirmed by checking whether the te bit in chcr is set to 1. to suspend dma transfer, clear the de bit in chcr to 0. section 13 direct memory access controller (dmac) rev. 5.00 mar. 15, 2007 page 362 of 794 rej09b0237-0500 section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 363 of 794 rej09b0237-0500 section 14 compare match timer (cmt) this lsi has an on-chip compare match timer (cmt) consisting of a 2-channel 16-bit timer. the cmt has a16-bit counter, and can generate interrupts at set intervals. 14.1 features cmt has the following features. ? selection of four counter input clocks any of four internal clocks (p /8, p /32, p /128, and p /512) can be selected independently for each channel. ? interrupt request on compare match ? when not in use, cmt can be stopped by halting its clock supply to reduce power consumption. figure 14.1 shows a block diagram of cmt. control circuit clock selection cmstr0 cmcsr0 cmcor0 cmcnt0 channel 0 channel 1 cmt p /8 cmcsr1 cmcor1 cmcnt1 p /32 p /128 p /512 p /8 p /32 p /128 p /512 clock selection control circuit comparator comparator [legend] cmstr: compare match timer start register cmcsr: compare match timer control/status register cmcor: compare match timer constant register cmcnt: compare match counter cmi: compare match interrupt module bus bus interface internal bus cmi0 cmi1 figure 14.1 block diagram of compare match timer section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 364 of 794 rej09b0237-0500 14.2 register descriptions the cmt has the following registers. ? compare match timer start register (cmstr) ? compare match timer control/status register_0 (cmcsr_0) ? compare match counter_0 (cmcnt_0) ? compare match constant register_0 (cmcor_0) ? compare match timer star t register_1 (cmstr_1) ? compare match timer control/status register_1 (cmcsr_1) ? compare match counter_1 (cmcnt_1) ? compare match constant register_1 (cmcor_1) 14.2.1 compare match tim er start register (cmstr) cmstr is a 16-bit register that selects whether compare match counter (cmcnt) operates or is stopped. cmstr is initialized to h'0000 by a power-on reset and a transition to standby mode. bit bit name initial value r/w description 15 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 str1 0 r/w count start 1 specifies whether compare ma tch counter 1 operates or is stopped. 0: cmcnt_1 count is stopped 1: cmcnt_1 count is started 0 str0 0 r/w count start 0 specifies whether compare ma tch counter 0 operates or is stopped. 0: cmcnt_0 count is stopped 1: cmcnt_0 count is started section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 365 of 794 rej09b0237-0500 14.2.2 compare match timer co ntrol/status register (cmcsr) cmcsr is a 16-bit register that indicates compar e match generation, enables interrupts and selects the counter input clock. cmcsr is initialized to h'0000 by a power-on reset and a transition to standby mode. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/(w) * compare match flag indicates whether or not the values of cmcnt and cmcor match. 0: cmcnt and cmcor values do not match [clearing condition] when 0 is written to this bit 1: cmcnt and cmcor values match 6 cmie 0 r/w compare match interrupt enable enables or disables compare match interrupt (cmi) generation when cmcnt and cmcor values match (cmf=1). 0: compare match interrupt (cmi) disabled 1: compare match interrupt (cmi) enabled 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 366 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 select the clock to be input to cmcnt from four internal clocks obtained by dividing the peripheral operating clock (p ). when the str bit in cmstr is set to 1, cmcnt starts counting on the clock selected with bits cks1 and cks0. 00: p /8 01: p /32 10: p /128 11: p /512 note: * only 0 can be written, to clear the flag. 14.2.3 compare matc h counter (cmcnt) cmcnt is a 16-bit register used as an up-counter. when the counter input clock is selected with bits cks1 and cks0 in cmcsr and the str bit in cmstr is set to 1, cmcnt starts counting using the selected clock. when the value in cmcnt and the value in comp are match constant register (cmcor) match, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. cmcnt is initialized to h'0000 by a power-on reset and a transition to standby mode. 14.2.4 compare match co nstant register (cmcor) cmcor is a 16-bit register that sets the interval up to a compare match with cmcnt. cmcor is initialized to h'ffff by a power-on reset and is init ialized to h'ffff in standby mode. section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 367 of 794 rej09b0237-0500 14.3 operation 14.3.1 interval count operation when an internal clock is selected with bits cks1 and cks0 in cmcsr and the str bit in cmstr is set to 1, cmcnt starts incrementing us ing the selected clock. when the values in cmcnt and cmcor match, cmcnt is cleared to h'0000 and the cmf flag in cmcsr is set to 1. when the cmie bit in cmcsr is set to 1, a compare match interrupt (cmi) is requested. cmcnt then starts counting up again from h'0000. figure 14.2 shows the operatio n of the compare match counter. cmcor1 h'0000 cmcnt1 value time counter cleared by compare match with cmcor1 figure 14.2 counter operation 14.3.2 cmcnt count timing one of four internal clocks (p /8, p /32, p /128, and p /512) obtained by dividing the p clock can be selected with bits cks1 and cks0 in cmcsr. figure 14.3 shows the timing. peripheral operating clock (p ) nth clock (n + 1)th clock count clock cmcnt1 n n + 1 figure 14.3 count timing section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 368 of 794 rej09b0237-0500 14.4 interrupts 14.4.1 interrupt sources the cmt has channels and each of them to which a different v ector address is allocated has compare match interrupt. when both the interrup t request flag (cmf) and interrupt enable bit (cmie) are set to 1, the corresponding interrupt request is output. when the interrupt is used to activate a cpu interrupt, the priority of channe ls can be changed by the interrupt controller settings. for details, see section 6, interrupt controller (intc). 14.4.2 timing of setting compare match flag when cmcor and cmcnt match, a compare match signal is generated and the cmf bit in cmcsr is set to 1. the compare match signal is ge nerated in the last cycle in which the values match (when the cmcnt value is updated to h'0000). that is, after a match between cmcor and cmcnt, the compare match signal is not generated until the next cmcnt counter clock input. figure 14.4 shows the timing of cmf bit setting. n peripheral operating clock (p ) counter clock cmcnt1 cmcor1 compare match signal (n + 1)th clock n 0 figure 14.4 timing of cmf setting 14.4.3 timing of cleari ng compare match flag the cmf bit in cmcsr is cl eared by reading 1 from this bit, then writing 0. section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 369 of 794 rej09b0237-0500 14.5 usage notes 14.5.1 conflict between write and co mpare-match processes of cmcnt when the compare match signal is generated in the t2 cycle while wri ting to cmcnt, clearing cmcnt has priority over writing to it. in this case, cmcnt is not written to. figure 14.5 shows the timing to clear the cmcnt counter. peripheral operating clock (p ) address internal write counter clear cmcnt t1 t2 n h'0000 cmcsr write cycle cmcnt figure 14.5 conflict between write and compare-match processes of cmcnt section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 370 of 794 rej09b0237-0500 14.5.2 conflict between word-write and count-up processes of cmcnt even when the count-up occurs in the t2 cycle while writing to cmcnt in words, the writing has priority over the count-up. in this case, the count-up is not performed. figure 14.6 shows the timing to write to cmcnt in words. m cmcnt count-up enable peripheral operating clock (p ) address internal write cmcnt t1 t2 n cmcsr write cycle cmcnt figure 14.6 conflict between word-wri te and count-up processes of cmcnt section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 371 of 794 rej09b0237-0500 14.5.3 conflict between byte-write and count-up processes of cmcnt even when the count-up occurs in the t2 cycle while writing to cmcnt in bytes, the byte-writing has priority over the count-up. in this case, the count-up is not performed. the byte data on another side, which is not written to, is also not counted and the previous contents remain. figure 14.7 shows the timing when the count-up occurs in the t2 cycle while writing to cmcnt in bytes. m xx cmcnth cmcnt count-up enable cmcnth cmcntl peripheral operating clock (p ) address internal write t1 t2 n cmcsr write cycle figure 14.7 conflict between byte-w rite and count-up processes of cmcnt 14.5.4 conflict between write processes to cmcnt with the co unting stopped and cmcor writing the same value to cmcnt with the counting stopped and cmcor is prohibited. if written, the cmf flag in cmcsr is set to 1 and cmcnt is cleared to h'0000. section 14 compare match timer (cmt) rev. 5.00 mar. 15, 2007 page 372 of 794 rej09b0237-0500 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 373 of 794 rej09b0237-0500 section 15 serial communi cation interface with fifo (scif) 15.1 overview this lsi has a three-channel serial communication interface with fifo (scif) that supports both asynchronous and clock synchronous serial communi cation. it also has 16-stage fifo registers for both transmission and reception independently for each channel that enable this lsi to perform efficient high-speed co ntinuous communication. 15.1.1 features ? asynchronous serial communication: ? serial data communication is performed by st art-stop in character units. the scif can communicate with a un iversal asynchronous receiver/tran smitter (uart), an asynchronous communication interface adapter (acia), or any other communications chip that employs a standard asynchronous seri al system. there are eight selectable serial data communication formats. ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? receive error detection: parity , framing, and overrun errors ? break detection: break is detected when a framin g error is followed by at least one frame at the space 0 level (low level). it is also detect ed by reading the rxd level directly from the port data register when a framing error occurs. ? synchronous mode: ? serial data communication is synchronized w ith a clock signal. the scif can communicate with other chips having a synchronous communication function. there is one serial data communication format. ? data length: 8 bits ? receive error detecti on: overrun errors ? full duplex communication: the transmitting and receiving sections are independent, so the scif can transmit and receive simultaneously. bo th sections use 16-stage fifo buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 374 of 794 rej09b0237-0500 ? internal or external tran smit/receive clock source: from either baud rate generator (internal) or sck pin (external) ? four types of interrupts: tr ansmit-fifo-data-empty, break , receive-fifo-data-full, and receive-error interrupts are requested independently. ? when the scif is not in use, it can be stopped by halting the clock supplied to it, saving power. ? in asynchronous, on-chip modem control functions ( rts and cts ) (only for channel 1 and channel 0). ? the number of data in the tran smit and receive fifo registers an d the number of receive errors of the receive data in the receive fifo register can be ascertained. ? a time-out error (dr) can be detected when receiving in asynchronous mode. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 375 of 794 rej09b0237-0500 figure 15.1 shows a block diagram of the scif for each channel. module data bus scfrdr (16 stage) scrsr rxd txd sck cts rts scftdr (16 stage) sctsr scsmr sclsr scfdr scfcr scfsr scbrrn parity generation parity check transmission/ reception control baud rate generator clock external clock p p /4 p /16 p /64 txi rxi eri bri scif bus interface internal data bus scscr scsptr scrsr: scfrdr: sctsr: scftdr: scsmr: scscr: [legend] scfsr: scbrr: scsptr: scfcr: scfdr: sclsr: receive shift register receive fifo data register transmit shift register transmit fifo data register serial mode register serial control register serial status register bit rate register serial port register fifo control register fifo data count register line status register figure 15.1 block diagram of scif section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 376 of 794 rej09b0237-0500 15.2 pin configuration the scif has the serial pins summarized in table 15.1. table 15.1 scif pins channel pin name a bbreviation i/o function 0 serial clock pin sck0 i/o clock i/o receive data pin rxd0 input receive data input transmit data pin txd0 output transmit data output request to send pin rts0 i/o request to send clear to send pin cts0 i/o clear to send 1 serial clock pin sck1 i/o clock i/o receive data pin rxd1 input receive data input transmit data pin txd1 ou tput transmit data output request to send rts1 output request to send clear to send pin cts1 input clear to send 2 serial clock pin sck2 i/o clock i/o receive data pin rxd2 input receive data input transmit data pin txd2 ou tput transmit data output section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 377 of 794 rej09b0237-0500 15.3 register description the scif has the following regist ers. these registers specify the data format and bit rate, and control the transmitter and receiver sections. ? receive fifo data re gister_0 (scfrdr_0) ? transmit fifo data register_0 (scftdr_0) ? serial mode register_0 (scsmr_0) ? serial control register_0 (scscr_0) ? serial status regi ster_0 (scfsr_0) ? bit rate register_0 (scbrr_0) ? fifo control register_0 (scfcr_0) ? fifo data count register_0 (scfdr_0) ? serial port register_0 (scsptr_0) ? line status register_0 (sclsr_0) ? receive fifo data re gister_1 (scfrdr_1) ? transmit fifo data register_1 (scftdr_1) ? serial mode register_1 (scsmr_1) ? serial control register_1 (scscr_1) ? serial status regi ster_1 (scfsr_1) ? bit rate register_1 (scbrr_1) ? fifo control register_1 (scfcr_1) ? fifo data count register_1 (scfdr_1) ? serial port register_1 (scsptr_1) ? line status register_1 (sclsr_1) ? receive fifo data re gister_2 (scfrdr_2) ? transmit fifo data register_2 (scftdr_2) ? serial mode register_2 (scsmr_2) ? serial control register_2 (scscr_2) ? serial status regi ster_2 (scfsr_2) ? bit rate register_2 (scbrr_2) ? fifo control register_2 (scfcr_2) ? fifo data count register_2 (scfdr_2) ? serial port register_2 (scsptr_2) ? line status register_2 (sclsr_2) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 378 of 794 rej09b0237-0500 15.3.1 receive shift register (scrsr) scrsr receives serial data. data input at the rxd pin is loaded into scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to scfrdr, the receive fifo data register. the cpu cannot read or write to scrsr directly. 15.3.2 receive fifo da ta register (scfrdr) scfrdr is a 16-stage 8-bit fifo register that stores serial recei ve data. the scif completes the reception of one byte of serial da ta by moving the received data from the receive shift register (scrsr) into scfrdr for storage. continuous reception is possible until 16 bytes are stored. the cpu can read but not write to scfrdr. if data is read when there is no receive data in the scfrdr, the value is undefined. when this register is full of recei ve data, subsequent serial data is lost. scfrdr is initialized to undefined value by a power-on reset. bit bit name initial value r/w description 7 to 0 ? undefined r fifo for transmits serial data 15.3.3 transmit shift register (sctsr) sctsr transmits serial data. the scif loads transm it data from the transmit fifo data register (scftdr) into sctsr, then transmits the data seri ally from the txd pin, lsb (bit 0) first. after transmitting one data byte, the scif automatically loads the next transmit data from scftdr into sctsr and starts transmitting again. the cpu cannot read or write to sctsr directly. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 379 of 794 rej09b0237-0500 15.3.4 transmit fifo data register (scftdr) scftdr is a 16-stage 8-bit fifo register that stores data for serial transmission. when the scif detects that the transmit shift register (sctsr) is empty, it moves transmit data written in the scftdr into sctsr and starts serial transmissi on. continuous serial transmission is performed until there is no transmit data left in scftdr. scftdr can always be written to by the cpu. when scftdr is full of transmit data (16 bytes), no more data can be written. if writing of new data is attempted, the data is ignored. scftdr is initialized to undefined value by a power-on reset. bit bit name initial value r/w description 7 to 0 ? undefined w fifo for transmits serial data 15.3.5 serial mode register (scsmr) scsmr is a 16-bit register that specifies the sc if serial commun ication format and selects the clock source for the baud rate generator. the cpu can always read and write to scsmr. scsmr is initialized to h'0000 by a power-on reset. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 c/ a 0 r/w communication mode selects whether the scif oper ates in asynchronous or synchronous mode. 0: asynchronous mode 1: synchronous mode section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 380 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 chr 0 r/w character length selects 7-bit or 8-bit data in asynchronous mode. in the synchronous mode, the data length is always eight bits, regardless of the chr setting. 0: 8-bit data 1: 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit fifo data register is not transmitted. 5 pe 0 r/w parity enable selects whether to add a parity bit to transmit data and to check the parity of receive data, in asynchronous mode. in synchronous mode, a parity bit is neither added nor checked, regardless of the pe setting. 0: parity bit not added or checked 1: parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. 4 o/ e 0 r/w parity mode selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity addition and checking. the o/ e setting is ignored in synchronous mode, or in asynchronous mode when parity addition and checking is disabled. 0: even parity * 1 1: odd parity * 2 note: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 381 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 stop 0 r/w stop bit length selects one or two bits as the stop bit length in asynchronous mode. this setting is used only in asynchronous mode. it is ignored in synchronous mode because no stop bits are added. when receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: one stop bit when transmitting, a single 1-bit is added at the end of each transmitted character. 1: two stop bits when transmitting, two 1 bits are added at the end of each transmitted character. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 select the internal clock source of the on-chip baud rate generator. four clock sources are available. p , p /4, p /16 and p /64. for further information on the clock source, bit rate register settings, and baud rate, see section 15.3.8, bit ra te register (scbrr). 00: p 01: p /4 10: p /16 11: p /64 note: p : peripheral clock section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 382 of 794 rej09b0237-0500 15.3.6 serial control register (scscr) scscr is a 16-bit register that operates the scif transmitter/receiver, enab les/disables interrupt requests, and selects the transmit/receive clock source. the cpu can always read and write to scscr. scscr is initialized to h'0000 by a power-on reset. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 tie 0 r/w transmit interrupt enable enables or disables the transmit-fifo-data-empty interrupt (txi). serial transmit data in the transmit fifo data register (scftdr) is send to the transmit shift register (sctsr). then, the tdfe flag in the serial status register (scfsr) is set to1 when the number of data in scftdr becomes less than the number of transmission triggers. at this time, a txi is requested. 0: transmit-fifo-data-empty interrupt request (txi) is disabled * 1: transmit-fifo-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by writing a greater number of transmit data than the specified transmission trigger number to scftdr and by clearing the tdfe bit to 0 after reading 1 from the tdfe bit, or can be cleared by clearing this bit to 0. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 383 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 rie 0 r/w receive interrupt enable enables or disables the receive-data-full (rxi) interrupts requested when the rdf flag or dr flag in serial status register (scfsr ) is set to1, receive-error (eri) interrupts requested when the er flag in scfsr is set to1, and break (bri) interrupts requested when the brk flag in scfsr or the orer flag in line status register (sclsr) is set to1. 0: receive-data-full interrupt (rxi), receive-error interrupt (eri), and break interrupt (bri) requests are disabled * 1: receive-data-full interrupt (rxi), receive-error interrupt (eri), and break interrupt (bri) requests are enabled note: * rxi interrupt requests can be cleared by reading the dr or rdf flag after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. eri or bri interrupt requests can be cleared by reading the er, br or orer flag after it has been set to 1, then clearing the flag to 0, or by clearing rie and reie to 0. 5 te 0 r/w transmit enable enables or disables the scif serial transmitter. 0: transmitter disabled 1: transmitter enabled * note: * serial transmission starts after writing of transmit data into scftdr. select the transmit format in scsmr and scfcr and reset the transmit fifo before setting te to 1. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 384 of 794 rej09b0237-0500 bit bit name initial value r/w description 4 re 0 r/w receive enable enables or disables the scif serial receiver. 0:receiver disabled * 1 1: receiver enabled * 2 note: 1. clearing re to 0 does not affect the receive flags (dr, er, brk, rdf, fer, per, and orer). these flags retain their previous values. 2. serial reception starts when a start bit is detected in asynchronous mode, or synchronous clock input is detected in synchronous mode. select the receive format in scsmr and scfcr and reset the receive fifo before setting re to 1. 3 reie 0 r receive error interrupt enable enables or disables the receive-error (eri) interrupts and break (bri) interrupts. the setting of reie bit is valid only when rie bit is set to 0. 0: receive-error interrupt (eri) and break interrupt (bri) requests are disabled * 1: receive-error interrupt (eri) and break interrupt (bri) requests are enabled note: * eri or bri interrupt requests can be cleared by reading the er, br or orer flag after it has been set to 1, then clearing the flag to 0, or by clearing rie and reie to 0. even if rie is set to 0, when reie is set to 1, eri or bri interrupt requests are enabled. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 385 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 select the scif clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output or serial clock input. the cke0 setting is valid only when the scif is operating on the internal clock (cke1 = 0). the cke0 setting is ignored when an external clock source is selected (cke1 = 1). in synchronous mode, select the scif operating mode in the serial mode register (scsmr), then set cke1 and cke0. ? asynchronous mode 00: internal clock, sck pin used for input pin (the input signal is ignored. the stat e of the sck pin depends on both the sckio and sckdt bits.) 01: internal clock, sck pin used for clock output ( the output clock frequency is 16 times the bit rate. ) 10: external clock, sck pin used for clock input (the input clock frequency is 16 times the bit rate.) 11: setting prohibited ? synchronous mode 00: internal clock, sck pin used for serial clock output 01: internal clock, sck pin used for serial clock output 10: external clock, sck pin used for serial clock input 11: setting prohibited section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 386 of 794 rej09b0237-0500 15.3.7 serial status register (scfsr) scfsr is a 16-bit register. the upper 8 bits indi cate the number of receives errors in the scfrdr data, and the lower 8 bits indicate the status flag indicating scif operating state. the cpu can always read and write to scfsr, but cannot write 1 to the st atus flags (er, tend, tdfe, brk, rdf, and dr). these fl ags can be cleared to 0 only if they have first been read (after being set to 1). bits 3 (fer) and 2 (per) are read-only bits that cannot be written. scfsr is initialized to h'0060 by a power-on reset. bit bit name initial value r/w description 15 14 13 12 per3 per2 per1 per0 0 0 0 0 r r r r number of parity errors indicate the number of data including a parity error in the receive data stored in the receive fifo data register (scfrdr). the value indicated by bits 15 to 12 represents the number of parity errors in scfrdr. when parity errors have occurred in all 16-byte receive data in scfrdr, per3 to per0 show 0. 11 10 9 8 fer3 fer2 fer1 fer0 0 0 0 0 r r r r number of framing errors indicate the number of data including a framing error in the receive data stored in scfrdr. the value indicated by bits 11 to 8 represents the number of framing errors in scfrdr. when framing errors have occurred in all 16-byte receive data in scfrdr, fer3 to fer0 show 0. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 387 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 er 0 r/(w) * receive error indicates the occurrence of a framing error, or of a parity error when receiving data that includes parity. * 1 0: receiving is in progress or has ended normally [clearing conditions] ? er is cleared to 0 a power-on reset ? er is cleared to 0 when the chip is when 0 is written after 1 is read from er 1: a framing error or parity error has occurred. [setting conditions] ? er is set to 1 when the stop bit is 0 after checking whether or not the last st op bit of the received data is 1 at the end of one data receive operation * 2 ? er is set to 1 when the total number of 1s in the receive data plus parity bit does not match the even/odd parity specified by the o/ e bit in scsmr notes: 1. clearing the re bit to 0 in scscr does not affect the er bit, which retains its previous value. even if a receive error occurs, the receive data is transferred to scfrdr and the receive operation is continued. whether or not the data read from scrdr includes a receive error can be detected by the fer and per bits in scfsr. 2. in two stop bits mode, only the first stop bit is checked; the second stop bit is not checked. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 388 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 tend 0 r/(w) * transmit end indicates that when the last bit of a serial character was transmitted, scftdr did not contain valid data, so transmission has ended. 0: transmission is in progress [clearing conditions] ? tend is cleared to 0 when 0 is written after 1 is read from tend after transmit data is written in scftdr 1: end of transmission [setting conditions] ? tend is set to 1 when the chip is a power-on reset ? tend is set to 1 when te is cleared to 0 in the serial control register (scscr) ? tend is set to 1 when scftdr does not contain receive data when the last bit of a one-byte serial character is transmitted section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 389 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 tdfe 0 r/(w) * transmit fifo data empty indicates that data has been transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), the number of data in scftdr has become less than the transmission trigger number specified by the ttrg1 and ttrg0 bits in the fifo control register (scfcr), and writing of transmit data to scftdr is enabled. 0: the number of transmit data written to scftdr is greater than the specified transmission trigger number [clearing conditions] ? tdfe is cleared to 0 when data exceeding the specified transmission trigger number is written to scftdr after 1 is read from the tdfe bit and then 0 is written ? tdfe is cleared to 0 when dmac write data exceeding the specified transmission trigger number to scftdr 1: the number of transmit data in scftdr is equal to or less than the specified transmission trigger number * [setting conditions] ? tdfe is set to 1 by a power-on reset ? tdfe is set to 1 when the number of transmit data in scftdr has become equal to or less than the specified transmission trigger number as a result of transmission note: * since scftdr is a 16-byte fifo register, the maximum number of data that can be written when tdfe is 1 is "16 minus the specified transmission trigger number". if an attempt is made to write additional data, the data is ignored. the number of data in scftdr is indicated by the upper 8 bits of scfdr. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 390 of 794 rej09b0237-0500 bit bit name initial value r/w description 4 brk 0 r/(w) * break detection indicates that a break signal has been detected in receive data. 0: no break signal received [clearing conditions] ? brk is cleared to 0 when the chip is a power-on reset ? brk is cleared to 0 when software reads brk after it has been set to 1, then writes 0 to brk 1: break signal received * [setting condition] ? brk is set to 1 when data including a framing error is received, and a framing error occurs with space 0 in the subsequent receive data note: * when a break is detected, transfer of the receive data (h'00) to scfrdr stops after detection. when the break ends and the receive signal becomes mark 1, the transfer of receive data resumes. 3 fer 0 r framing error indicates a framing error in the data read from the next receive fifo data register (scfrdr) in asynchronous mode. 0: no receive framing error occurred in the next data read from scfrdr [clearing conditions] ? fer is cleared to 0 when the chip undergoes a power-on reset ? fer is cleared to 0 when no framing error is present in the next data read from scfrdr 1: a receive framing error occurred in the next data read from scfrdr. [setting condition] ? fer is set to 1 when a framing error is present in the next data read from scfrdr section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 391 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 per 0 r parity error indicates a parity error in the data read from the next receive fifo data register (scfrdr) in asynchronous mode. 0: no receive parity error occurred in the next data read from scfrdr [clearing conditions] ? per is cleared to 0 when the chip undergoes a power-on reset ? per is cleared to 0 when no parity error is present in the next data read from scfrdr 1: a receive parity error occurred in the data read from scfrdr [setting condition] ? per is set to 1 when a parity error is present in the next data read from scfrdr section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 392 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 rdf 0 r/(w) * receive fifo data full indicates that receive data has been transferred to the receive fifo data register (scfrdr), and the number of data in scfrdr has become more than the receive trigger number specified by the rtrg1 and rtrg0 bits in the fi fo control register (scfcr). 0: the number of transmit data written to scfrdr is less than the specified receive trigger number [clearing conditions] ? rdf is cleared to 0 by a power-on reset ? rdf is cleared to 0 when the scfrdr is read until the number of receive data in scfrdr becomes less than the specified receive trigger number after 1 is read from rdf and then 0 is written 1: the number of receive data in scfrdr is more than the specified receive trigger number [setting condition] ? rdf is set to 1 when a number of receive data more than the specified receive trigger number is stored in scfrdr * note: * scftdr is a 16-byte fifo register. when rdf is 1, the specified receive trigger number of data can be read at the maximum. if an attempt is made to read after all the data in scfrdr has been read, the data is undefined. the number of receive data in scfrdr is indicated by the lower 8 bits of scfdr. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 393 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 dr 0 r/(w) * receive data ready indicates that the number of data in the receive fifo data register (scfrdr) is less than the specified receive trigger number, and that the next data has not yet been received after the elapse of 15 etu from the last stop bit in asynchronous mode. in clock synchronous mode, this bit is not set to 1. 0: receiving is in progress, or no receive data remains in scfrdr after receiving ended normally [clearing conditions] ? dr is cleared to 0 when the chip undergoes a power-on reset ? dr is cleared to 0 when all receive data are read after 1 is read from dr and then 0 is written 1: next receive data has not been received [setting conditions] ? dr is set to 1 when scfrdr contains less data than the specified receiv e trigger number, and the next data has not yet been received after the elapse of 15 etu from the last stop bit. * note: * this is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit) note: * the only value that can be writ ten is 0 to clear the flag. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 394 of 794 rej09b0237-0500 15.3.8 bit rate register (scbrr) scbrr is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in the serial mode register (scsmr), determines the serial transmit/receive bit rate. the cpu can always read and write to scbrr. s cbrr is initialized to h'ff by a power-on reset. each channel has independent baud rate generator control, so different values can be set in three channels. the scbrr setting is calculated as follows: ? asynchronous mode: n = 10 6 - 1 64 2 2n-1 b p ? synchronous mode: n = 10 6 - 1 8 2 2n-1 b p b: bit rate (bits/s) n: scbrr setting for baud rate generator (0 n 255) (the setting value should satisfy the electrical characteristics.) p : operating frequency for peripheral modules (mhz) n: baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 15.2.) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 395 of 794 rej09b0237-0500 table 15.2 scsmr settings scsmr settings n clock source cks1 cks0 0 p 0 0 1 p /4 0 1 2 p /16 1 0 3 p /64 1 1 note: the bit rate error in asynchro nous is given by the following formula: error (%) = - 1 100 (n + 1) b 64 2n-1 2 p 10 6 table 15.3 lists examples of scbrr settings in asynchronous mode, and table 15.4 lists examples of scbrr settings in synchronous mode. table 15.3 bit rates and scbrr settings in asynchronous mode p (mhz) 5 6 6.144 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 88 ?0.25 2 106 ?0.44 2 108 0.08 150 2 64 0.16 2 77 0.16 2 79 0.00 300 1 129 0.16 1 155 0.16 1 159 0.00 600 1 64 0.16 1 77 0.16 1 79 0.00 1200 0 129 0.16 0 155 0.16 0 159 0.00 2400 0 64 0.16 0 77 0.16 0 79 0.00 4800 0 32 ?1.36 0 38 0.16 0 39 0.00 9600 0 15 1.73 0 19 ?2.34 0 19 0.00 19200 0 7 1.73 0 9 ?2.34 0 9 0.00 31250 0 4 0.00 0 5 0.00 0 5 2.40 38400 0 3 1.73 0 4 ?2.34 0 4 0.00 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 396 of 794 rej09b0237-0500 p (mhz) 7.3728 8 9.8304 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 130 ?0.07 2 141 0.03 2 174 ?0.26 150 2 95 0.00 2 103 0.16 2 127 0.00 300 1 191 0.00 1 207 0.16 1 255 0.00 600 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 23 0.00 0 25 0.16 0 31 0.00 19200 0 11 0.00 0 12 0.16 0 15 0.00 31250 0 6 5.33 0 7 0.00 0 9 ?1.70 38400 0 5 0.00 0 6 ?6.99 0 7 0.00 p (mhz) 10 12 12.288 14.7456 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 177 ?0.25 2 212 0.03 2 217 0.08 3 64 0.70 150 2 129 0.16 2 155 0.16 2 159 0.00 2 191 0.00 300 2 64 0.16 2 77 0.16 2 79 0.00 2 95 0.00 600 1 129 0.16 1 155 0.16 1 159 0.00 1 191 0.00 1200 1 64 0.16 1 77 0.16 1 79 0.00 1 95 0.00 2400 0 129 0.16 0 155 0.16 0 159 0.00 0 191 0.00 4800 0 64 0.16 0 77 0.16 0 79 0.00 0 95 0.00 9600 0 32 ?1.36 0 38 0.16 0 39 0.00 0 47 0.00 19200 0 15 1.73 0 19 0.16 0 19 0.00 0 23 0.00 31250 0 9 0.00 0 11 0.00 0 11 2.40 0 14 ?1.70 38400 0 7 1.73 0 9 ?2.34 0 9 0.00 0 11 0.00 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 397 of 794 rej09b0237-0500 p (mhz) 16 19.6608 20 24 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 70 0.03 3 86 0.31 3 88 ?0.25 3 106 ?0.44 150 2 207 0.16 2 255 0.00 3 64 0.16 3 77 0.16 300 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 600 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 1200 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 2400 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 4800 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16 9600 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16 19200 0 25 0.16 0 31 0.00 0 32 ?1.36 0 38 0.16 31250 0 15 0.00 0 19 ?1.70 0 19 0.00 0 23 0.00 38400 0 12 0.16 0 15 0.00 0 15 1.73 0 19 ?2.34 24.576 28.7 30 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 108 0.08 3 126 0.31 3 132 0.13 150 3 79 0.00 3 92 0.46 3 97 ?0.35 300 2 159 0.00 2 186 ?0.08 2 194 0.16 600 2 79 0.00 2 92 0.46 2 97 ?0.35 1200 1 159 0.00 1 186 ?0.08 1 194 0.16 2400 1 79 0.00 1 92 0.46 1 97 ?0.35 4800 0 159 0.00 0 186 ?0.08 0 194 ?1.36 9600 0 79 0.00 0 92 0.46 0 97 ?0.35 19200 0 39 0.00 0 46 ?0.61 0 48 ?0.35 31250 0 24 ?1.70 0 28 ?1.03 0 29 0.00 38400 0 19 0.00 0 22 1.55 0 23 1.73 note: settings with an error of 1% or less are recommended. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 398 of 794 rej09b0237-0500 table 15.4 bit rates and scbrr settings in synchronous mode 5 8 16 28.7 30 bit rate (bits/s) n n n n n n n n n n 110 ? ? ? ? ? ? ? ? ? ? 250 3 77 3 124 3 249 ? ? ? ? 500 3 38 2 249 3 124 3 223 3 233 1k 2 77 2 124 2 249 3 111 3 116 2.5k 1 124 1 199 2 99 2 178 2 187 5k 0 249 1 99 1 199 2 89 2 93 10k 0 124 0 199 1 99 1 178 1 187 25k 0 49 0 79 0 159 1 71 1 74 50k 0 24 0 39 0 79 0 143 0 149 100k ? ? 0 19 0 39 0 71 0 74 250k 0 4 0 7 0 15 ? ? 0 29 500k ? ? 0 3 0 7 ? ? 0 14 1m ? ? 0 1 0 3 ? ? ? ? 2m 0 0 * 0 1 ? ? ? ? [legend] blank: no setting possible ? : setting possible, but error occurs * : continuous transmission/reception is disabled. note: settings with an error of 1% or less are recommended. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 399 of 794 rej09b0237-0500 table 15.5 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. tables 15.6 and 15.7 list the maximum rates for external clock input. table 15.5 maximum bit rates for variou s frequencies with baud rate generator (asynchronous mode) settings p (mhz) maximum bit rate (bits/s) n n 5 156250 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.6608 614400 0 0 20 625000 0 0 24 750000 0 0 24.576 768000 0 0 28.7 896875 0 0 30 937500 0 0 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 400 of 794 rej09b0237-0500 table 15.6 maximum bit rates with external clock input (asynchronous mode) p (mhz) external input clock (mh z) maximum bit rate (bits/s) 5 1.2500 78125 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 19.6608 4.9152 307200 20 5.0000 312500 24 6.0000 375000 24.576 6.1440 384000 28.7 7.1750 448436 30 7.5000 468750 table 15.7 maximum bit rates with exte rnal clock input (synchronous mode) p (mhz) external input clock (mh z) maximum bit rate (bits/s) 5 0.8333 833333.3 8 1.3333 1333333.3 16 2.6667 2666666.7 24 4.0000 4000000.0 28.7 4.7833 4783333.3 30 5.0000 5000000.0 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 401 of 794 rej09b0237-0500 15.3.9 fifo control register (scfcr) scfcr is a 16-bit register that resets the numbe r of data in the transmit and receive fifo registers, sets the trigger data number, and contains an enable bit for loop-back testing. scfcr can always be read and written to by the cpu. it is initialized to h'0000 by a power-on reset. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 rstrg2 rstrg1 rstrg0 0 0 0 r/w r/w r/w rts output active trigger when the number of receive data in the receive fifo register (scfrdr) becomes more than the number shown below, the rts signal is set to high. these bits are available only in scfcr_0 and scfcr_1. in scfcr_2, thes e bits are reserved. the initial value is 0 and the write value should always be 0. 000: 15 001: 1 010: 4 011: 6 100: 8 101: 10 110: 12 111: 14 section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 402 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 6 rtrg1 rtrg0 0 0 r/w r/w receive fifo data trigger set the specified receive trigger number. the receive data full (rdf) flag in the seri al status register (scfsr) is set when the number of receive data stored in the receive fifo register (scf rdr) exceeds the specified trigger number shown below. ? asynchronous mode 00: 1 01: 4 10: 8 11: 14 ? synchronous mode 00: 1 01: 2 10: 8 11: 14 5 4 ttrg1 ttrg0 0 0 r/w r/w transmit fifo data trigger 1 and 0 set the specified transmit trigger number. the transmit fifo data register empty (t dfe) flag in the serial status register (scfsr) is set when the number of transmit data in the transmit fifo data register (scftdr) becomes less than the specified trigger number shown below. 00: 8 (8) * 01: 4 (12) * 10: 2 (14) * 11: 0 (16) * note: * values in parentheses mean the number of remaining bytes in scftdr when the tdfe flag is set to 1. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 403 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 mce 0 r/w modem control enable enables modem control signals cts and rts . in synchronous mode, clear this bit to 0. this bit is available only in scfcr_0 and scfcr_1. in scfcr_2, this bit is reserved. the initial value is 0 and the write value should always be 0. 0: modem signal disabled * 1: modem signal enabled note: * the cts signal is fixed active 0 regardless of the input value, and the rts signal is also fixed 0. 2 tfrst 0 r/w transmit fifo data register reset disables the transmit data in the transmit fifo data register and resets the data to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * reset operation is executed by a power-on reset. 1 rfrst 0 r/w receive fifo data register reset disables the receive data in the receive fifo data register and resets the data to the empty state. 0: reset operation disabled * 1: reset operation enabled note: * reset operation is executed by a power-on reset. 0 loop 0 r/w loop-back test internally connects the transmit output pin (txd) and receive input pin (rxd) and enables loop-back testing. 0: loop back test disabled 1: loop back test enabled section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 404 of 794 rej09b0237-0500 15.3.10 fifo data count register (scfdr) scfdr is a 16-bit register which indicates the numb er of data stored in the transmit fifo data register (scftdr) and the receive fifo data register (scfrdr). it indicates the number of transmit data in scftdr with the upper eight bits, and the number of receive data in scfrdr with the lower eight bits. scfdr can always be read from by the cpu. scfdr is initialized to h'0000 by a power on reset. bit bit name initial value r/w description 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 10 9 8 t4 t3 t2 t1 t0 0 0 0 0 0 r r r r r indicate the number of non-transmitted data stored in scftdr. h'00 means no tr ansmit data, and h'10 means that scftdr is full of transmit data. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 1 0 r4 r3 r2 r1 r0 0 0 0 0 0 r r r r r indicate the number of re ceive data stored in scfrdr. h'00 means no receive data, and h'10 means that scfrdr full of receive data. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 405 of 794 rej09b0237-0500 15.3.11 serial port register (scsptr) scsptr is a 16-bit register that controls input/output and data for the pins multiplexed to the scif function. bits 7 and 6 can control the rts pin, bits 5 and 4 can control the cts pin, and bits 3 and 2 can control the sck pin. bits 1 and 0 can be used to read the input data from the rxd pin and to output data to the txd pin, so they control break of serial transfer. in addition to descriptions of individual bits shown below, see section 15.6, serial port register (scsptr) and scif pins. scsptr can always be read from or written to by the cpu. bits 7, 5, 3, and 1 in scsptr are initialized by a power-on reset. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 rtsio 0 r/w rts port input/output control controls the rts pin in combination with the rtsdt bit in this register and the mce bit in scfcr. this bit is reserved in scptr_2 of scif channel 2 since scif channel 2 does not support the flow control. 6 rtsdt ? * r/w rts port data controls the rts pin in combination with the rtsio bit in this register and the mce bit in scfcr. select the rts pin function in the pfc (pin function controller) beforehand. mce rtsio rtsdt: rts pin state 0 0 : input (initial state) 0 1 0: low level output 0 1 1: high level output 1 : sequence output according to modem control logic : don't care the rts pin state is read from this bit instead of the set value. this bit is reserved in scptr_2 of scif channel 2 since scif channel 2 does not support the flow control. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 406 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 ctsio 0 r/w cts port input/output control controls the cts pin in combination with the ctsdt bit in this register and the mce bit in scfcr. this bit is reserved in scptr_2 of scif channel 2 since scif channel 2 does not support the flow control. 4 ctsdt ? * r/w cts port data controls the cts pin in combination with the ctsio bit in this register and the mce bit in scfcr. select the cts pin function in the pfc (pin function controller) beforehand. mce ctsio ctsdt: cts pin state 0 0 : input (initial state) 0 1 0: low level output 0 1 1: high level output 1 : input to modem control logic : don't care the cts pin state is read from this bit instead of the set value. this bit is reserved in scptr_2 of scif channel 2 since scif channel 2 does not support the flow control. 3 sckio 0 r/w sck port input/output control controls the sck pin in combination with the sckdt bit in this register, the c/a bit in scsmr, and bits cke1 and cke0 in scscr. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 407 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 sckdt ? * r/w sck port data controls the sck pin in combination with the sckio bit in this register, the c/ a bit in scsmr, and bits cke1 and cke0 in scscr. select the sck pin function in the pfc (pin function controller) beforehand. c/ a cke1 cke0 sckio sckdt: sck pin state 0 0 0 0 : input (initial state) 0 0 0 0 0: low level output 0 0 0 1 1: high level output 0 0 1 : internal clock output according to serial core logic 0 1 0 : external clock input to serial core logic 0 1 1 : setting prohibited 1 0 0 : internal clock output according to serial core logic 1 0 1 : internal clock output according to serial core logic 1 1 0 : external clock input to serial core logic 1 1 1 : setting prohibited : don't care the sck pin state is read from this bit instead of the set value. 1 spbio 0 r/w serial port break input/output control controls the txd pin in co mbination with the spbdt bit in this register and the te bit in scscr. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 408 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 spbdt ? * r/w serial port break data controls the txd pin in combination with the spbio bit in this register and the te bit in scscr. the rxd pin state can also be monitored. select the txd or rxd pin function in the pfc (pin f unction controller) beforehand. te spbio spbdt: txd pin state 0 0 : input (initial state) 0 1 0: low level output 0 1 1: high level output 0 : transmit data output according to serial core logic : don't care the rxd pin state is read from this bit instead of the set value. note: * this bit is read as an undefined value and the setting value is 0. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 409 of 794 rej09b0237-0500 15.3.12 line status register (sclsr) sclsr is a 16-bit readable/writable register which can always be r ead from and written to by the cpu. however, a 1 cannot be written to the orer fl ag. this flag can be cleared to 0 only if it has first been read (after being set to 1). sclsr is initialized to h'0000 by a power-on reset. bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 orer 0 r/(w) * overrun error indicates the occurrence of an overrun error. 0: receiving is in progress or has ended normally * 1 [clearing conditions] ? orer is cleared to 0 when the chip is a power-on reset ? orer is cleared to 0 when 0 is written after 1 is read from orer. 1: an overrun error has occurred * 2 [setting condition] ? orer is set to 1 when the next serial receiving is finished while receive fifo data are full. notes: 1. clearing the re bit to 0 in scscr does not affect the orer bit, which retains its previous value. 2. the receive fifo data register (scfrdr) hold the data before an overrun error is occurred, and the next receive data is extinguished. when orer is set to 1, scif can not continue the next serial receiving. note: * the only value that can be writ ten is 0 to clear the flag. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 410 of 794 rej09b0237-0500 15.4 operation 15.4.1 overview for serial communication, th e scif has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. the scif has a 16-byte fifo buffe r for both transmit and receive operations, reducing the overhead of the cpu, and enabling continuous high-speed communication. moreover, it has rts and cts signals as modem control signals (for channels 0 and 1). the transmission format is selected in the serial mode register (scsmr), which is shown in table 15.8. the scif clock source is selected by the combination of the cke1 and cke0 bits in the serial control register (scscr), which is shown in table 15.9. asynchronous mode: ? data length is selectable: 7 or 8 bits. ? parity bit is selectable. so is the stop bit length (1 or 2 bits). the combination of the preceding selections constitutes the communi cation format and character length. ? in receiving, it is possible to detect framing er rors, parity errors, r eceive fifo data full, overrun errors, receive data ready, and breaks. ? the number of stored data bytes is indicated for both the transm it and receive fifo registers. ? an internal or external clock can be selected as the scif clock source. ? when an internal clock is selected, the sc if operates using the on-chip baud rate generator. ? when an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) synchronous mode: ? the transmission/reception format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors (orer). ? an internal or external clock can be selected as the scif clock source. ? when an internal clock is selected, the sc if operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. ? when an external clock is selected, the scif operates on the input serial clock. the on- chip baud rate generator is not used. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 411 of 794 rej09b0237-0500 table 15.8 scsmr settings and scif communication formats scsmr settings scif communication format bit 7 c/ a bit 6 chr bit 5 pe bit 3 stop mode data length parity bit stop bit length 0 0 0 0 8 bits not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 1 0 0 7 bits not set 1 bit 1 2 bits 1 0 set 1 bit 1 asynchronous 2 bits 1 * * * synchronous 8 bits not set none note: * : don't care table 15.9 scsmr and scscr setting s and scif clock source selection scsmr scscr settings scif transmit/receive clock bit 7 c/ a bit 1 cke1 bit 0 cke0 mode clock source sck pin function 0 0 0 asynchronous internal scif does not use the sck pin. the state of the sck pin depends on both the sckio and sckdt bits. 1 clock with a frequency 16 times the bit rate is output. 1 0 external input a clock with frequency 16 times the bit rate. 1 ? setting prohibited. 1 0 * synchronous internal serial clock is output. 1 0 external input the serial clock. 1 ? setting prohibited. note: * : don't care section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 412 of 794 rej09b0237-0500 15.4.2 operation in asynchronous mode in asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. serial comm unication is synchronized one character at a time. the transmitting and receiving sections of th e scif are independent, so full duplex communication is possible. the tr ansmitter and receiver are 16-byte fifo buffered, so data can be written and read while transmitti ng and receiving are in progress , enabling contin uous transmitting and receiving. figure 15.2 shows the general format of asyn chronous serial communi cation. in asynchronous serial communication, the communica tion line is normally held in the mark (high) state. the scif monitors the line and starts serial communicati on when the line goes to the space (low) state, indicating a start bit. one serial ch aracter consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in asynchronous mode , the scif synchronizes at the falling edge of the start bit. the scif samples each data bit on the eighth pul se of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 15.2 example of data form at in asynchronous communication (8-bit data with parity and two stop bits) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 413 of 794 rej09b0237-0500 transmit/receive formats: table 15.10 lists the eight commu nication formats that can be selected in asynchronous mode. th e format is selected by settings in the serial mode register (scsmr). table 15.10 serial communication formats (asynchronous mode) scsmr bits serial transmit /receive format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop [legend] start: start bit stop: stop bit p: parity bit clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the scif tr ansmit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (scsmr) and bits cke1 and cke0 in the serial control register (scscr) (table 15.9). when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the scif operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to 16 times the desired bit rate. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 414 of 794 rej09b0237-0500 transmitting and receiving data: scif in itialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scscr), then initialize the scif as follows. when changing the operation mode or the communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 initializes the transmit shift register (sctsr). clearing te and re to 0, however, does not initialize the serial status register (scfsr), transmit fifo data register (scftdr), or receive fifo data register (scfrdr), which retain their previous contents. clear te to 0 afte r all transmit data has been transmitted and the tend flag in the scfsr is set. the te bit can be cleared to 0 during transmission, but the transmit data goes to the mark state after the bit is cleared to 0. set the tfrst bit in scfcr to 1 and reset scftdr before te is set again to start transmission. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. scif operation becomes unreliable if the clock is stopped. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 415 of 794 rej09b0237-0500 figure 15.3 shows a sample flowchart for initializing the scif. start of initialization clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te, re, tie, and rie bits cleared to 0) set data transfer format in scsmr set value in scbrr 1-bit interval elapsed? set rtrg1-0 and ttrg1-0 bits in scfcr, and clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1, and set tie, rie, and reie bits end of initialization wait no yes set the clock selection in scscr. be sure to clear bits tie, rie, te, and re to 0. set the data transfer format in scsmr. write a value corresponding to the bit rate into scbrr. (not necessary if an external clock is used.) wait at least one bit interval, then set the te bit or re bit in scscr to 1. also set the rie, reie, and tie bits. setting the te bit enables the txd and rxd pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. [1] [1] [2] [3] [4] [2] [3] [4] after reading brk, dr, and er flags in scfsr, and each flag in sclsr, write 0 to clear them figure 15.3 sample flowchart for scif initialization section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 416 of 794 rej09b0237-0500 transmitting serial da ta (asynchronous mode) figure 15.4 shows a sample flow chart for serial transmission. use the following procedure for serial data transmission after enabling the scif for transmission. start of transmission read tdfe flag in scfsr tdfe = 1? write transmit data in scftdr, and read 1 from tdfe flag and tend flag in scfsr, then clear to 0 all data transmitted? read tend flag in scfsr tend = 1? break output? clear spbdt to 0 and set spbio to 1 clear te bit in scscr to 0 end of transmission no yes no yes no yes no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr, and read 1 from the tdfe and tend flags, then clear to 0. the number of transmit data bytes that can be written is 16 - (transmit trigger set number). [2] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe flag to 0. [3] break output at the end of serial transmission: to output a break in serial transmission, clear the spbdt bit to 0 and set the spbio bit to 1 in scsptr, then clear the te bit in scscr to 0. in [1] and [2], it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of scfdr. [1] [2] [3] figure 15.4 sample flowchart for transmitting serial data section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 417 of 794 rej09b0237-0500 in serial transmission, the scif operates as described below. 1. when data is written into the transmit fifo data register (scftdr), the scif transfers the data from scftdr to the transmit shift register (sctsr) and starts tran smitting. confirm that the tdfe flag in the serial status register (sc fsr) is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is (16 ? transmit trigger setting). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls below the transmit trigger number set in the fifo control register (scfcr), the tdfe flag is se t. if the tie bit in the serial control register (scsr) is set to 1 at this time, a transm it-fifo-data-empty interrupt (txi) request is generated. the serial transmit data is sent from the txd pin in the following order. a. start bit: one-bit 0 is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one or two 1 bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at th e timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if th ere is no transmit data, the tend flag in scfsr is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 418 of 794 rej09b0237-0500 figure 15.5 shows an example of the operation for transmission. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend serial data start bit data parity bit stop bit start bit idle state (mark state) data parity bit stop bit txi interrupt request data written to scftdr and tdfe flag read as 1 then cleared to 0 by txi interrupt handler one frame txi interrupt request figure 15.5 example of transmit operation (8-bit data, parity, one stop bit) 4. when modem control is enabled, transmission can be stopped and rest arted in accordance with the cts input value. when cts is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. when cts is set to 0, the next transmit data is output starting from the start bit. figure 15.6 shows an example of the operation when modem control is used (only for channel 0). serial data txd 0 d0 d1 d7 0/1 0 1 d0 d1 d7 0/1 cts drive high before stop bit start bit parity bit stop bit start bit figure 15.6 example of op eration using modem control ( cts ) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 419 of 794 rej09b0237-0500 receiving serial data (asynchronous mode): figures 15.7 and 15.8 show a sample flowchart for serial reception. use the following procedure for serial data r eception after enabling th e scif for reception. start of reception read er, dr, brk flags in scfsr and orer flag in sclsr er, dr, brk or orer = 1? read rdf flag in scfsr rdf = 1? read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? clear re bit in scscr to 0 end of reception yes no yes yes no no error handling [1] receive error handling and break detection: read the dr, er, and brk flags in scfsr, and the orer flag in sclsr, to identify any error, perform the appropriate error handling, then clear the dr, er, brk, and orer flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd pin. [2] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, read 1 from the rdf flag, and then clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [3] serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading from scrfdr. [1] [2] [3] figure 15.7 sample flowchart for receiving serial data (1) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 420 of 794 rej09b0237-0500 error handling receive error handling er = 1? brk = 1? break handling dr = 1? read receive data in scfrdr clear dr, er, brk flags in scfsr, and orer flag in sclsr, to 0 end yes yes yes no overrun error handling orer = 1? yes no no no [1] whether a framing error or parity error has occurred in the receive data that is to be read from scfrdr can be ascertained from the fer and per bits in scfsr. [2] when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00, and the break data in which a framing error occurred is stored. figure 15.8 sample flowchart for receiving serial data (2) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 421 of 794 rej09b0237-0500 in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the stop bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr) to scfrdr. c. overrun check: the scif checks that the orer flag is 0, indicating that the overrun error has not occurred. d. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. if all the above checks are passed, the receive data is stored in scfrdr. note: when a parity error or a framing error occurs, reception is not suspended. 4. if the rie bit in scscr is set to 1 when th e rdf or dr flag change s to 1, a receive-fifo- data-full interrupt (rxi) request is generated. if the rie bit or the reie bit in scscr is set to 1 when the er flag changes to 1, a receive-error interrupt (eri) request is generated. if the rie bit or the reie bit in scscr is set to 1 when the brk or orer flag changes to 1, a break reception interrupt (br i) request is generated. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 422 of 794 rej09b0237-0500 figure 15.9 shows an example of the operation for reception. 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0/1 0 rdf fer serial data start bit data parity bit stop bit start bit data parity bit stop bit rxi interrupt request one frame data read and rdf flag read as 1 then cleared to 0 by rxi interrupt handler eri interrupt request generated by receive error figure 15.9 example of scif receive operation (8-bit data, parity, one stop bit) 5. when modem control is enabled, the rts signal is output depending on the empty status of scfrdr. when rts is 0, reception is possible. when rts is 1, this indicates that the scfrdr is full and no extra data can be received. (only for channel 0 and channel 1) figure 15.10 shows an example of the operation when modem control is used. d0 d1 d2 d7 0/1 d0 d1 d7 0/1 10 0 rts serial data rxd start bit parity bit stop bit start bit figure 15.10 example of op eration using modem control ( rts ) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 423 of 794 rej09b0237-0500 15.4.3 synchronous mode in synchronous mode, the scif transmits and recei ves data in synchronization with clock pulses. this mode is suitable for high-speed serial communication. the scif transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. the transmitter an d receiver are also 16-byte fifo buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 15.11 shows the general format in synchronous serial communication. don?t care don?t care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 15.11 data format in synchronous communication in synchronous serial communicati on, each data bit is output on the communication line from one falling edge of the serial clock to the next. data is guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remain s in the state of the msb. in synchronous mode, the scif transmits data by synchronizing with the falling edge of the serial clock, and receives data by synchronizing wi th the rising edge of the serial clock. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 424 of 794 rej09b0237-0500 communication format: the data length is fixed at eight bits. no parity bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the scif transmit/receive clock. when the scif operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received character. when the scif is not transmitting or receiving, the clock signal remains in the high st ate. when only receiving, the clock signal outputs while the re bit of scscr is 1 an d the number of data in receive fifo is less than the receive fifo data trigger number. in this case, 8 (16 + 1) = 136 pulses of synchronous clock are output. to perform reception of n characters of data, select an external clock as the clock source. if an internal clock should be used, set re = 1 and te = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data. transmitting and receiving data scif initializat ion (synchronous mode): before transmitting, receiving, or changing the mode or communication format, the software must clear the te and re bits to 0 in the serial control re gister (scscr), then in itialize the scif. clearing te to 0 initializes the transmit shift register (s ctsr). clearing re to 0, however, does not initialize the rdf, per, fer, and orer flags an d receive data register (scrdr), which retain their previous contents. figure 15.12 shows a sample flowchart for initializing the scif. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 425 of 794 rej09b0237-0500 start of initialization clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 to clear the fifo buffer after reading brk, dr, and er flags in scfsr and a flag in sclsr, write 0 to clear them set cke1 and cke0 bits in scscr (leaving te, re, tie, and rie bits cleared to 0) set data transfer format in scsmr set value in scbrr 1-bit interval elapsed? set rtrg1-0 and ttrg1-0 bits in scfcr, and clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1, and set tie, rie, and reie bits end of initialization wait no yes leave the te and re bits cleared to 0 until the initialization almost ends. be sure to clear the tie, rie, te, and re bits to 0. set the cke1 and cke0 bits. set the data transfer format in scsmr. write a value corresponding to the bit rate into scbrr. this is not necessary if an external clock is used. wait at least one bit interval after this write before moving to the next step. set the te or re bit in scscr to 1. also set the tei, rie, and reie bits to enable the txd, rxd, and sck pins to be used. when transmitting, the txd pin will go to the mark state. when receiving in clocked synchronous mode with the synchronization clock output (clock master) selected, a clock starts to be output from the scif_clk pin at this point. [1] [1] [2] [3] [4] [5] [2] [3] [4] [5] figure 15.12 sample flowch art for scif initialization section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 426 of 794 rej09b0237-0500 transmitting serial data (synchronous mode): figure 15.13 shows a sample flowchart for transmitting serial data. start of transmission read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr read tdfe and tend flags in scfsr while they are 1, then clear them to 0 all data transmitted? read tend flag in scfsr tend = 1? clear te bit in scscr to 0 end of transmission no yes no yes no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr. read the tdfe and tend flags while they are 1, then clear them to 0. [2] serial transmission continuation procedeure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, them write data to scftdr, and then clear the tdfe flag to 0. [1] [2] figure 15.13 sample flowchart for transmitting serial data section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 427 of 794 rej09b0237-0500 in transmitting serial data, the scif operates as follows: 1. when data is written into the transmit fifo data register (scftdr), the scif transfers the data from scftdr to the transmit shift register (sctsr) and starts tran smitting. confirm that the tdfe flag in the serial stat us register (scfsr) is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is (16 ? transmit trigger setting). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls below the transmit trigger number set in the fifo control register (scfcr), the tdfe flag is se t. if the tie bit in the serial control register (scsr) is set to 1 at this time, a transm it-fifo-data-empty interrupt (txi) request is generated. if clock output mode is selected, the scif outputs eight synchronous clock pulses. if an external clock source is selected, the scif ou tputs data in synchronization with the input clock. data is output from the txd pin in order from the lsb (bit 0) to the msb (bit 7). 3. the scif checks the scftdr transmit data at the timing for sending the msb (bit 7). if data is present, the data is transf erred from scftdr to sctsr, the msb (bit 7) is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in scfsr is set to 1, the msb (bit 7) is sent, and then the txd pin holds the states. 4. after the end of serial transmission, the sck pin is held in the high state. figure 15.14 shows an example of scif transmit operation. synchronization clock serial data tdfe tend data written to scftdr and tdfe flag cleared to 0 by txi interrupt handler one frame bit 0 lsb txi interrupt request msb bit 1 bit 6 bit 7 bit 7 bit 0 bit 1 txi interrupt request figure 15.14 example of scif transmit operation section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 428 of 794 rej09b0237-0500 receiving serial data (synchronous mode): figure 15.15 and 15.16 show a sample flowchart for receiving serial data. when switching from asynchronous mode to sy nchronous mode without scif initialization, make sure that orer, per, and fer are cleared to 0. start of reception read orer flag in sclsr orer = 1? read rdf flag in scfsr rdf = 1? read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? clear re bit in scscr to 0 end of reception yes no yes yes no no error handling [1] receive error handling: read the orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the orer flag to 0. transmission/reception cannot be resumed while the orer flag is set to 1. [2] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, and clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [3] serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading scfrdr. [1] [2] [3] figure 15.15 sample flowchart for receiving serial data (1) error handling clear orer flag in sclsr to 0 end overrun error handling orer = 1? yes no figure 15.16 sample flowchart for receiving serial data (2) section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 429 of 794 rej09b0237-0500 in receiving, the scif operates as follows: 1. the scif synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into scrsr in order from the lsb to the msb. after receiving the data, the scif checks the receive data can be load ed from scrsr into scfrdr or not. if this check is passed, the scif stores the received data in scfrdr. if the check is not passed (overrun error is detected), further reception is prevented. 3. after setting rdf to 1, if the receive-data-full interrupt enable bit (rie) is set to 1 in scscr, the scif requests a receive-data -full interrupt (rxi). if the orer bit is set to 1 and the rie bit or reie bit in scscr is also set to 1, the scif requests a break interrupt (bri). figure 15.17 shows an example of scif receive operation. synchronization clock serial data rdf orer data read from scfrdr and rdf flag cleared to 0 by rxi interrupt handler one frame bit 7 lsb rxi interrupt request msb bit 0 bit 6 bit 7 bit 7 bit 0 bit 1 bri interrupt request by overrun error rxi interrupt request figure 15.17 example of scif receive operation section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 430 of 794 rej09b0237-0500 transmitting and receiving serial data simultaneously (synchronous mode): figure 15.18 shows a sample flowchart fo r transmitting and receiving se rial data simultaneously. start of transmission and reception initialization read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr read tdfe and tend flags in scfsr while they are 1, then clear them to 0 read orer flag in sclsr orer = 1? read rdf flag in scfsr rdf = 1? clear te and re bits in scscr to 0 end of transmission and reception read receive data in scfrdr, and clear rdf flag in scfsr to 0 all data received? no no yes no no yes yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr. read the tdfe and tend flags while they are 1, then clear them to 0. the transition of the tdfe flag from 0 to 1 can also be identified by a txi interrupt. [2] receive error handling: read the orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the orer flag to 0. reception cannot be resumed while the orer flag is set to 1. [3] scif status check and receive data read: read scfsr and check that rdf = 1, then read the receive data in scfrdr, and clear the rdf flag to 0. the transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. [4] serial transmission and reception continuation procedure: to continue serial transmission and reception, read 1 from the rdf flag and the receive data in scfrdr, and clear the rdf flag to 0 before receiving the msb in the current frame. similarly, read 1 from the tdfe flag to confirm that writing is possible before transmitting the msb in the current frame. then write data to scftdr and clear the tdfe flag to 0. [1] yes error handling [4] when switching from a transmit operation or receive operation to simultaneous transmission and reception operations, clear the te and re bits to 0, and then set them simultaneously to 1. note: [3] [2] figure 15.18 sample flowchart for transmitting/receiving serial data section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 431 of 794 rej09b0237-0500 15.5 scif interrupts the scif has four interrupt sources: transmit-fifo-data-empty (txi), receive-error (eri), receive-data-full (rxi), and break (bri). table 15.11 shows the interrupt sources and their order of priority. the interrupt sources are enabled or disabled by means of the tie, rie, and reie bits in scscr. a separate interrupt request is sent to the interrupt contro ller for each of these interrupt sources. when txi request is enabled by tie bit and the tdfe flag in the serial stat us register (scfsr) is set to 1, a txi interrupt request is generated. when rxi request is enabled by rie bit and the rdf or dr flag in scfsr is set to 1, an rxi interrupt request is generated. the rxi interrupt request caused by dr flag is generated only in asynchronous mode. when bri request is enabled by rie bit or reie bit and the brk flag in scfsr or orer flag in sclsr is set to 1, a bri interrupt request is generated. when eri request is enabled by rie bit or reie bit and the er flag in scfcr is set to 1, an eri interrupt request is generated. when the rie bit is set to 0 and the reie bit is set to 1, scif request eri interrupt and bri interrupt without requesting rxi interrupt. the txi interrupt indicates that transmit data can be written, and the rxi interrupt indicates that there is receive data in scfrdr. table 15.11 scif interrupt sources interrupt source description interrupt enable bit priority on reset release eri interrupt initiated by receive error (er) rie or reie high rxi interrupt initiated by rece ive data fifo full (rdf) or data ready (dr) rie bri interrupt initiated by break (brk) or overrun error (orer) rie or reie txi interrupt initiated by transmit fifo data empty (tdfe) tie low section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 432 of 794 rej09b0237-0500 15.6 serial port register (s csptr) and scif pins the relationship between scsptr and the scif pins is shown in figures 15.19 to 15.23. sptrw: scsptr write sptrr: scsptr read note: * the modem control function is specified for the rts pin by setting the mce bit in scfcr. reset internal data bus modem control enable signal * bit 7 bit 6 reset rts signal qd r rtsio rts c qd r rtsdt sptrw sptrw sptrr c figure 15.19 rtsio bit, rtsdt bit, and rts pin section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 433 of 794 rej09b0237-0500 sptrw: scsptr write sptrr: scsptr read note: * the modem control function is specified for the cts pin by setting the mce bit in scfcr. reset internal data bus modem control enable signal * bit 5 bit 4 reset cts signal qd r ctsio cts c qd r ctsdt sptrw sptrw sptrr c figure 15.20 ctsio bit, ctsdt bit, and cts pin section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 434 of 794 rej09b0237-0500 sptrw: scsptr write sptrr: scsptr read note: * these signals control the sck pin according to the settings of the c/ a bit in scsmr and bits cke1 and cke0 in scscr. reset internal data bus clock output enable signal * sirial clock output signal * serial clock input signal * serial input enable signal * bit 3 bit 2 reset qd r sckio sck2 c qd r sckdt sptrw sptrw sptrr c figure 15.21 sckio bit, sckdt bit, and sck pin sptrw: scsptr write reset internal data bus transmit enable signal bit 1 bit 0 reset serial transmit data qd r spbio txd c qd r spbdt sptrw sptrw c figure 15.22 spbio bit, spbdt bit, and txd pin section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 435 of 794 rej09b0237-0500 sptrr: scsptr read internal data bus serial receive data rxd sptrr bit 0 figure 15.23 spbdt bit and rxd pin section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 436 of 794 rej09b0237-0500 15.7 usage notes note the following when using the scif. 1. scftdr writing and tdfe flag the tdfe flag in the serial status register (s cfsr) is set when the number of transmit data bytes written in the transmit fifo data regist er (scftdr) has fall en below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr). after tdfe is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again after being read as 1 and cleared to 0. tdfe clearing should therefore be carried out when scftdr contains more than the transmit trigger number of transmit data bytes. the number of tran smit data bytes in scftdr can be found from the upper 8 bits of the fifo data count register (scfdr). 2. scfrdr reading and rdf flag the rdf flag in the serial status register (scfsr) is set when th e number of receive data bytes in the receive fifo data register (scfrdr) ha s become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). after rdf is set, receive data equivalent to the trig ger number can be read from scfrdr, allowing efficient continuous reception. however, if the number of data bytes in scfrdr is equal to or greater than the trigger number, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after all the receive data has been read. the number of receive data bytes in scfrdr can be found from the lowe r 8 bits of the fifo data count register (scfdr). 3. break detection and processing break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) ma y also be set. note that, altho ugh transfer of receive data to scfrdr is halted in the break state, th e scif receiver continues to operate. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 437 of 794 rej09b0237-0500 4. sending a break signal the i/o condition and level of the txd pin are determined by the spbio and spbdt bits in the serial port register (scsptr). this f eature can be used to send a break signal. until te bit is set to 1 (enabling transmission) after initializing, txd pin does not work. during the period, mark status is performed by spbdt bit. therefore, the spbio and spbdt bits should be set to 1 (high level output). to send a break signal during serial transmissi on, clear the spbdt bit to 0 (designating low level), then clear the te bit to 0 (halting transmission). when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the txd pin. 5. receive data sampling timing and receive marg in (asynchronous mode) the scif operates on a base clock with a frequenc y of 16 times the transf er rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 15.24. 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 d0 d1 16 clocks 8 clocks base clock receive data (rxd) start bit ?7.5 clocks +7.5 clocks synchronization sampling timing data sampling timing figure 15.24 receive data sampling timing in asynchronous mode section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 438 of 794 rej09b0237-0500 the receive margin in asynchron ous mode can therefore be expres sed as shown in equation 1. equation 1: m = (0.5 - ) = (l - 0.5) f - (1+f) 100 % 1 2n d - 0.5 n where: m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation 1, if f = 0 and d = 0.5, the receive margin is 46.875%, as given by equation 2. equation 2: when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. 6. prohibited multiple pin allocation for channel 1 although signals sck1, rxd1, and txd1 can be respectively assigned to multiple pins of pd4 or pe20, pd3 or pe19, and pd2 or pe18, either of them must be selected. for example, if signal sck1 is assigned to both pins pd4 and pe20, correct operation of the scif is not guaranteed. 7. status of the txd and rts pins when the te bit is cleared the txdi (i = 0, 1, 2) and rtsj (j = 0, 1) pins usually function as output pins during serial communication. however, even if these functions are selected by the pin function controller (pfc), the internal weak keeper drives the pins to unstable levels as long as the te bit in scscri (i = 0, 1, 2) is cleared. to make these pins always function as output pins (regardless of the value of the te bit), set scsptri (i = 0, 1, 2) and pfc in the following order. a. set the spbio and spbdt bits in scsptri (i = 0, 1, 2). set the rtsio and rtsdt bits in scsptrj (j = 0, 1). b. select the txdi (i = 0, 1, 2) and rtsj (j = 0, 1) pins with the pfc. 8. interval from when the te bit in scscr is set to 1 until a start bit is transmitted in asynchronous mode in the scif included in former products, a start bit is transmitted after the internal equivalent to one frame. in the scif included in this produc t, however, a start bit is transmitted directly after the te bit is set to 1. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 439 of 794 rej09b0237-0500 9. clear timing of the fer or per bits when the dmac saves the receive data in asynchronous mode the fer or per bits in scfsr are set when data including a framing error or parity error is received in asynchronous mode, wh ereas cleared when the corres ponding data is read from scfrdr. therefore, when data w ith an error is received while the dmac is set to save the receive data automatically, the receive-error in terrupt is accepted after the dmac reads the corresponding data. as a result, the cpu cannot check the fer or per bits. to prevent this defect, the rtrg[1:0] bits in scfcr should be set to the higher number to delay the dmac call timing. this enables the cpu to check the fer or per bits in the receive-error interrupt routine, prior to the dmac to read the error data. section 15 serial communication interface with fifo (scif) rev. 5.00 mar. 15, 2007 page 440 of 794 rej09b0237-0500 section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 441 of 794 rej09b0237-0500 section 16 serial i/o with fifo (siof) this lsi includes a clock-synchronized serial i/o module with fifo (siof) that comprises one channel. the siof can perform serial communicatio n with a serial peripher al interface bus (spi). 16.1 features ? serial transfer ? 16-stage 32-bit fifos (independent transmission and reception) ? supports 8-bit data/16-bit data/16-bit stereo audio input and output ? msb first for data transmission ? supports a maximum of 48-khz sampling rate ? synchronization by either frame synchronization pulse or left/right channel switch ? supports codec control data interface ? connectable to linear, audio, or a-law or -law codec chip ? supports both master and slave modes ? serial clock ? an external pin input or internal clock (p ) can be selected as the clock source. ? interrupts: one type ? dma transfer ? supports dma transmission and reception by a transfer request for transmission and reception ? spi mode ? fixed master mode can perform the full-duplex communication with the spi slave devices continuously. ? selects the falling/rising edge of the sck as data sampling. ? selects the clock phase of the sck as a transmit timing. ? selects one slave device. ? the length of transmit/receive data is fixed to 8 bits. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 442 of 794 rej09b0237-0500 figure 16.1 shows a block diagram of the siof. p/s s/p p 1/nmclk siofmclk siofsck siofsync sioftxd siofrxd timing control siof interrupt request peripheral bus bus interface control registers transmit fifo (32 bits x16 stages) receive fifo (32 bits x16 stages) transmit control data receive control data baud rate generator figure 16.1 block diagram of siof section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 443 of 794 rej09b0237-0500 16.2 input/output pins the pin configuration in this module is shown in table 16.1. table 16.1 pin configuration channel pin name abbreviation * i/o function siof0_mclk siofmclk input master clock input siof0_sck (sck0) siofsck (sck) i/o serial clock (common to transmission/reception) in spi mode, fixed to output. siof0_sync ( ss00 ) siofsync ( ss0 ) i/o frame synchronous signal (common to transmission/reception) in spi mode, fixed to output, and selects slave device 0. siof0_txd (mosi0) sioftxd (mosi) output transmit data 0 siof0_rxd (miso0) siofrxd (miso) input receive data note: * the pins are abbreviated as siofmc lk, siofsck, siofsync, sioftxd, and siofrxd in the following descriptions. in spi mode, the pins are called sck, ss0 , mosi, and miso. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 444 of 794 rej09b0237-0500 16.3 register descriptions the siof has the following register s. for the addresses of these regi sters and the register states in each operating state, refer to secti on 24, list of registers. in the register descript ions following this section, channel numbers are omitted. channel 0: ? mode register_0 (simdr_0) ? control register_0 (sictr_0) ? transmit data register_0 (sitdr_0) ? receive data register_0 (sirdr_0) ? transmit control data register_0 (sitcr_0) ? receive control data register_0 (sircr_0) ? status register_0 (sistr_0) ? interrupt enable register_0 (siier_0) ? fifo control register_0 (sifctr_0) ? clock select register_0 (siscr_0) ? transmit data assign register_0 (sitdar_0) ? receive data assign re gister_0 (sirdar_0) ? control data assign register_0 (sicdar_0) ? spi control regist er_0 (spicr_0) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 445 of 794 rej09b0237-0500 16.3.1 mode re gister (simdr) simdr is a 16-bit readable/writable register that sets the siof operating mode. bit bit name initial value r/w description 15 14 trmd1 trmd0 1 0 r/w r/w transfer mode 1, 0 select transfer mode. for details, see table 16.2. 00: slave mode 1 01: slave mode 2 10: master mode 1 11: master mode 2 13 syncat 0 r/w siofsync pin valid timing indicates the position of the siofsync signal to be output as a synchronization pulse. 0: at the start-bit data of frame 1: at the last-bit data of slot 12 redg 0 r/w receive data sampling edge 0: the siofrxd signal is sa mpled at the falling edge of siofsck (the sioftxd signal is transmitted at the rising edge of siofsck.) 1: the siofrxd signal is samp led at the rising edge of siofsck (the sioftxd signal is transmitted at the falling edge of siofsck.) note: this bit is valid only in master mode. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 446 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 9 8 fl3 fl2 fl1 fl0 0 0 0 0 r/w r/w r/w r/w frame length 3 to 0 00xx: data length is 8 bits and frame length is 8 bits. 0100: data length is 8 bits and frame length is 16 bits. 0101: data length is 8 bits and frame length is 32 bits. 0110: data length is 8 bits and frame length is 64 bits. 0111: data length is 8 bits and frame length is 128 bits. 10xx: data length is 16 bits and frame length is 16 bits. 1100: data length is 16 bits and frame length is 32 bits. 1101: data length is 16 bits and frame length is 64 bits. 1110: data length is 16 bits and frame length is 128 bits. 1111: data length is 16 bits and frame length is 256 bits. note: when data length is specified as 8 bits, control data cannot be transmitted or received. x: don't care 7 txdiz 0 r/w sioftxd pin output when transmission is invalid * 0: high output (1 output) when invalid 1: high-impedance state when invalid note: invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 rcim 0 r/w receive control data interrupt mode 0: sets the rcrdy bit in sistr when the contents of sircr change. 1: sets the rcrdy bit in sistr each time when the sircr receives the control data. 5 syncac 0 r/w siofsync pin polarity valid when the siofsync signal is output as synchronous pulse in master mode. 0: active-high 1: active-low section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 447 of 794 rej09b0237-0500 bit bit name initial value r/w description 4 syncdl 0 r/w data pin bit delay for siofsync pin valid when the siofsync signal is output as synchronous pulse. only one-bit delay is valid for transmission in slave mode. 0: no bit delay 1: 1-bit delay 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. table 16.2 operation in each transfer mode transfer mode master/slave siofsync bit delay control data method * slave mode 1 slave synchronous pulse slot position slave mode 2 slave synchronous pulse secondary fs master mode 1 master synchronous pulse syncdl bit slot position master mode 2 master l/r no not supported note: * the control data method is valid only when t he fl3 to fl0 bits are specified as 1xxx. (x: don?t care.) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 448 of 794 rej09b0237-0500 16.3.2 control register (sictr) sictr is a 16-bit readable/writable register that sets the siof operating state. bit bit name initial value r/w description 15 scke 0 r/w serial clock output enable this bit is valid in master mode. 0: disables the siofsck output (outputs 0) 1: enables the siofsck output ? if this bit is set to 1, the siof initializes the baud rate generator and initiate s the operation. at the same time, the siof outputs the clock generated by the baud rate generator to the siofsck pin. this bit is initialized in module stop mode. 14 fse 0 r/w frame synchrono us signal output enable this bit is valid in master mode. 0: disables the siofsync output (outputs 0) 1: enables the siofsync output ? if this bit is set to 1, the siof initializes the frame counter and initiates the operation. this bit is initialized in module stop mode. 13 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 449 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 txe 0 r/w transmit enable 0: disables data transmission from the sioftxd pin 1: enables data transmission from the sioftxd pin ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal). ? when the 1 setting for this bit becomes valid, the siof issues a transmit transfer request according to the setting of the tfwm bit in sifctr. when transmit data is stored in the transmit fifo, transmission of data from the sioftxd pin begins. ? this bit is initialized upon a transmit reset. this bit is initialized in module stop mode. 8 rxe 0 r/w receive enable 0: disables data reception from siofrxd 1: enables data reception from siofrxd ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal). ? when the 1 setting for this bit becomes valid, the siof begins the recept ion of data from the siofrxd pin. when receiv e data is stored in the receive fifo, the siof issues a reception transfer request according to the setting of the rfwm bit in sifctr. ? this bit is initialized upon receive reset. this bit is initialized in module stop mode. 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 450 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 txrst 0 r/w transmit reset 0: does not reset transmit operation 1: resets transmit operation ? this bit setting becomes valid immediately. this bit should be cleared to 0 before setting the register to be initialized. ? when the 1 setting for this bit becomes valid, the siof immediately sets transmit data from the sioftxd pin to 1, and initializes the transmit data register and transmit-related status. the following are initialized. ? sitdr ? sitcr ? transmit fifo write pointer and read pointer ? tcrdy, tfemp, and tdreq bits in sistr ? txe bit 0 rxrst 0 r/w receive reset 0: does not reset receive operation 1: resets receive operation ? this bit setting becomes valid immediately. this bit should be cleared to 0 before setting the register to be initialized. ? when the 1 setting for this bit becomes valid, the siof immediately disables reception from the siofrxd pin, and initializes the receive data register and receive-related status. the following are initialized. ? sirdr ? sircr ? receive fifo write pointer and read pointer ? rcrdy, rfful, and rdreq bits in sistr ? rxe bit section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 451 of 794 rej09b0237-0500 16.3.3 transmit data register (sitdr) sitdr is a 32-bit write-only register th at specifies the siof transmit data. sitdr is initialized by the conditions specified in s ection 23, list of registers, or by a transmit reset caused by the txrst bit in sictr. sitdr is initialized in module stop mode. bit bit name initial value r/w description 31 to 16 sitdl 15 to 0 all 0 w left-channel transmit data specify data to be output from the sioftxd pin as left- channel data. the position of the left-channel data in the transmit frame is specified by the tdla bit in sitdar. ? these bits are valid only when the tdle bit in sitdar is set to 1. 15 to 0 sitdr 15 to 0 all 0 w right-channel transmit data specify data to be output fr om the sioftxd pin as right-channel data. the pos ition of the right-channel data in the transmit frame is specified by the tdra bit in sitdar. ? these bits are valid only when the tdre bit and tlrep bit in sitdar are set to 1 and cleared to 0, respectively. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 452 of 794 rej09b0237-0500 16.3.4 receive data register (sirdr) sirdr is a 32-bit read-only register that reads recei ve data of the siof. si rdr stores data in the receive fifo and is initialized by the conditions specified in section 23, list of registers, or by a receive reset caused by the rxrst bit in sictr. bit bit name initial value r/w description 31 to 16 sirdl 15 to 0 all 0 r left-channel receive data store data received from the siofrxd pin as left- channel data. the position of the left-channel data in the receive frame is specified by the rdla bit in sirdar. ? these bits are valid only when the rdle bit in sirdar is set to 1. 15 to 0 sirdr 15 to 0 all 0 r right-channel receive data store data received from t he siofrxd pin as right- channel data. the position of the right-channel data in the receive frame is specified by the rdra bit in sirdar. ? these bits are valid only when the rdre bit in sirdar is set to 1. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 453 of 794 rej09b0237-0500 16.3.5 transmit control data register (sitcr) sitcr is a 32-bit readable/writable register that specifies transmit control data of the siof. sitcr can be specified only when the fl3 to fl0 bits in simdr are specif ied as 1xxx (x: don't care.). sitcr is initialized in module stop mode. bit bit name initial value r/w description 31 to 16 sitc0 15 to 0 all 0 r/w control channel 0 transmit data specify data to be output fr om the sioftxd pin as control channel 0 transmit data. the position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sitc1 15 to 0 all 0 r/w control channel 1 transmit data specify data to be output fr om the sioftxd pin as control channel 1 transmit data. the position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 454 of 794 rej09b0237-0500 16.3.6 receive control data register (sircr) sircr is a 32-bit readable/writable register that stores receive control data of the siof. sircr can be specified only when the fl3 to fl0 bits in simdr are specified as 1xxx (x: don't care.). bit bit name initial value r/w description 31 to 16 sirc0 15 to 0 all 0 r control channel 0 receive data store data received from t he siofrxd pin as control channel 0 receive data. t he position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sirc1 15 to 0 all 0 r control channel 1 receive data store data received from t he siofrxd pin as control channel 1 receive data. t he position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 455 of 794 rej09b0237-0500 16.3.7 status register (sistr) sistr is a 16-bit read-only register that shows the si of state. each bit in this register becomes an siof interrupt source when the corresponding bit in siier is set to 1. sistr is initialized in module stop mode. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 tcrdy 0 r transmit control data ready 0: indicates that a write to sitcr is disabled 1: indicates that a write to sitcr is enabled ? if sitcr is written when this bit is cleared to 0, sitcr is over-written and the prev ious contents of sitcr are not output from the sioftxd pin. ? this bit is valid when the txe bit in sitcr is set to 1. ? this bit indicates a state of the siof. if sitcr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 13 tfemp 0 r transmit fifo empty 0: indicates that transmit fifo is not empty 1: indicates that transmit fifo is empty ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if sitdr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 456 of 794 rej09b0237-0500 bit bit name initial value r/w description 12 tdreq 0 r transmit data transfer request 0: indicates that the size of empty space in the transmit fifo does not exceed the size specified by the tfwm bit in sifctr. 1: indicates that the size of empty space in the transmit fifo exceeds the size specified by the tfwm bit in sifctr. a transmit data transfer request is issued when the empty space in the transmit fifo e xceeds the size specified by the tfwm bit in sifctr. when using transmit data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if the size of empty space in the transmit fifo is less than the size specified by the tfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 rcrdy 0 r receive control data ready 0: indicates that the sircr stores no valid data. 1: indicates that the sircr stores valid data. ? if sircr is written when this bit is set to 1, sircr is modified by the latest data. ? this bit is valid when the rxe bit in sictr is set to 1. ? this bit indicates a state of the siof. if sircr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 457 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 rfful 0 r receive fifo full 0: receive fifo not full 1: receive fifo full ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if sirdr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 8 rdreq 0 r receive data transfer request 0: indicates that the size of valid space in the receive fifo does not exceed the si ze specified by the rfwm bit in sifctr. 1: indicates that the size of valid space in the receive fifo exceeds the size specified by the rfwm bit in sifctr. a receive data transfer request is issued when the valid space in the receive fifo e xceeds the size specified by the rfwm bit in sifctr. when using receive data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if the size of valid space in the receive fifo is less than the size specified by the rfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 458 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 saerr 0 r/w slot assign error 0: indicates that no slot assign error occurs 1: indicates that a slot assign error occurs a slot assign error occurs when the specifications in sitdar, sirdar, and sicdar overlap. if a slot assign error occurs, the siof does not transmit data to the sioftxd pin and does not receive data from the siofrxd pin. note that the siof does not clear the txe bit or rxe bit in sictr at a slot assign error. ? this bit is valid when the txe bit or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 4 fserr 0 r/w frame synchronization error 0: indicates that no frame synchronization error occurs 1: indicates that a frame synchronization error occurs a frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. if a frame synchronization error occurs, the siof performs transmission or reception for slots that can be transferred. ? this bit is valid when the txe or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 459 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 tfovf 0 r/w transmit fifo overflow 0: no transmit fifo overflow 1: transmit fifo overflow a transmit fifo overflow means that there has been an attempt to write to sitdr w hen the transmit fifo is full. when a transmit fifo overflow occurs, the siof indicates overflow, and writing is invalid. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 2 tfudf 0 r/w transmit fifo underflow 0: no transmit fifo underflow 1: transmit fifo underflow a transmit fifo underflow means that loading for transmission has occurred when the transmit fifo is empty. when a transmit fifo underflow occurs, the siof repeatedly sends the previous transmit data. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 460 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 rfudf 0 r/w receive fifo underflow 0: no receive fifo underflow 1: receive fifo underflow a receive fifo underflow means that reading of sirdr has occurred when the receive fifo is empty. when a receive fifo underflow occurs, the value of data read from sirdr is not guaranteed. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 0 rfovf 0 r/w receive fifo overflow 0: no receive fifo overflow 1: receive fifo overflow a receive fifo overflow means that writing has occurred when the receive fifo is full. when a receive fifo overflow occurs, the siof indicates overflow, and receive data is lost. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 461 of 794 rej09b0237-0500 16.3.8 interrupt enab le register (siier) siier is a 16-bit readable/writable register that enables the issue of siof interrupts. when each bit in this register is set to 1 and the correspondi ng bit in sistr is set to 1, the siof issues an interrupt. bit bit name initial value r/w description 15 tdmae 0 r/w transmit data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the tdreqe bit can be set as transmit interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac 14 tcrdye 0 r/w transmit control data ready enable 0: disables interrupts due to transmit control data ready 1: enables interrupts due to transmit control data ready 13 tfempe 0 r/w transmit fifo empty enable 0: disables interrupts due to transmit fifo empty 1: enables interrupts due to transmit fifo empty 12 tdreqe 0 r/w transmit data transfer request enable 0: disables interrupts due to transmit data transfer requests 1: enables interrupts due to transmit data transfer requests 11 rdmae 0 r/w receive data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the rdreqe bit can be set as receive interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac 10 rcrdye 0 r/w receive control data ready enable 0: disables interrupts due to receive control data ready 1: enables interrupts due to receive control data ready section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 462 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 rffule 0 r/w receive fifo full enable 0: disables interrupts due to receive fifo full 1: enables interrupts due to receive fifo full 8 rdreqe 0 r/w receive data transfer request enable 0: disables interrupts due to receive data transfer requests 1: enables interrupts due to receive data transfer requests 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 saerre 0 r/w slot assign error enable 0: disables interrupts due to slot assign error 1: enables interrupts due to slot assign error 4 fserre 0 r/w frame synchronization error enable 0: disables interrupts due to frame synchronization error 1: enables interrupts due to frame synchronization error 3 tfovfe 0 r/w transmit fifo overflow enable 0: disables interrupts due to transmit fifo overflow 1: enables interrupts due to transmit fifo overflow 2 tfudfe 0 r/w transmit fifo underflow enable 0: disables interrupts due to transmit fifo underflow 1: enables interrupts due to transmit fifo underflow 1 rfudfe 0 r/w receive fifo underflow enable 0: disables interrupts due to receive fifo underflow 1: enables interrupts due to receive fifo underflow 0 rfovfe 0 r/w receive fifo overflow enable 0: disables interrupts due to receive fifo overflow 1: enables interrupts due to receive fifo overflow section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 463 of 794 rej09b0237-0500 16.3.9 fifo control register (sifctr) sifctr is a 16-bit readable/writable register that indicates the area available for the transmit/receive fifo transfer. bit bit name initial value r/w description 15 14 13 tfwm2 tfwm1 tfwm0 0 0 0 r/w r/w r/w transmit fifo watermark 000: issue a transfer request when 16 stages of the transmit fifo are empty. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 12 or more stages of the transmit fifo are empty. 101: issue a transfer request when 8 or more stages of the transmit fifo are empty. 110: issue a transfer request when 4 or more stages of the transmit fifo are empty. 111: issue a transfer request when 1 or more stages of transmit fifo are empty. ? a transfer request to the transmit fifo is issued by the tdreqe bit in sistr. ? the transmit fifo is always used as 16 stages of the fifo regardless of these bit settings. 12 11 10 9 8 tfua4 tfua3 tfua2 tfua1 tfua0 1 0 0 0 0 r r r r r transmit fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as b'00000 (full) to b'10000 (empty). section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 464 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 6 5 rfwm2 rfwm1 rfwm0 0 0 0 r/w r/w r/w receive fifo watermark 000: issue a transfer request when 1 stage or more of the receive fifo are valid. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 4 or more stages of the receive fifo are valid. 101: issue a transfer request when 8 or more stages of the receive fifo are valid. 110: issue a transfer request when 12 or more stages of the receive fifo are valid. 111: issue a transfer request when 16 stages of the receive fifo are valid. ? a transfer request to the receive fifo is issued by the rdreqe bit in sistr. ? the receive fifo is always used as 16 stages of the fifo regardless of these bit settings. 4 3 2 1 0 rfua4 rfua3 rfua2 rfua1 rfua0 0 0 0 0 0 r r r r r receive fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as b'00000 (empty) to b'10000 (full). section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 465 of 794 rej09b0237-0500 16.3.10 clock select register (siscr) siscr is a 16-bit readable/writable register that se ts the serial clock generation conditions for the master clock. siscr can be specified when th e trmd1 and trmd0 bits in simdr are specified as b'10 or b'11. bit bit name initial value r/w description 15 mssel 1 r/w master clock source selection 0: uses the input signal of the siofmclk pin as the master clock 1: uses p as the master clock the master clock is the clock input to the baud rate generator. 14 msimm 1 r/w master clock direct selection 0: uses the output clock of the baud rate generator as the serial clock 1: uses the master clock itself as the serial clock 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 11 10 9 8 brps4 brps3 brps2 brps1 brps0 0 0 0 0 0 r/w r/w r/w r/w r/w prescalar setting set the master clock division ratio according to the count value of the prescalar of the baud rate generator. the range of settings is from b'00000 ( 1/1) to b'11111 ( 1/32). 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 466 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 1 0 brdv2 brdv1 brdv0 0 0 0 r/w r/w r/w baud rate generator?s division ratio setting set the frequency division ratio for the output stage of the baud rate generator. 000: prescalar output 1/2 001: prescalar output 1/4 010: prescalar output 1/8 011: prescalar output 1/16 100: prescalar output 1/32 101: setting prohibited 110: setting prohibited 111: prescalar output 1/1 * the final frequency division ratio of the baud rate generator is determined by brps brdv (maximum 1/1024). note: * this setting is valid on ly when the brps4 to brps0 bits are set to b'00000. 16.3.11 transmit data a ssign register (sitdar) sitdar is a 16-bit readable/writable register that specifies the position of the transmit data in a frame (slot number). bit bit name initial value r/w description 15 tdle 0 r/w transmit left-channel data enable 0: disables left-channel data transmission 1: enables left-channel data transmission 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 467 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 9 8 tdla3 tdla2 tdla1 tdla0 0 0 0 0 r/w r/w r/w r/w transmit left-channel data assigns 3 to 0 specify the position of left-channel data in a transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the left channel is specified in the sitdl bit in sitdr. 7 tdre 0 r/w transmit right-channel data enable 0: disables right-channel data transmission 1: enables right-channel data transmission 6 tlrep 0 r/w transmit left-channel repeat 0: transmits data specified in the sitdr bit in sitdr as right-channel data 1: repeatedly transmits data s pecified in the sitdl bit in sitdr as right-channel data ? this bit setting is valid when the tdre bit is set to 1. ? when this bit is set to 1, the sitdr settings are ignored. 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 tdra3 tdra2 tdra1 tdra0 0 0 0 0 r/w r/w r/w r/w transmit right-channel data assigns 3 to 0 specify the position of right-channel data in a transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the right channel is specified in the sitdr bit in sitdr. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 468 of 794 rej09b0237-0500 16.3.12 receive data a ssign register (sirdar) sirdar is a 16-bit readable/writable register that specifies the position of the receive data in a frame (slot number). bit bit name initial value r/w description 15 rdle 0 r/w receive left-channel data enable 0: disables left-channel data reception 1: enables left-channel data reception 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 rdla3 rdla2 rdla1 rdla0 0 0 0 0 r/w r/w r/w r/w receive left-channel data assigns 3 to 0 specify the position of left-channel data in a receive frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? receive data for the left channel is stored in the sirdl bit in sirdr. 7 rdre 0 r/w receive right-channel data enable 0: disables right-channel data reception 1: enables right-channel data reception 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 rdra3 rdra2 rdra1 rdra0 0 0 0 0 r/w r/w r/w r/w receive right-channel data assigns 3 to 0 specify the position of right-channel data in a receive frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? receive data for the right channel is stored in the sirdr bit in sirdr. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 469 of 794 rej09b0237-0500 16.3.13 control data assign register (sicdar) sicdar is a 16-bit readable/writable register that specifies the position of the control data in a frame (slot number). sicdar can be specified only when the fl bit in simdr is specified as 1xxx (x: don't care.). bit bit name initial value r/w description 15 cd0e 0 r/w control channel 0 data enable 0: disables transmission and reception of control channel 0 data 1: enables transmission and reception of control channel 0 data 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 cd0a3 cd0a2 cd0a1 cd0a0 0 0 0 0 r/w r/w r/w r/w control channel 0 data assigns 3 to 0 specify the position of control channel 0 data in a receive or transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the control channel 0 data is specified in the sitd0 bit in sitcr. ? receive data for the control channel 0 data is stored in the sird0 bit in sircr. 7 cd1e 0 r/w control channel 1 data enable 0: disables transmission and reception of control channel 1 data 1: enables transmission and reception of control channel 1 data 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 470 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 2 1 0 cd1a3 cd1a2 cd1a1 cd1a0 0 0 0 0 r/w r/w r/w r/w control channel 1 data assigns 3 to 0 specify the position of control channel 1 data in a receive or transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the control channel 1 data is specified in the sitd1 bit in sitcr. ? receive data for the control channel 1 data is stored in the sird1 bit in sircr. 16.3.14 spi control register (spicr) spicr is a 16-bit readable/writable register th at specifies the operat ing mode of the spi. bit bit name initial value r/w description 15 spim 0 r/w spi mode selects the siof operating mode. 0: operates as the siof. 1: the siof operates in master mode of the spi. 14 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 13 cpha 0 r/w spi clock phase selects the spi clock phase. 0: samples data at the first edge of the sck. 1: samples data at the second edge of the sck. 12 cpol 0 r/w spi clock polarity selects the spi clock polarity. 0: the sck is high-active, and goes low in the idle state. 1: the sck is low-active, and goes high in the idle state. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 471 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 ss0e 0 r/w slave device 0 ( ss0 ) enable 0: not select slave device 0. 1: selects slave device 0. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. setting of ss assert set the setup timing of the ss for the sck. ? cpha = 0 (unit: sck clock) ssast[1:0] ss setup ss hold 00 0.5 clock 0 clock 01 1 clock 0.5 clock 10 1.5 clock 1 clock 11 2 clock 1.5 clock ? cpha = 1 (unit: sck clock) ssast[1:0] ss setup ss hold 00 0 clock 0.5 clock 01 0.5 clock 1 clock 10 1 clock 1.5 clock 11 1.5 clock 2 clock 5 4 ssast1 ssast0 0 0 r/w r/w 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 472 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 fld1 fld0 0 0 r/w r/w frame delay specify the minimum time of the idle state between frames in terms of the clock number of the sck. 00: not delay. the continuous communication of the spi is performed when the ss pin asserts low continuously. 01: delay for 1 clock of the sck. 10: delay for 2 clocks of the sck. 11: delay for 3 clocks of the sck. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 473 of 794 rej09b0237-0500 16.4 operation 16.4.1 serial clocks master/slave modes: the following two modes are avai lable as the siof clock mode. ? slave mode: siofsck, siofsync input ? master mode: siofsck, siofsync output baud rate generator: in siof master mode, the baud rate generator (brg) is used to generate the serial clock. the division ratio is from 1/1 to 1/1024. figure 16.2 shows connections for supply of the serial clock. brg mclk 1/1 to 1/1024 mclk scke siofsck siofmclk p timing control master figure 16.2 serial clock supply table 16.3 shows an example of serial clock frequency. table 16.3 siof serial clock frequency sampling rate frame length 8 khz 44.1 khz 48 khz 32 bits 256 khz 1.4112 mhz 1.536 mhz 64 bits 512 khz 2.8224 mhz 3.072 mhz 128 bits 1.024 mhz 5.6448 mhz 6.144 mhz 256 bits 2.048 mhz 11.289 mhz 12.289 mhz section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 474 of 794 rej09b0237-0500 16.4.2 serial timing siofsync: the siofsync is a frame synchronous sign al. depending on the transfer mode, it has the following functions. ? synchronous pulse: 1-bit-width pulse indicating the start of the frame ? l/r: 1/2-frame-width pulse indicating the left-channel stereo data (l) in high level and the right-channel stereo data (r) in low level figure 16.3 shows the siofsync synchronization timing. siofsck siofrxd sioftxd siofsync siofsck siofrxd sioftxd siofsync (a) synchronous pulse (b) l/r 1 frame 1 frame start bit data 1-bit delay start bit of left channel data (1/2 frame length) start bit of right channel data (1/2 frame length) no delay figure 16.3 serial data synchronization timing section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 475 of 794 rej09b0237-0500 transmit/receive timing: the sioftxd transmit timing and si ofrxd receive timing relative to the siofsck can be set as the sampling timing in the follow ing ways. the transmit/receive timing is set using the redg bit in simdr. ? falling-edge sampling ? rising-edge sampling figure 16.4 shows the transmit/receive timing. siofsck siofsync sioftxd siofrxd siofsck siofsync sioftxd siofrxd (a) falling-edge sampling (a) rising-edge sampling receive timing transmit timing receive timing transmit timing figure 16.4 siof transmit/receive timing 16.4.3 transfer data format the siof performs the following transfer. ? transmit/receive data: transfer of 8-b it data/16-bit data/1 6-bit stereo data ? control data: transfer of 16-bit data (u ses the specific register as interface) transfer mode: the siof supports the following four tran sfer modes as listed in table 16.4. the transfer mode can be specified by the trmd1 and trmd0 bits in simdr. table 16.4 serial transfer modes transfer mode siofsync bit delay control data slave mode 1 synchronous pulse slot position slave mode 2 synchronous pulse secondary fs master mode 1 synchronous pulse syncdl bit slot position master mode 2 l/r no not supported section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 476 of 794 rej09b0237-0500 frame length: the length of the frame to be transferred by the siof is specified by the fl3 to fl0 bits in simdr. table 16.5 shows the relationship between the fl3 to fl0 bit settings and frame length. table 16.5 frame length fl3 to fl0 slot length number of bits in a frame transfer data 00xx 8 8 8-bit monaural data 0100 8 16 8-bit monaural data 0101 8 32 8-bit monaural data 0110 8 64 8-bit monaural data 0111 8 128 8-bit monaural data 10xx 16 16 16-bit monaural data 1100 16 32 16-bit monaural/stereo data 1101 16 64 16-bit monaural/stereo data 1110 16 128 16-bit monaural/stereo data 1111 16 256 16-bit monaural/stereo data note: x: don't care. slot position: the siof can specify the posi tion of transmit data, receive data, and control data in a frame (common to transmission and reception) by sl ot numbers. the slot number of each data is specified by the following registers. ? transmit data: sitdar ? receive data: sirdar ? control data: sicdar only 16-bit data is valid for control data. in additio n, control data is always assigned to the same slot number both in tran smission and reception. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 477 of 794 rej09b0237-0500 16.4.4 register allocation of transfer data transmit/receive data: writing and reading of transmit/r eceive data is performed for the following registers. ? transmit data writing : sitdr (32-bit access) ? receive data reading: sirdr (32-bit access) figure 16.5 shows the transmit/receive data and the sitdr and si rdr bit alignment. 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 l-channel data r-channel data (a) 16-bit stereo data data data data (b) 16-bit monaural data (c) 8-bit monaural data (d) 16-bit stereo data (left and right same audio output) data figure 16.5 transmit/receive data bit alignment note: in the figure, only the sh aded areas are transmitted or received as valid data. data in unshaded areas is not tr ansmitted or received. monaural or stereo can be specified for transmit data by the tdle bit and tdre bit in sitdar. monaural or stereo can be specified for receive data by the rdle bit an d rdre bit in sirdar. to achieve left and right same audio output while stereo is specified for tr ansmit data, specify the tlrep bit in sitdar. tables 16.6 and 16.7 show the audio mode specification for transmit data and that for receive data, respectively. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 478 of 794 rej09b0237-0500 table 16.6 audio mode specifi cation for transmit data bit mode tdle tdre tlrep monaural 1 0 x stereo 1 1 0 left and right same audio output 1 1 1 note: x: don't care table 16.7 audio mode speci fication for receive data bit mode rdle rdre monaural 1 0 stereo 1 1 note: left and right same audio mode is not supported in receive data. to execute 8-bit monaural transmission or reception, use the left channel. control data: control data is written to or read from by the following registers. ? transmit control data wr ite: sitcr (32-bit access) ? receive control data read: sircr (32-bit access) figure 16.6 shows the control data and bit alignment in sitcr and sircr. 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 (a) control data: one channel (b) control data: two channels control data (channel 0) control data (channel 0) control data (channel 1) figure 16.6 control data bit alignment section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 479 of 794 rej09b0237-0500 the number of channels in control data is specified by the cd0e and cd1e bits in sicdar. table 16.8 shows the relationship between the number of channels in control data and bit settings. table 16.8 setting number of channels in control data bit number of channels cd0e cd1e 1 1 0 2 1 1 note: to use only one channel in control data, use channel 0. 16.4.5 control data interface control data performs control command output to the codec and status input from the codec. the siof supports the following tw o control data interface methods. ? control by slot position ? control by secondary fs control data is valid only when data length is specified as 16 bits. control by slot position (mas ter mode 1, slave mode 1): control data is transferred for all frames transmitted or received by the siof by speci fying the slot position of control data. this method can be used in both siof master and slave modes. figure 16.7 shows an example of the control data interface timing by slot position control. siofsck siofrxd sioftxd siofsync l-channel data r-channel data specifications: trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0001, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0010, rdra[3:0]=0010, cd1a[3:0]=0011 control channel 0 control channel 1 1 frame slot no.0 slot no.1 slot no.2 slot no.3 figure 16.7 control data interface (slot position) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 480 of 794 rej09b0237-0500 control by secondary fs (slave mode 2): the codec normally outputs the siofsync signal as synchronization pulse (fs). in this method, the codec outputs the secondary fs specific to the control data transfer after 1/2 frame time has been passed (not the normal fs output timing) to transmit or receive control data. this method is valid for siof slave mode. the following summarizes the control data interf ace procedure by the secondary fs. ? transmit normal transmit data of lsb = 0 (the siof forcibly clears 0). ? to execute control data transmission, send transmit data of lsb = 1 (the siof forcibly set to 1 by writing sitcdr). ? the codec outputs the secondary fs. ? the siof transmits or receives (stores in sircd r) control data (data specified by sitcdr) synchronously with the secondary fs. figure 16.8 shows an example of the contro l data interface timing by the secondary fs. siofsck siofrxd sioftxd siofsync l-channel data specifications: trmd[1:0]=01, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1110 (frame length: 128 bits), tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 lsb=1 (secondary fs request) 1 frame 1/2 frame 1/2 frame normal fs normal fs secondary fs control channel 0 slot no.0 slot no.0 figure 16.8 control data interface (secondary fs) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 481 of 794 rej09b0237-0500 16.4.6 fifo overview: the transmit and receive fi fos of the siof have the following features. ? 16-stage 32-bit fifos for transmission and reception ? the fifo pointer can be updated in one read or write cycle re gardless of access size of the cpu and dmac. (one-stage 32-bit fifo access cannot be divided into multiple accesses.) transfer request: the transfer request of the fifo can be issued to the cpu or dmac as the following interrupt sources. ? fifo transmit request: tdreq (transmit interrupt source) ? fifo receive request: rdreq (receive interrupt source) the request conditions for fifo transmit or receive can be speci fied individuall y. the request conditions for the fifo transmit and receive are specified by the tfwm 2 to tfwm0 bits and rfwm2 to rfwm0 bits in sifctr, respecti vely. tables 16.9 and 16.10 summarize the conditions specified by sifctr. table 16.9 conditions to issue transmit request tfwm2 to tfwm0 number of requested stages transmit request used areas 000 1 empty area is 16 stages 100 4 empty area is 12 stages or more 101 8 empty area is 8 stages or more 110 12 empty area is 4 stages or more smallest 111 16 empty area is 1 stage or more largest table 16.10 conditions to issue receive request rfwm2 to rfwm0 number of requested stages receive request used areas 000 1 valid data is 1 stage or more 100 4 valid data is 4 stages or more 101 8 valid data is 8 stages or more 110 12 valid data is 12 stages or more smallest 111 16 valid data is 16 stages largest section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 482 of 794 rej09b0237-0500 the number of stages of the fifo is always sixteen even if the data area or empty area exceeds the fifo size (the number of fifos). accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen fi fo stages. the fifo transmit or receive request is canceled when the above condition is not satisfied even if the fifo is not empty or full. number of fifos: the number of fifo stages used in transmission and reception is indicated by the following register. ? transmit fifo: the number of empty fifo stages is indicat ed by the tfua4 to tfua0 bits in sifctr. ? receive fifo: the number of valid data stages is indicated by the rfua4 to rfua0 bits in sifctr. the above indicate possible data numbers that can be transferred by the cpu or dmac. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 483 of 794 rej09b0237-0500 16.4.7 transmit and receive procedures transmission in master mode: figure 16.9 shows an example of settings and operation for master mode transmission. start no ye s no ye s end no. 1 2 3 4 5 6 7 8 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the scke bit in sictr to 1 start siofsck output set the fse and txe bits in sictr to 1 tdreq = 1? set sitdr transmit sitdr from sioftxd synchronously with siofsync transfer ended? clear the txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set operation start for baud rate generator set the start for frame synchronous signal output and enable transmission set transmit data set to disable transmission output serial clock output frame synchronous signal and issue transmit transfer request * transmit end transmission flow chart siof settings siof operation note: * when interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the txe bit should be set to 1. figure 16.9 example of transmit operation in master mode section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 484 of 794 rej09b0237-0500 reception in master mode: figure 16.10 shows an example of settings and operation for master mode reception. start no ye s no ye s end no. 1 2 3 4 5 6 7 8 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the scke bit in sictr to 1 start siofsck output set the fse and rxe bits in sictr to 1 rdreq = 1? transfer ended? clear the rxe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set operation start for baud rate generator output serial clock flow chart siof settings siof operation set the start for frame synchronous signal output and enable reception issue receive transfer request according to the receive fifo threshold value reception end reception output frame synchronous signal read receive data set to disable reception read sirdr store siofrxd receive data in sirdr synchronously with siofsync figure 16.10 example of recei ve operation in master mode section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 485 of 794 rej09b0237-0500 transmission in slave mode: figure 16.11 shows an example of settings and oper ation for slave mode transmission. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the txe bit in sictr to 1 tdreq = 1? set sitdr transmit sitdr from sioftxd synchronously with siofsync transfer ended? clear the txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set transmit data set to disable transmission issue transmit transfer request to enable transmission when frame synchronous signal is input transmit end transmission flow chart siof settings siof operation set to enable transmission figure 16.11 example of transmit operation in slave mode section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 486 of 794 rej09b0237-0500 reception in slave mode: figure 16.12 shows an example of settings and operation for slave mode reception. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the rxe bit in sictr to 1 rdreq = 1? transfer ended? clear the rxe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value flow chart siof settings siof operation issue receive transfer request according to the receive fifo threshold value reception end reception read receive data set to disable reception read sirdr store siofrxd receive data in sirdr synchronously with siofsync set to enable reception enable reception when the frame synchronous signal is input figure 16.12 example of recei ve operation in slave mode section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 487 of 794 rej09b0237-0500 transmit/receive reset: the siof can separately reset the tr ansmit and receive units by setting the following bits to 1. ? transmit reset: txrst bit in sictr ? receive reset: rxrst bit in sictr table 16.11 shows the details of initializa tion upon transmit or receive reset. table 16.11 transmit and receive reset type objects initialized transmit reset sitdr transmit fifo write pointer and read pointer tcrdy, tfemp, and tdreq bits in sistr txe bit in sictr receive reset sirdr receive fifo write pointer and read pointer rcrdy, rfful, and rdreq bits in sistr rxe bit in sictr module stop mode: the siof stops the transmit/receive opera tion in module stop mode. and all the registers in siof are retained. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 488 of 794 rej09b0237-0500 16.4.8 interrupts the siof has one type of interrupt. interrupt sources: interrupts can be issued by several sour ces. each source is shown as an siof status in sistr. table 16.12 lists the siof interrupt sources. table 16.12 siof interrupt sources no. classification bit name function name description 1 tdreq transmit fifo transfer request the transmit fifo stores data of specified size or more. 2 transmission tfemp transmit fifo empty the transmit fifo is empty. 3 rdreq receive fifo transfer request the receive fifo stores data of specified size or more. 4 reception rfful receive fifo full the receive fifo is full. 5 tcrdy transmit control data ready the transmit control register is ready to be written. 6 control rcrdy receive control data ready the receive control data register stores valid data. 7 tfudf transmit fifo underflow serial data transmit timing has arrived while the transmit fifo is empty. 8 tfovf transmit fifo overflow write to the transmit fifo is performed while the transmit fifo is full. 9 rfovf receive fifo overflow serial data is received while the receive fifo is full. 10 rfudf receive fifo underflow the receive fifo is read while the receive fifo is empty. 11 fserr fs error a synchronous signal is input before the specified bit number has been passed (in slave mode). 12 error saerr assign error the same slot is specified in both serial data and control data. whether an interrupt is issued or not as the resu lt of an interrupt source is determined by the siier settings. if an interrupt source is set to 1 an d the corresponding bit in siier is set to 1, an siof interrupt is issued. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 489 of 794 rej09b0237-0500 regarding transmit and receive classification: the transmit sources an d receive sources are signals indicating the state; after being set, if th e state changes, they are automatically cleared by the siof. when the dma transfer is used, a dma transfer re quest is pulled low (0 level) for one cycle at the end of dma transfer. processing when errors occur: on occurrence of each of the erro rs indicated as a status in sistr, the siof performs the following operations. ? transmit fifo underflow (tfudf) the immediately preceding transm it data is again transmitted. ? transmit fifo overflow (tfovf) the contents of the transmit fi fo are protected, and the write operation causing the overflow is ignored. ? receive fifo ove rflow (rfovf) data causing the overflow is discarded and lost. ? receive fifo underflow (rfudf) an undefined value is output on the bus. ? fs error (fserr) the internal counter is reset according to the fsyn signal in which an error occurs. ? assign error (saerr) ? if the same slot is assigned to both serial data and control data, the slot is assigned to serial data. ? if the same slot is assigned to two control data items, data cannot be transferred correctly. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 490 of 794 rej09b0237-0500 16.4.9 transmit a nd receive timing examples of the siof se rial transmission and reception are shown in figures 16.13 to 16.19. 8-bit monaural data (1): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, an frame length = 8 bits siofsck siofrxd sioftxd siofsync l-channel data slot no.0 trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=0000 (frame length: 8 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 specifications: 1 frame 1-bit delay figure 16.13 transmit and receive timing (8-bit monaural data (1)) 8-bit monaural data (2): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, and frame length = 16 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=0100 (frame length: 16 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 slot no.0 slot no.1 specifications: 1 frame 1-bit delay figure 16.14 transmit and receive timing (8-bit monaural data (2)) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 491 of 794 rej09b0237-0500 16-bit monaural data (1): synchronous pulse method, falling edge sampling, slot no.0 used for transmit and receive data, and frame length = 64 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1101 (frame length: 64 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame 1-bit delay figure 16.15 transmit and receive timing (16-bit monaural data (1)) 16-bit stereo data (1): l/r method, rising edge sampling, slot no.0 used for left channel data, slot no.1 used for right channel data, and frame length = 32 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=11, tdle=1, rdle=1, cd0e=0, redg=1, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1100 (frame length: 32 bits) tdre=1, rdre=1, cd1e=0, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0000 r-channel data slot no.0 slot no.1 specifications: 1 frame no bit delay figure 16.16 transmit and receive timing (16-bit stereo data (1)) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 492 of 794 rej09b0237-0500 16-bit stereo data (2): l/r method, rising edge sampling, slot no.0 used for left-channel transmit data, slot no.1 used fo r left-channel receive data, slot no.2 used for right-channel transmit data, slot no.3 used for right-channel receive data, and frame length = 64 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=01, tdle=1, rdle=1, cd0e=0, redg=1, tdla[3:0]=0000, rdla[3:0]=0001, cd0a[3:0]=0000, fl[3:0]=1101 (frame length: 64 bits), tdre=1, rdre=1, cd1e=0, tdra[3:0]=0010, rdra[3:0]=0011, cd1a[3:0]=0000 l-channel data r-channel data l-channel data r-channel data slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame no bit delay figure 16.17 transmit and receive timing (16-bit stereo data (2)) 16-bit stereo data (3): synchronous pulse method, falling edge sampling, slot no.0 used for left- channel data, slot no.1 used for right-channel data, slot no.2 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0010, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 16.18 transmit and receive timing (16-bit stereo data (3)) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 493 of 794 rej09b0237-0500 16-bit stereo data (4): synchronous pulse method, falling edge sampling, slot no.0 used for left- channel data, slot no.2 used for right-channel data, slot no.1 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=1, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0001, fl[3:0]=1110 (frame length: 128 bits) tdre=1, rdre=1, cd1e=1, tdra[3:0]=0010, rdra[3:0]=0010, cd1a[3:0]=0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 16.19 transmit and receive timing (16-bit stereo data (4)) synchronization-pulse output mode at end of each slot (syncat bit = 1): synchronous pulse method, falling edge sampling, slot no.0 used for left-channel data, slot no.1 used for right- channel data, slot no.2 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits in this mode, valid data must be set to slot no. 0. siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0010, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0011 l-channel data r-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame figure 16.20 transmit and recei ve timing (16-bit stereo data) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 494 of 794 rej09b0237-0500 16.4.10 spi mode spi-mode operation is selected for the siof by the setting in spicr. example of configuration: figure 16.21 shows an example of the configuration for spi-mode communications. master spi baud rate generator p/s transmit fifo receive fifo mosi miso ss0 ss sck s/p slave 0 spi figure 16.21 example of configuration in spi mode spi operation: the states of operation in spi mode are described in terms of transmission and reception in table 16.13. in spi mode, the data lengt h is fixed to 8 bits and the values of the upper 8 bits of sitdr and sirdr are the valid data fo r transmission and recepti on, respectively. fixed master mode can perform the full-duplex communi cation with the spi slav e devices continuously. that is, 8-bit data is continuou sly transmitted/received, and resetti ng of transmit/receive operation by the txrst or rxrst bit with sck = p controls the respective frames. sitdr/sirdr data the shaded part is the data which is transmitted or received. 31 0 24 23 section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 495 of 794 rej09b0237-0500 the only sources of interrupts that should be en abled in spi-mode transfer are transmit data transfer request (tdreq), tr ansmit fifo empty (tfemp), r eceive-data transfer request (rdreq), receive-fifo full (rfful), and r eceive-fifo overflow (rfovf). enabled or disabled states are selectable by the interrupt enab le register (siier). interrupts from other sources must be disabled at all times. for the dma transfer requests, the enabled so urces are transmit-data dma transfer request (tdma) and receive-data dma tr ansfer request (rdma). enable d or disabled states are selectable by the interrupt enable register (siier). in spi mode, the baud rate is set by siscr. table 16.13 states of transmit an d receive operations in spi mode txe rxe tdmae rdmae spi transmit/receive operation 0 0 don?t care don?t care transmission/reception is disabled 0 1 0 1 half-duplex reception the transmit fifo does not operate and dummy data is transmitted from the mosi. data received at the miso is stored in the receive fifo and is transferred by using the dma. receive operation continues as long as re bit = 1; the receive-fifo overflow (rfovf) status is set after the receive fifo has become full and further receive data is ignored. 1 0 0 0 half-duplex transmission the data in the transmit fifo is transmitted from the mosi. the receive fifo does not operate, and data on the miso is ignored. when the transmit fifo becomes empty, the transmit operation is completed. 1 0 half-duplex transmission the data which has been tran sferred by using the dma to the transmit fifo is transmitted from the mosi. the receive fifo does not operate and data on the miso is ignored. when the transmit fi fo becomes empty, the transmit operation is completed. section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 496 of 794 rej09b0237-0500 txe rxe tdmae rdmae spi transmit/receive operation 1 1 0 0 full-duplex communication the transmit and receive fi fos operate at the same time. data in the transmit fifo are transmitted or received. when there is no da ta left in the transmit fifo, the transmit and receive operat ions end. note that even if only reception is to be done, dummy transmission is necessary because only master mode is allowed in the spi mode. note: in spi mode, settings other than the above are prohibited. in half-duplex reception (transmission is disabl ed), the value output fr om the mosi can be controlled by the txdiz bit in simdr as follows. txdiz = 0: transmission is disabled, 1 is output on the mosi. txdiz = 1: transmission is disabled, th e mosi is in the high-impedance state. serial clock timing: timing on the data and clock lines in spi mode is shown in figures 16.22 and 16.23. the user can select from four serial transfer format s, which differ according to the phase and polarity of the serial clock. sck (cpol = 0) (cpol = 1) sampling miso/mosi ts: the setup time for the sck edge. the minimum value is 1/2 of the period of the sck. the setting is made by the ssast1 and ssast0 bits in spicr. th: the hold time for the sck edge. the minimum value is 0. td: the idle time. a number of sck-clock cycles from 0 to 3 is set by the fld1 and fld0 bits in spicr. msb ts th td bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ss0 figure 16.22 spi data/clock timing 1 (cpha = 0) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 497 of 794 rej09b0237-0500 sck (cpol = 0) (cpol = 1) sampling miso/mosi ts: the setup time for the sck edge. the minimum value is 0. the setting is made by the ssast1 and ssast0 bits in spicr. th: the hold time for the sck edge. the minimum value is 1/2 of the period of the sck. td: the idle time. a number of sck-clock cycles from 0 to 3 is set by the fld1 and fld0 bits in spicr. msb ts th td bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ss0 figure 16.23 spi data/clock timing 2 (cpha = 1) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 498 of 794 rej09b0237-0500 procedures for tran smission/reception: shown in figures 16.24 to 16.27 are examples of settings for spi transmission/reception alon g with the corresponding operations. time chart siof setting siof operation no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 start set the serial clock and threshold values for fifo. start baud rate generator operation. initialize the frame in the siof (ie, initialize the state of signal ss0 ), and enable transmission and reception. set the data for transmission. read the received data. disable transmission and reception. transmission/reception end. to be prepared for the transmission/reception that is resumed later, set fse = 0 to synchronize the frame in this lsi. to be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. if communication is not to be resumed (branching to no), no further setting is needed. to return to the same communication mode, go back to setting of fse at step 3 of this flowchart. go on to 'start' of the corresponding flowchart. [note] in spi mode, registers simdr, sitdar, sirdar, and sicdar should be set to their initial values. note: * for the case when interrupt generation on transmit fifo underflow is enabled, set the txe bit to 1 after setting data for trans mission at step no.5. [note] serial clock will not be output form the pin until communication is actually started. [note] communication is actually started after sitdr has been written. executes transmission and reception simultaneously. (even when transmission is not necessary, dummy transmission must be performed. the output of dummy transmission can be masked by setting the pin function.) check sistr.tfemp (transmit fifo empty) and ensure completion of communication by using a wait loop or other means. (checking sistr.tfemp is enough to confirm the completion of simultaneous transmission and reception.) set siscr, sifctr, and spicr. set the scke bit in sictr to 1. set the fse bit in sictr to 1. set the txe and rxe bits in sictr to 1. * tdreq=1? set the sitdr register. synchronously to ss0 , output the contents of sitdr from mosi and receive data from miso. rdreq=1? read the sirdr register. transfer complete? clear the txe and rxe bits in sictr to 0. clear the fse bit in sictr to 0. set bprs = 00000 and brdv = 111 in the siscr register. apply a pulse to bits txrst and rxrst in the sictr register (0->1->0 input). set the siscr register to set the baud rate again. change communication mode? no ye s no ye s no ye s no ye s end with fse=0, txe=0, and rxe=0 held, start setting other bits. figure 16.24 spi transmission/reception operation (example of full-duplex transmission/reception by the cpu with tdmae = 0) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 499 of 794 rej09b0237-0500 no. 1 2 3 4 5 6 7 8 9 10 11 12 start tdreq=1? no ye s no ye s no ye s end set siscr, sifctr, and spicr. set the scke bit in sictr to 1. set the fse bit in sictr to 1. set the txe bit in sictr to 1. * set the sitdr register. synchronously to ss0 , output the contents of sitdr from mosi. transfer complete? clear the txe bit in sictr to 0. clear the fse bit in sictr to 0. set bprs = 00000 and brdv = 111 in the siscr register. apply a pulse to bit txrst in the sictr register (0->1->0 input). set the siscr register to set the baud rate again. with fse=0, txe=0, and rxe=0 held, start setting other bits. note: * for the case when interrupt generation on transmit fifo underflow is enabled, set the txe bit to 1 after setting data for trans mission at step no.5. set the serial clock and threshold values for fifo. start baud rate generator operation. initialize the frame in the siof (ie, initialize the state of signal ss0 ), and enable transmission. [note] in spi mode, registers simdr, sitdar, sirdar, and sicdar should be set to their initial values. [note] serial clock will not be output form the pin until communication is actually started. [note] communication is actually started after sitdr has been written. set the data for transmission. executes transmission. transmission ends. disable transmission. to be prepared for the transmission/reception that is resumed later, set fse = 0 to synchronize the frame in this lsi. to be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. if communication is not to be resumed (branching to no), no further setting is needed. to return to the same communication mode, go back to setting of fse at step 3 of this flowchart. go on to 'start' of the corresponding flowchart. check sistr.tfemp (transmit fifo empty) and ensure completion of communication by using a wait loop or other means. time chart siof setting siof operation change communication mode? figure 16.25 spi transmission operation (example of half-duplex transmission by the cpu with tdmae = 0) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 500 of 794 rej09b0237-0500 time chart siof/dma setting siof/dma operation no. 1 2 3 4 5 6 7 8 9 10 12 13 11 start complete setting for dma before making settings for the siof. when the dma transfr end interrupt is used, clear the ie bit in dma.chcrn before the execution returns from the interrupt service routine. make settings for dma. tdreq=1? no ye s no ye s no ye s end set siscr, sifctr, spicr, and siier. set the scke bit in sictr to 1. set the fse bit in sictr to 1. set the txe bit in sictr to 1. dma transfer (set the sitdr register.) synchronously to ss0 , output the contents of sitdr from mosi. transfer complete? clear the txe bit in sictr to 0. clear the fse bit in sictr to 0. set bprs = 00000 and brdv = 111 in the siscr register. apply a pulse to bit txrst in the sictr register (0->1->0 input). set the siscr register to set the baud rate again. with fse=0, txe=0, and rxe=0 held, start setting other bits. set the serial clock, threshold values for fifo, and tdmae = 1 start baud rate generator operation. initialize the frame in the siof (ie, initialize the state of signal ss0 ), and enable transmission. set the data for transmission. disable transmission. to be prepared for the transmission/reception that is resumed later, set fse = 0 to synchronize the frame in this lsi. to be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. if communication is not to be resumed (branching to no), no further setting is needed. to return to the same communication mode, go back to setting of fse at step 4 of this flowchart. go on to 'start' of the corresponding flowchart. for example, in the dma transfer end interrupt service routine, check sistr.tfemp (transmit fifo empty) and ensure completion of communication by using a wait loop. [note] in spi mode, registers simdr, sitdar, sirdar, and sicdar should be set to their initial values. [note] serial clock will not be output form the pin until communication is actually started. [note] communication is actually started after sitdr has been written. executes transmission. transmission ends. change communication mode? figure 16.26 spi transmission operation (example of half-duplex transmission by dma with tdmae = 1) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 501 of 794 rej09b0237-0500 no. 1 2 3 4 5 6 7 8 9 10 12 13 11 start read data from the sirdr register. at the point when a dei interrupt is generated, reception has already proceeded excessively. therefore, read the necessary amount of data from fifo and skip the remainder, or cancel by rxrst. rdreq=1? no ye s no ye s no ye s end time chart siof/dma setting siof/dma operation make settings for dma. set siscr, sifctr, spicr, and siier. set the scke bit in sictr to 1. set the fse bit in sictr to 1. set the rxe bit in sictr to 1. dma transfer (read from the sirdr register.) synchronously to ss0 , receive data from miso. transfer complete? clear the rxe bit in sictr to 0. clear the fse bit in sictr to 0. set bprs = 00000 and brdv = 111 in the siscr register. apply a pulse to bit rxrst in the sictr register (0->1->0 input). set the siscr register to set the baud rate again. with fse=0, txe=0, and rxe=0 held, start setting other bits. complete setting for dma before making settings for the siof. set the serial clock, threshold values for fifo, and rdmae = 1 start baud rate generator operation. initialize the frame in the siof (ie, initialize the state of signal ss0 ), and enable reception. disable reception. to be prepared for the transmission/reception that is resumed later, set fse = 0 to synchronize the frame in this lsi. to be prepared for the transmission/reception that is resumed later, initialize inside the baud rate generator. if communication is not to be resumed (branching to no), no further setting is needed. to return to the same communication mode, go back to setting of fse at step 4 of this flowchart. go on to 'start' of the corresponding flowchart. when the dma transfr end interrupt is used, clear the ie bit in dma.chcrn before the execution returns from the interrupt service routine. [note] in spi mode, registers simdr, sitdar, sirdar, and sicdar should be set to their initial values. [note] serial clock will not be output form the pin until communication is actually started. [note] communication is actually started after rxe = 1 has been set. executes reception. reception ends. change communication mode? figure 16.27 spi reception operation (examp le of half-duplex reception by dma with rdmae = 1) section 16 serial i/o with fifo (siof) rev. 5.00 mar. 15, 2007 page 502 of 794 rej09b0237-0500 section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 503 of 794 rej09b0237-0500 section 17 host interface (hif) this lsi incorporates a host in terface (hif) for use in high-speed transfer of data between external devices which cannot utilize the system bus. the hif allows external devices to read from and write to 2 kbytes (1 kbyte 2 banks) of the on- chip ram exclusively for hif use (hifram) within this lsi, in 32-bit units. interrupts issued to this lsi by an external device, interrupts sent from this lsi to the external device, and dma transfer requests sent from this lsi to the external device are also supported. by using hifram and these interrupt functions, software-based data transfer between external devices and this lsi becomes possible, and connection to external devi ces not releasing bus mastership is enabled. using hifram, the hif also supports hif boot mode allowing this lsi to be booted. 17.1 features the hif has the following features. ? an external device can read from or write to hifram in 32-bit units via the hif pins (access in 8-bit or 16-bit units not allowed). the on-chip cpu can read from or write to hifram in 8- bit, 16-bit, or 32-bit units, via the internal peripheral bus. the hifram access mode can be specified as bank mode or non-bank mode. ? when an external device accesses hifram vi a the hif pins, automatic increment of addresses and the endian can be specifi ed with the hif internal registers. ? by writing to specific bits in the hif internal registers from an external device, or by accessing the end address of hifram from the external device, interrupts (internal interrupts) can be issued to the on-chip cpu. conversely, by writing to specific bits in the hif internal registers from the on-chip cpu, interrupts (external interrupts) or dmac transfer requests can be sent from the on-chip cpu to the external device. ? there are seven interrupt source bits each for internal interr upts and external interrupts. accordingly, software control of 128 different interrupts is possible, enabling high-speed data transfer using interrupts. ? in hif boot mode, this lsi can be booted from hifram by an external device storing the instruction code in hifram. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 504 of 794 rej09b0237-0500 figure 17.1 shows a block diagram of the hif. hifscr hifdata hifiicr hifmcr hifeicr hifbcr hifadr hifdtr hifbicr hifidx hifgsr hifcs hifrs hifwr hifrd hifmd hifint hifdreq hifd15 to hifd00 hif hifrdy hifebl hifi hifbi select hifram control circuit internal bus [legend] hif index register hif general status register hif status/control register hif memory control register hif internal interrupt control register hif external interrupt control register hifidx: hifgsr: hifscr: hifmcr: hifiicr: hifeicr: hif address register hif data register hif boot control register hifdreq trigger register hif bank interrupt control register hif interrupt (internal interrupt) hif bank interrupt (internal interrupt) hifadr: hifdata: hifbcr: hifdtr: hifbicr: hifi: hifib: hifram figure 17.1 block diagram of hif section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 505 of 794 rej09b0237-0500 17.2 input/output pins table 17.1 shows the hif pin configuration. table 17.1 pin configuration name abbreviation i/o description hif data pins hifd15 to hifd00 i/o address, data, or command input/output to the hif hif chip select hifcs input chip select input to the hif hif register select hifrs input switching between hif access types 0: normal access (other than below) 1: index register write or status register read hif write hifwr input write strobe signal. low level is input when an external device writes data to the hif. hif read hifrd input read strobe signal. low level is input when an external device reads data from the hif. hif interrupt hifint output interrupt request to an external device from the hif hif mode hifmd input selects whether or not this lsi is started up in hif boot mode. if a power-on reset is canceled when high level is input, this lsi is started up in hif boot mode. hifdmac transfer request hifdreq output to an external device, dmac transfer request with hifram as the destination hif boot ready hifrdy output indicates t hat the hif reset is canceled in this lsi and access from an external device to the hif can be accepted. after 10 clock cycles (max.) of the peripheral clock following negate of the reset input pin of this lsi, this pin is asserted. hif pin enable hifebl input all hif pins other than this pin are asserted by high-level input. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 506 of 794 rej09b0237-0500 17.3 parallel access 17.3.1 operation the hif can be accessed by combining the hifcs , hifrs, hifwr , and hifrd pins. table 17.2 shows the correspondence betw een combinations of these signals and hif operations. table 17.2 hif operations hifcs hifrs hifwr hifrd operation 1 * * * no operation (nop) 0 0 1 0 read from register specified by hifidx[7:0] 0 0 0 1 write to register specified by hifidx[7:0] 0 1 1 0 read from status register (hifgsr[7:0]) 0 1 0 1 write to index register (hifidx[7:0]) 0 * 1 1 no operation (nop) 0 * 0 0 setting prohibited [legend] * : don't care 17.3.2 connection method when connecting the hif to an external device, a method like that shown in figure 17.2 should be used. external device cs a02 wr rd d15 to d00 hif hifcs hifrs hifwr hifrd hifd15 to hifd00 figure 17.2 hif connection example section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 507 of 794 rej09b0237-0500 17.4 register descriptions the hif has the following registers. ? hif index register (hifidx) ? hif general status register (hifgsr) ? hif status/control register (hifscr) ? hif memory control register (hifmcr) ? hif internal interrupt control register (hifiicr) ? hif external interrupt control register (hifeicr) ? hif address register (hifadr) ? hif data register (hifdata) ? hif boot control register (hifbcr) ? hifdreq trigger register (hifdtr) ? hif bank interrupt control register (hifbicr) 17.4.1 hif index register (hifidx) hifidx is a 32-bit register used to specify the register read from or written to by an external device when the hifrs pin is held low. hifidx can be only read by the on-chip cpu. hifidx can be only written to by an external device while the hifrs pin is driven high. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 508 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 6 5 4 3 2 reg5 reg4 reg3 reg2 reg1 reg0 0 0 0 0 0 0 r/w * r/w * r/w * r/w * r/w * r/w * hif internal register select these bits specify which register among hifgsr, hifscr, hifmcr, hifii cr, hifeicr, hifadr, hifdata, and hifbcr is accessed by an external device. 000000: hifgsr 000001: hifscr 000010: hifmcr 000011: hifiicr 000100: hifeicr 000101: hifadr 000110: hifdata 001111: hifbcr other than above: setting prohibited section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 509 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 byte1 byte0 0 0 r/w * r/w * internal register byte specification these bits specify in advance the target word location before the external device accesses a register among hifgsr, hifscr, hifmcr, hi fiicr, hifeicr, hifadr, hifdata, and hifbcr. see also section 17.9, alignment control. ? when hifscr.bo = 0 00: bits 31 to 16 in register 01: setting prohibited 10: bits 15 to 0 in register 11: setting prohibited ? when hifscr.bo = 1 00: bits 15 to 0 in register 01: setting prohibited 10: bits 31 to 16 in register 11: setting prohibited however, when hifdata is selected using bits reg5 to reg0, each time reading or writing of hifdata occurs, these bits change according to the following rule. 00 10 00 10... repeated note: * this bit can be only written to by an external device while the hifrs pin is held high. it cannot be written to by the on-chip cpu. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 510 of 794 rej09b0237-0500 17.4.2 hif general status register (hifgsr) hifgsr is a 32-bit register, which can be freely used for handshaking between an external device connected to the hif and the softwa re of this lsi. hifgsr can be read from and written to by the on-chip cpu. reading from hifgsr by an external device should be performed with the hifrs pin high, or hifgsr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. writing to hifgsr by an external device should be perf ormed with hifgsr specifi ed by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 status15 to status0 all 0 r/w general status this register can be read from and written to by an external device connected to the hif, and by the on- chip cpu. these bits are initialized only at a power- on reset. 17.4.3 hif status/control register (hifscr) hifscr is a 32-bit register used to control the hifram access mode and endian setting. hifscr can be read from and written to by the on- chip cpu. access to hi fscr by an external device should be performed with hifscr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 511 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 dmd dpol 0 0 r/w r/w dreq mode dreq polarity controls the assert mode for the hifdreq pin. for details on the negate timing, see section 17.8, external dmac interface. 00: for a dmac transfer request to an external device, low level is generated at the hifdreq pin. the default for the hifdreq pin is high-level output. 01: for a dmac transfer request to an external device, high level is generated at the hifdreq pin. the default for the hifdreq pin is low-level output. 10: for a dmac transfer request to an external device, falling edge is generated at the hifdreq pin. the default for the hifdreq pin is high-level output. 11: for a dmac transfer request to an external device, rising edge is g enerated at the hifdreq pin. the default for the hifdreq pin is low-level output. 9 8 bmd bsel 0 0 r/w r/w hifram bank mode hifram bank select controls the hifram access mode. 00: both an external device and the on-chip cpu can access bank 0. when access by both of these conflict, even though the access addresses differ, access by the external device is processed before access by the on-chip cpu. bank 1 cannot be accessed. 01: both an external device and the on-chip cpu can access bank 1. when access by both of these conflict, even though the access addresses differ, access by the external device is processed before access by the on-chip cpu. bank 0 cannot be accessed. 10: an external device can access only bank 0 while the on-chip cpu can access only bank 1. 11: an external device can access only bank 1 while the on-chip cpu can access only bank 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 512 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 5 md1 0/1 r hif mode 1 indicates whether this lsi was started up in hif boot mode or non-hif boot mode. this bit stores the value of the hifmd pin sampled at a power-on reset 0: started up in non-hif boot mode (booted from the memory connected to area 0) 1: started up in hif boot mode (booted from hifram) 4, 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 wbswp 0 r/w byte order for access of hifdata specifies the byte order when an external device accesses hifdata. see also section 17.9, alignment control. 0: aligned according to the bo bit. 1: swapped in word units from the big endian order and then swapped in byte units within each word. the setting of the bo bit is ignored. 1 edn 0 r/w endian for hifram access specifies the byte order when hifram is accessed by the on-chip cpu. 0: big endian (msb first) 1: little endian (lsb first) section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 513 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 bo 0 r/w byte order for access of all hif registers including hifdata specifies the byte order when an external device accesses all hif register s including hifdata. however, for the hifdata alignment, this bit is referred to only when wbswp = 0 and ignored when wbswp = 1. see also section 17.9, alignment control. 0: big endian (msb first) 1: little endian (lsb first) 17.4.4 hif memory control register (hifmcr) hifmcr is a 32-bit register used to control hifram. hifmcr can be only read by the on-chip cpu. access to hifmcr by an external device should be performed with hifmcr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 lock 0 r/w * lock this bit is used to lock the access direction (read or write) for consecutive access of hifram by an external device via hifdata. when this bit is set to 1, the values of the rd and wt bits set at the same time are held until this bit is next cleared to 0. when the rd bit and this bit are simultaneously set to 1, consecutive read mode is entered. when the wt bit and this bit are simultaneously set to 1, consecutive write mode is entered. both the rd and wt bits should not be set to 1 simultaneously. 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 514 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 wt 0 r/w * write when this bit is set to 1, the hifdata value is written to the hifram position corresponding to hifadr. if this bit and the lock bit are set to 1 simultaneously, hifram consecutive writ e mode is entered, and high- speed data transfer becomes possible. this mode is maintained until this bit is next cleared to 0, or until the lock bit is cleared to 0. if the lock bit is not simultaneously set to 1 with this bit, writing to hifram is performed only once. thereafter, the value of this bit is automatically cleared to 0. 4 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 3 rd 0 r/w * read when this bit is set to 1, the hifram data corresponding to hifadr is fetched to hifdata. if this bit and the lock bit are set to 1 simultaneously, hifram consecutive read mode is entered, and high- speed data transfer becomes possible. this mode is maintained until this bit is next cleared to 0, or until the lock bit is cleared to 0. if the lock bit is not simultaneously set to 1 with this bit, reading of hifram is performed only once. thereafter, the value of this bit is automatically cleared to 0. 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 ai/ad 0 r/w * address auto-increment/decrement this bit is valid only when the lock bit is 1. the value of hifadr is automatically incremented by 4 or decremented by 4 according to the setting of this bit each time reading or writing of hifram is performed. 0: auto-increment mode (+4) 1: auto-decrement mode ( ? 4) note: * this bit can be only written to by an exte rnal device when the hifrs pin is low. it cannot be written to by the on-chip cpu. changing the hifram banks accessible from an external device by setting the bmd and bsel bits in hifscr does not affect the setting of this bit. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 515 of 794 rej09b0237-0500 17.4.5 hif internal interrupt control register (hifiicr) hifiicr is a 32-bit register used to issue interr upts from an external device connected to the hif to the on-chip cpu. access to hi fiicr by an external device sh ould be performed with hifiicr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 5 4 3 2 1 iic6 iic5 iic4 iic3 iic2 iic1 iic0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w internal interrupt source these bits specify the source for interrupts generated by the iir bit. these bits can be written to from both an external device and the on-chip cpu. by using these bits, fast execution of interrupt ex ception handling is possible. these bits are completely under software control, and their values have no effect on the operation of this lsi. 0 iir 0 r/w internal interrupt request while this bit is 1, an interrupt request (hifi) is issued to the on-chip cpu. 17.4.6 hif external interrupt control register (hifeicr) hifeicr is a 32-bit register used to issue interru pts to an external device connected to the hif from this lsi. access to hifeicr by an external device should be performed with hifeicr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 516 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 6 5 4 3 2 1 eic6 eic5 eic4 eic3 eic2 eic1 eic0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w external interrupt source these bits specify the source for interrupts generated by the eir bit. these bits can be written to from both an external device and the on-chip cpu. by using these bits, fast execution of interrupt ex ception handling is possible. these bits are completely under software control, and their values have no effect on the operation of this lsi. 0 eir 0 r/w external interrupt request while this bit is 1, the hifint pin is asserted to issue an interrupt request to an external device from this lsi. 17.4.7 hif address register (hifadr) hifadr is a 32-bit register which indicates the ad dress in hifram to be accessed by an external device. when using the lock bit setting in hi fmcr to specify consecutive access of hifram, auto-increment (+4) or auto-decrement (-4) of th e address, according to the ai/ad bit setting in hifmcr, is performed automatically, and hifadr is updated. hifadr can be only read by the on-chip cpu. access to hifadr by an external device should be performed with hifadr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 to 2 a9 to a2 all 0 r/w * hifram address specification these bits specify the address of hifram to be accessed by an external device, with 32-bit boundary. 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * this bit can be only written to by an extern al device when the hifrs pin is low. it cannot be written to by the on-chip cpu. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 517 of 794 rej09b0237-0500 17.4.8 hif data register (hifdata) hifdata is a 32-bit register used to hold data to be written to hifram and data read from hifram for external device accesse s. if hifdata is not used when accessing hifram, it can be used for data transfer between an external device connected to the hif and the on-chip cpu. hifdata can be read from and written to by the on-chip cpu. acces s to hifdata by an external device should be performed with hifdat a specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 0 d31 to d0 all 0 r/w 32-bit data 17.4.9 hif boot control register (hifbcr) hifbcr is a 32-bit register for exclusive control of an external device and the on-chip cpu regarding access of hifram. hifbcr can be only read by the on-chip cpu. access to hifbcr by an external device should be performed with hifbcr specified by bits reg5 to reg0 in hifidx and the hifrs pin low. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 1 ? all 0 r/w ac-bit writing assistance these bits should be used to write the bit pattern (h'a5) needed to set the ac bit to 1. these bits are always read as 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 518 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 ac 0/1 r/w hifram access exclusive control controls accessing of hifram by the on-chip cpu for the hifram bank selected by the bmd and bsel bits in hifscr as the bank allowed to be accessed by this lsi. 0: the on-chip cpu can perform reading/writing of hifram. 1: when an hifram read/writ e operation by the on-chip cpu occurs, the cpu enters the wait state, and execution of the instruction is halted until this bit is cleared to 0. when booted in non-hif boot m ode, the initial value of this bit is 0. when booted in hif boot mode, the initial value of this bit is 1. after an external device writes a boot program to hifram via the hif, clearing this bit to 0 boots the on- chip cpu from hifram. when 1 is written to this bit by an external device, h'a5 should be written to bits 7 to 0 to prevent erroneous writing. 17.4.10 hifdreq trigger register (hifdtr) hifdtr is a 32-bit register. writing to hifdtr by the on-chip cpu asserts the hifdreq pin. hifdtr cannot be accessed by an external device. bit bit name initial value r/w description 31 to 1 ? all 0 r * 1 reserved these bits are always read as 0. the write value should always be 0. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 519 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 dtrg 0 r/w * 1 * 2 hifdreq trigger when 1 is written to this bit, the hifdreq pin is asserted according to the setting of the dmd and dpol bits in hifscr. this bit is automatically cleared to 0 in synchronization with negate of the hifdreq pin. though this bit can be set to 1 by the on-chip cpu, it cannot be cleared to 0. to avoid conflict between clearing of this bit by negate of the hifdreq pin and setting of this bit by the on- chip cpu, make sure this bit is cleared to 0 before setting this bit to 1 by the on-chip cpu. notes: 1. this bit cannot be accessed by an exte rnal device. it can be accessed only by the on- chip cpu. 2. writing 0 to this bit by the on-chip cpu is ignored. 17.4.11 hif bank interrupt control register (hifbicr) hifbicr is a 32-bit register that controls hif bank interrupts. hifbicr cannot be accessed by an external device. bit bit name initial value r/w description 31 to 2 ? all 0 r * 1 reserved these bits are always read as 0. the write value should always be 0. 1 bie 0 r/w * 1 bank interrupt enable enables or disables a bank interrupt request (hifbi) issued to the on-chip cpu. 0: hifbi disabled 1: hifbi enabled section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 520 of 794 rej09b0237-0500 bit bit name initial value r/w description 0 bif 0 r/w * 1 * 2 bank interrupt request flag while this bit is 1, a bank interrupt request (hifbi) is issued to the on-chip cpu according to the setting of the bie bit. in auto-increment mode (ai/ad bit in hifmcr is 0), this bit is automatically set to 1 when an external device has completed access to the 32-bit data in the end address of hifram and the hifcs pin has been negated. in auto-decrement mode (ai/ad bit in hifmcr is 1), this bit is automatically set to 1 when an external device has completed access to the 32-bit data in the start address of hifram and the hifcs pin has been negated. though this bit can be cleared to 0 by the on-chip cpu, it cannot be set to 1. make sure setting of this bit by hifram access from an external device and clearing of this bit by the on- chip cpu do not conflict using software. notes: 1. this bit cannot be accessed by an external device. it can only be accessed by the on- chip cpu. 2. writing 1 to this bit by the on-chip cpu is ignored. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 521 of 794 rej09b0237-0500 17.5 memory map table 17.3 shows the memory map of hifram. table 17.3 memory map classification start address end address memory size map from external device * 1 h'0000 h'03ff 1 kbyte map from on-chip cpu * 1 * 2 h'f84e0000 h'f84e03ff 1 kbyte notes: 1. map for a single hifram bank. which bank is to be accessed by an external device or the on-chip cpu depends on the bmd an d bsel bits in hifscr. the mapping addresses are common between the banks. 2. note that in hif boot mode, bank 0 is selected, and the first 1 kbyte in each of the following address ranges are also mapped: h'00000000 to h'01ffffff (first-half 32 mbytes of area 0 in the p0 area), h'2000 0000 to h'21ffffff (first-half 32 mbytes of area 0 in the p0 area), h'40000000 to h'41fffff f (first-half 32 mbytes of area 0 in the p0 area), h'60000000 to h'61ffff ff (first-half 32 mbytes of area 0 in the p0 area), h'80000000 to h'81ffffff (first- half 32 mbytes of area 0 in the p1 area), h'a0000000 to h'a1ffffff (first-half 32 mbytes of ar ea 0 in the p2 area), and h'c0000000 to h'c1ffffff (first-half 32 mbytes of area 0 in the p3 area). if an external device modifies hifram when hifram is accessed from the p0, p1, or p3 area with the cache enabled, coheren cy may not be ensured. when the cache is enabled, accessing hifram from the p2 area is recommended. in hif boot mode, among the first-half 32 mbyt es of each area 0, access to the areas to which hifram is not mapped is inhibited. even in hif boot mode, the second-half 32 mbyt es of area 0, area 3, area 4, area 5b, area 5, area 6b, and area 6 are mapped to the external memory as normally. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 522 of 794 rej09b0237-0500 17.6 interface (basic) figure 17.3 shows the basic read/write sequence. hif read is defined by the overlap period of the hifrd low-level period and hifcs low-level period, and hif write is defined by the overlap period of the hifwr low-level period and hifcs low-level period. the hifrs signal indicates whether this is normal access or index/status register access; low level indicates normal access and high level indicates index/status register access. hifcs hifrs write cycle read cycle hifrd hifwr hifd15 to hifd00 wt_d rd_d figure 17.3 basic ti ming for hif interface section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 523 of 794 rej09b0237-0500 17.7 interface (details) 17.7.1 hifidx write/hifgsr read writing of hifidx and reading of hi fgsr are shown in figure 17.4. hifcs hifrs hifrd hifwr hifd15 to hifd00 wt_d rd_d hifidx write cycle hifgsr read cycle figure 17.4 hifidx write and hifgsr read 17.7.2 reading/writing of hif registers other than hifidx and hifgsr as shown in figure 17.5, in reading and writing of hif internal registers other than hifidx and hifgsr, first hifrs is held high and hifidx is wr itten to in order to sel ect the register to be accessed and the byte location. then hifrs is held low, and reading or wr iting of the register selected by hifidx is performed. hifcs hifrs hifrd hifwr hifd15 to hifd00 wt_d hifidx rd_d index write register write register read register selection figure 17.5 hif register settings section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 524 of 794 rej09b0237-0500 17.7.3 consecutive data writing to hifram by external device figure 17.6 shows the timing chart for consecutiv e data transfer from an external device to hifram. as shown in this timing chart, by setting the start address and the data to be written first, consecutive data transfer can subsequently be performed. hifcs hifrs hifrd hifwr hifd15 to hifd00 0016 ahal 0018 d0d1 001a d2d3 000a 00a0 0018 d4d5 d8d9 d6d7 high level hifadr setting [15:8] = ah [7:0] = al data for first write operation set in hifdata [31:24] = d0, [23:16] = d1, [15:8] = d2, [7:0] = d3 hifmcr setting consecutive write auto-increment hifdata selection consecutive data writing figure 17.6 consecutive data writing to hifram 17.7.4 consecutive data reading from hifram to external device figure 17.7 shows the timing chart for consecutiv e data reading from hifram to an external device. as this timing chart indicates, by setting the start address, data can subsequently be read out consecutively. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 525 of 794 rej09b0237-0500 hifcs hifrs hifrd hifwr 0016 ahal 000a 0088 0018 d0d1 d2d3 d4d5 d6d7 d8d9 dcdd dadb hifadr setting [15:8] = ah [7:0] = al hifmcr setting consecutive read auto-increment consecutive data reading hifdata selection hifd15 to hifd00 figure 17.7 consecutive data reading from hifram 17.8 external dmac interface figures 17.8 to 17.11 show the hifdreq output timing. the start of the hifdreq assert synchronizes with the dtrg bit in hifdtr being set to 1. the hifdreq negate timing and assert level are determined by the dmd and dpol bits in hifscr, respectively. when the external dmac is specified to detect low level of the hifdreq signal, set dmd = 0 and dpol = 0. after writing 1 to the dtrg bit, the hifdreq signal remains low until low level is detected for both the hifcs and hifrs signals. in this case, when the hifdreq signal is used, make sure that the setup time ( hifcs assertion to hifrs settling) and the hold time (hifrs hold to hifcs negate) are satisfied. if t hifas and t hifah stipulated in section 25.4.11, hif timing, are not satisfied, the hifdreq signal may be negated unintentionally. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 526 of 794 rej09b0237-0500 dtrg bit dpol bit hifdreq asserted in synchronization with the dtrg bit being set by the on-chip cpu. the dtrg bit is cleared simultaneously with hifdreq negate. negated when hifcs = hifrs = low level. latency is t pcyc (peripheral clock cycle) 3 cyc or less. hifcs hifrs figure 17.8 hifdreq timing (when dmd = 0 and dpol = 0) when the external dmac is specified to detect high level of the hifdreq signal, set dmd = 0 and dpol = 1. at the time the dpol bit is set to 1, hifdreq becomes low. then after writing 1 to the dtrg bit, hifdreq remains high until low level is detected for both the hifcs and hifrs signals. in this case, when the hifdreq signal is used, make sure that the setup time ( hifcs assertion to hifrs settling) and the hold time (hifrs hold to hifcs negate) are satisfied. if t hifas and t hifah stipulated in section 25.4.11, hif timing, are not satisfied, the hifdreq signal may be negated unintentionally. dtrg bit dpol bit hifdreq hifcs hifrs negated in synchronization with the dpol bit being set by the on-chip cpu. the dtrg bit is cleared simultaneously with hifdreq negate. negated when hifcs = hifrs = low level. latency is t pcyc (peripheral clock cycle) 3 cyc or less. asserted in synchronization with the dtrg bit being set by the on-chip cpu. figure 17.9 hifdreq timing (when dmd = 0 and dpol = 1) section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 527 of 794 rej09b0237-0500 when the external dmac is specified to detect the falling edge of the hifdreq signal, set dmd = 1 and dpol = 0. after writing 1 to the dtrg bit, a low pulse of 32 peripheral clock cycles is generated at the hifdreq pin. dtrg bit dpol bit hifdreq after assert, negated when t pcyc (peripheral clock cycle) 32 cyc have elapsed. asserted in synchronization with the dtrg bit being set by the on-chip cpu. the dtrg bit is cleared simultaneously with hifdreq negate. figure 17.10 hifdreq timing (when dmd = 1 and dpol = 0) when the external dmac is specified to detect the rising edge of the hifdreq signal, set dmd = 1 and dpol = 1. at the time the dpol bit is set to 1, hifdreq becomes low. then after writing 1 to the dtrg bit, a low pulse of 32 peripheral clock cycles is generated at the hifdreq pin. dtrg bit dpol bit hifdreq after assert, negated when t pcyc (peripheral clock cycle) 32 cyc have elapsed. asserted in synchronization with the dtrg bit being set by the on-chip cpu. the dtrg bit is cleared simultaneously with hifdreq negate. negated in synchronization with the dpol bit being set by the on-chip cpu. figure 17.11 hifdreq timing (when dmd = 1 and dpol = 1) when the external dmac supports intermittent op erating mode (block transfer mode), efficient data transfer can be implemented by using th e hifram consecutive acce ss and bank functions. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 528 of 794 rej09b0237-0500 table 17.4 consecutive write proced ure to hifram by external dmac external device this lsi no. cpu dmac hif cpu 1 hif initial setting hif initial setting 2 dmac initial setting 3 set hifadr to hifram end address ? 8 4 select hifdata and write dummy data (4 bytes) to hifdata 5 set hifram consecutive write with address increment in hifmcr 6 select hifdata and write dummy data (4 bytes) to hifdata hif bank interrupt occurs hifram bank switching by hif bank interrupt handler (external device accesses bank 1 and on- chip cpu accesses bank 0) 7 activate dmac assert hifdreq set dtrg bit to 1 8 consecutive data write to bank 1 in hifram 9 write to end address of bank 1 in hifram completes and operation halts hif bank interrupt occurs hifram bank switching by hif bank interrupt handler (external device accesses bank 0 and on- chip cpu accesses bank 1) 10 re-activate dmac assert hifdreq set dtrg bit to 1 11 consecutive data write to bank 0 in hifram read data from bank 1 in hifram section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 529 of 794 rej09b0237-0500 external device this lsi no. cpu dmac hif cpu 12 write to end address of bank 0 in hifram completes and operation halts hif bank interrupt occurs hifram bank switching by hif bank interrupt handler (external device accesses bank 1 and on- chip cpu accesses bank 0) 13 re-activate dmac assert hifdreq set dtrg bit to 1 hereafter no. 11 to 13 are repeated. when a regi ster other than hifdata is accessed (except that hifgsr read with hifrs = low), hifram cons ecutive write is interrupted, and no. 3 to 6 need to be done again. table 17.5 consecutive read procedure from hifram by external dmac external device this lsi no. cpu dmac hif cpu 1 hif initial setting hif initial setting 2 dmac initial setting 3 set hifadr to hifram start address 4 set hifram consecutive read with address increment in hifmcr 5 select hifdata 6 write data to bank 1 in hifram 7 after writing data to end address of bank 1 in hifram, perform hifram bank switching (external device accesses bank 1 and on- chip cpu accesses bank 0) 8 activate dmac assert hifdreq set dtrg bit to 1 section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 530 of 794 rej09b0237-0500 external device this lsi no. cpu dmac hif cpu 9 consecutive data read from bank 1 in hifram write data to bank 0 in hifram 10 read from end address of bank 1 in hifram completes and operation halts hif bank interrupt occurs hifram bank switching by hif bank interrupt handler (external device accesses bank 0 and on- chip cpu accesses bank 1) 11 re-activate dmac assert hifdreq set dtrg bit to 1 12 consecutive data read from bank 0 in hifram write data to bank 1 in hifram 13 read from end address of bank 0 in hifram completes and operation halts hif bank interrupt occurs hifram bank switching by hif bank interrupt handler (external device accesses bank 1 and on- chip cpu accesses bank 0) 14 re-activate dmac assert hifdreq set dtrg bit to 1 hereafter no. 12 to 14 are repeated. when a regi ster other than hifdata is accessed (except that hifgsr read with hifrs = low), hifram c onsecutive read is interrupted, and no. 3 to 5 need to be done again. section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 531 of 794 rej09b0237-0500 17.9 alignment control tables 17.6 and 17.7 show the alignment contro l when an external device accesses the hifdata register, and the hif registers other th an the hifdata regi ster, respectively. table 17.6 hifdata register alignment for access by an external device data in hifdata wbswp bi t bo bit byte[1:0] bits alignment in hifd[15:0] pins 0 0 b'00 h'7654 b'10 h'3210 1 b'00 h'3210 b'10 h'7654 1 0 b'00 h'1032 b'10 h'5476 1 b'00 h'5476 h'76543210 b'10 h'1032 table 17.7 hif registers (other than hifd ata) alignment for access by an external device data in hifdata wbswp bi t bo bit byte[1:0] bits alignment in hifd[15:0] pins 0 b'00 h'7654 b'10 h'3210 1 b'00 h'3210 h'76543210 don't care b'10 h'7654 section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 532 of 794 rej09b0237-0500 17.10 interface when external device power is cut off when the power supply of an external device in terfacing with the hif is cut off, intermediate levels may be applied to the hif input pins or the hif output pins may drive an external device not powered, thus causing the device to be damaged. the hifebl pin is provided to prevent this from happening. the system power monitor block controls the hifebl pin in synchronization with the cutoff of the external device power so th at all hif pins can be se t to the high-impedance state. figure 17.12 shows an imag e of high-impedance control of the hif pins. table 17.8 lists the input/output control for the hif pins. hifcs hifwr hifrd hifd15 to hifd00 hifrs hifmd hifint hifdreq hifrdy hifebl figure 17.12 image of high-impedance control of hif pins by hifebl pin section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 533 of 794 rej09b0237-0500 table 17.8 input/output control for hif pins lsi status reset state by res pin reset canceled by res pin hifmd input level high (boot setting) low (non-boot setting) high (after the reset canceled by boot setting) low (after the reset canceled by non-boot setting) hifebl input level low high the hifebl pin is a general input port and the hif is not controlled by the signal input on this pin. low high general input port at the initial state * 1 hifrdy output control output buffer: on (low output) output buffer: on (low output) general input port output buffer: off output buffer: on (sequence output) general input port at the initial state * 2 hifint output control output buffer: off output buffer: off general input port output buffer: off output buffer: on (sequence output) general input port at the initial state * 2 hifdreq output control output buffer: off output buffer: off general input port output buffer: off output buffer: on (sequence output) general input port at the initial state * 2 hifd 15 to hifd0 i/o control i/o buffer: off i/o buffer: off general input port i/o buffer: off i/o buffer controlled according to states of hifcs , hifwr , and hifrd general input port at the initial state * 2 hifcs input control input buffer: off input buffer: off general input port input buffer: off input buffer: on general input port at the initial state * 2 hifrs input control input buffer: off input buffer: off general input port input buffer: off input buffer: on general input port at the initial state * 2 section 17 host interface (hif) rev. 5.00 mar. 15, 2007 page 534 of 794 rej09b0237-0500 lsi status reset state by res pin reset canceled by res pin hifmd input level high (boot setting) low (non-boot setting) high (after the reset canceled by boot setting) low (after the reset canceled by non-boot setting) hifebl input level low high the hifebl pin is a general input port and the hif is not controlled by the signal input on this pin. low high general input port at the initial state * 1 hifwr input control input buffer: off input buffer: off general input port input buffer: off input buffer: on general input port at the initial state * 2 hifrd input control input buffer: off input buffer: off general input port input buffer: off input buffer: on general input port at the initial state * 2 notes: 1. the pin also functions as an hifebl pin by setting the pfc registers. 2. the pin also functions as an hif pin by setting the pfc registers. when the hif pin function is selected for the hifebl pin and this pin by setting the pfc registers, the input and/or output buffers are controlled according to the hifebl pin state. when the hif pin function is not selected for the hifebl pin and is selected for this pin by setting the pfc registers, the input and/or output buffers are always turned off. this setting is prohibited. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 535 of 794 rej09b0237-0500 section 18 pin function controller (pfc) the pin function controller (pfc) consists of registers that select multiplexed pin functions and input/output directions. tables 18.1 to 18.5 show the multiplexed pins in this lsi. table 18.6 shows the pin functions in each operating mode. table 18.1 list of mult iplexed pins (port a) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) a pa16 input/output (port) a16 output (bsc) ? ? pa17 input/output (port) a17 output (bsc) ? ? pa18 input/output (port) a18 output (bsc) ? ? pa19 input/output (port) a19 output (bsc) ? ? pa20 input/output (port) a20 output (bsc) ? ? pa21 input/output (port) a21 output (bsc) sck_sio0 input/output (siof) ? pa22 input/output (port) a22 output (bsc) siomclk0 input (siof) ? pa23 input/output (port) a23 output (bsc) rxd_sio0 input (siof) ? pa24 input/output (port) a24 output (bsc) txd_sio0 output (siof) ? pa25 input/output (port) a25 output (bsc) siofsync0 input/output (siof) ? table 18.2 list of mult iplexed pins (port b) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) b pb00 input/output (port) wait input (bsc) ? ? pb01 input/output (port) iois16 input (bsc) ? ? pb02 input/output (port) cke output (bsc) ? ? section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 536 of 794 rej09b0237-0500 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) b pb03 input/output (port) cas output (bsc) ? ? pb04 input/output (port) ras output (bsc) ? ? pb05 input/output (port) we2(be2) output (bsc) dqmul output (bsc) iciord output (bsc) ? ? pb06 input/output (port) we3(be3) output (bsc) dqmuu output (bsc) iciowr output (bsc) ? ? pb07 input/output (port) ce2b output (bsc) ? ? pb08 input/output (port) cs6b output (bsc) ce1b output (bsc) ? ? pb09 input/output (port) ce2a output (bsc) ? ? pb10 input/output (port) cs5b output (bsc) ce1a output (bsc) ? ? pb11 input/output (port) cs4 output (bsc) ? ? pb12 input/output (port) cs3 output (bsc) ? ? pb13 input/output (port) bs output (bsc) ? ? section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 537 of 794 rej09b0237-0500 table 18.3 list of mult iplexed pins (port c) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) c pc00 input/output (port) mii_rxd0 input (etherc) ? ? pc01 input/output (port) mii_rxd1 input (etherc) ? ? pc02 input/output (port) mii_rxd2 input (etherc) ? ? pc03 input/output (port) mii_rxd3 input (etherc) ? ? pc04 input/output (port) mii_txd0 output (etherc) ? speed100 output (phy) pc05 input/output (port) mii_txd1 output (etherc) ? link output (phy) pc06 input/output (port) mii_txd2 output (etherc) ? crs output (phy) pc07 input/output (port) mii_txd3 output (etherc) ? duplex output (phy) pc08 input/output (port) rx_dv input (etherc) ? ? pc09 input/output (port) rx_er input (etherc) ? ? pc10 input/output (port) rx_clk input (etherc) ? ? pc11 input/output (port) tx_er output (etherc) ? ? pc12 input/output (port) tx_en output (etherc) ? ? pc13 input/output (port) tx_clk input (etherc) ? ? pc14 input/output (port) col input (etherc) ? ? pc15 input/output (port) crs input (etherc) ? ? pc16 input/output (port) mdio input/output (etherc) ? ? pc17 input/output (port) mdc output (etherc) ? ? pc18 input/output (port) lnksta input (etherc) ? ? pc19 input/output (port) exout output (etherc) ? ? pc20 input/output (port) wol output (etherc) ? ? section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 538 of 794 rej09b0237-0500 table 18.4 list of mult iplexed pins (port d) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) d pd0 input/output (port) irq0 input (intc) ? tend0 output (dmac) pd1 input/output (port) irq1 input (intc) ? tend1 output (dmac) pd2 input/output (port) irq2 input (intc) txd1 output (scif) dreq0 input (dmac) pd3 input/output (port) irq3 input (intc) rxd1 input (scif) dack0 output (dmac) pd4 input/output (port) irq4 input (intc) sck1 input/output (scif) ? pd5 input/output (port) irq5 input (intc) txd2 output (scif) dreq1 input (dmac) pd6 input/output (port) irq6 input (intc) rxd2 input (scif) dack1 output (dmac) pd7 input/output (port) irq7 input (intc) sck2 input/output (scif) ? table 18.5 list of mult iplexed pins (port e) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe00 input/output (port) hifebl input (hif) sck_sio0 input/output (siof) ? pe01 input/output (port) hifrdy output (hif) siomclk0 input (siof) ? pe02 input/output (port) hifdreq output (hif) rxd_sio0 input (siof) ? pe03 input/output (port) hifmd input (hif) ? ? pe04 input/output (port) hifint output (hif) txd_sio0 output (siof) ? pe05 input/output (port) hifrd input (hif) ? ? pe06 input/output (port) hifwr input (hif) siosync0 input/output (siof) ? pe07 input/output (port) hifrs input (hif) ? ? pe08 input/output (port) hifcs input (hif) ? ? pe09 input/output (port) hifd00 input/output (hif) ? d16 input/output (bsc) pe10 input/output (port) hifd01 input/output (hif) ? d17 input/output (bsc) pe11 input/output (port) hifd02 input/output (hif) ? d18 input/output (bsc) pe12 input/output (port) hifd03 input/output (hif) ? d19 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 539 of 794 rej09b0237-0500 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe13 input/output (port) hifd04 input/output (hif) ? d20 input/output (bsc) pe14 input/output (port) hifd05 input/output (hif) ? d21 input/output (bsc) pe15 input/output (port) hifd06 input/output (hif) txd0 output (scif) d22 input/output (bsc) pe16 input/output (port) hifd07 input/output (hif) rxd0 input (scif) d23 input/output (bsc) pe17 input/output (port) hifd08 input/output (hif) sck0 input/output (scif) d24 input/output (bsc) pe18 input/output (port) hifd09 input/output (hif) txd1 output (scif) d25 input/output (bsc) pe19 input/output (port) hifd10 input/output (hif) rxd1 input (scif) d26 input/output (bsc) pe20 input/output (port) hifd11 input/output (hif) sck1 input/output (scif) d27 input/output (bsc) pe21 input/output (port) hifd12 input/output (hif) rts0 output (scif) d28 input/output (bsc) pe22 input/output (port) hifd13 input/output (hif) cts0 input (scif) d29 input/output (bsc) pe23 input/output (port) hifd14 input/output (hif) rts1 output (scif) d30 input/output (bsc) pe24 input/output (port) hifd15 input/output (hif) cts1 input (scif) d31 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 540 of 794 rej09b0237-0500 table 18.6 pin functions in each operating mode not hif boot mode hif boot mode pin no. initial function function settable by pfc initial function function settable by pfc c13 a00 ? a00 ? a14 a01 ? a01 ? b13 a02 ? a02 ? a13 a03 ? a03 ? c12 a04 ? a04 ? b12 a05 ? a05 ? d11 a06 ? a06 ? a12 a07 ? a07 ? c11 a08 ? a08 ? b11 a09 ? a09 ? d10 a10 ? a10 ? a11 a11 ? a11 ? c10 a12 ? a12 ? a10 a13 ? a13 ? d9 a14 ? a14 ? b10 a15 ? a15 ? a5 pa16 pa16/a16 pa16 pa16/a16 b5 pa17 pa17/a17 pa17 pa17/a17 a4 pa18 pa18/a18 pa18 pa18/a18 d5 pa19 pa19/a19 pa19 pa19/a19 b4 pa20 pa20/a20 pa20 pa20/a20 c4 pa21 pa21/a21/sck_sio0 pa21 pa21/a21/sck_sio0 a3 pa22 pa22/a22/siomclk0 pa22 pa22/a22/siomclk0 d4 pa23 pa23/a23/rxd_sio0 pa23 pa23/a23/rxd_sio0 b3 pa24 pa24/a24/txd_sio0 pa24 pa24/a24/txd_sio0 a2 pa25 pa25/a25/siofsync0 pa25 pa25/a25/siofsync0 b8 pb00 pb00/ wait pb00 pb00/ wait d6 pb01 pb01/ iois16 pb01 pb01/ iois16 c15 pb02 pb02/cke pb02 pb02/cke section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 541 of 794 rej09b0237-0500 not hif boot mode hif boot mode pin no. initial function function settable by pfc initial function function settable by pfc d12 pb03 pb03/ cas pb03 pb03/ cas c14 pb04 pb04/ ras pb04 pb04/ ras d15 ( we0 /dqmll) ? ( we0 /dqmll) ? d14 ( we1 /dqmlu/ we ) ? ( we1 /dqmlu/ we ) ? d7 pb05 pb05/ we2(be2) /dqmul/ iciord pb05 pb05/ we2(be2) /dqmul/ iciord c7 pb06 pb06/ we3(be3) /dqmuu/ iciowr pb06 pb06/ we3(be3) /dqmuu/ iciowr a8 rd ? rd ? d13 rdwr ? rdwr ? b6 pb07 pb07/ ce2b pb07 pb07/ ce2b c5 pb08 pb08/( cs6b / ce1b ) pb08 pb08/( cs6b / ce1b ) a6 pb09 pb09/ ce2a pb09 pb09/ ce2a c6 pb10 pb10/( cs5b / ce1a ) pb10 pb10/( cs5b / ce1a ) c8 pb11 pb11/ cs4 pb11 pb11/ cs4 a15 pb12 pb12/ cs3 pb12 pb12/ cs3 d8 cs0 ? cs0 ? c9 pb13 pb13/ bs pb13 pb13/ bs r6 pc00 pc00/mii_rxd0 pc00 pc00/mii_rxd0 m7 pc01 pc01/mii_rxd1 pc01 pc01/mii_rxd1 p6 pc02 pc02/mii_rxd2 pc02 pc02/mii_rxd2 n7 pc03 pc03/mii_rxd3 pc03 pc03/mii_rxd3 p8 pc04 pc04/mii_txd0/ speed100 pc04 pc04/mii_txd0/ speed100 m9 pc05 pc05/mii_txd1/ link pc05 pc05/mii_txd1/ link r9 pc06 pc06/mii_txd2/ crs pc06 pc06/mii_txd2/ crs n9 pc07 pc07/mii_txd3/ duplex pc07 pc07/mii_txd3/ duplex n6 pc08 pc08/rx_dv pc08 pc08/rx_dv m6 pc09 pc09/rx_er pc09 pc09/rx_er r8 pc10 pc10/rx_clk pc10 pc10/rx_clk n8 pc11 pc11/tx_er pc11 pc11/tx_er section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 542 of 794 rej09b0237-0500 not hif boot mode hif boot mode pin no. initial function function settable by pfc initial function function settable by pfc p9 pc12 pc12/tx_en pc12 pc12/tx_en m8 pc13 pc13/tx_clk pc13 pc13/tx_clk r10 pc14 pc14/col pc14 pc14/col p1 pc15 pc15/crs pc15 pc15/crs n2 pc16 pc16/mdio pc16 pc16/mdio m4 pc17 pc17/mdc pc17 pc17/mdc p2 pc18 pc18/lnksta pc18 pc18/lnksta n11 pc19 pc19/exout pc19 pc19/exout p10 pc20 pc20/wol pc20 pc20/wol d1 pd0 pd0/irq0/tend0 pd0 pd0/irq0/tend0 e4 pd1 pd1/irq1/tend1 pd1 pd1/irq1/tend1 d2 pd2 pd2/irq2/txd1/dreq0 pd2 pd2/irq2/txd1/dreq0 d3 pd3 pd3/irq3/rxd1/dack0 pd3 pd3/irq3/rxd1dack0 c1 pd4 pd4/irq4/sck1 pd4 pd4/irq4/sck1 c2 pd5 pd5/irq5/txd2/dreq1 pd5 pd5/irq5/txd2/dreq1 c3 pd6 pd6/irq6/rxd2/dack1 pd6 pd6/irq6/rxd2/dack1 b2 pd7 pd7/irq7/sck2 pd7 pd7/irq7/sck2 n1 pe00 pe00/hifebl/sck_sio0 hifebl pe00/hifebl/sck_sio0 m3 pe01 pe01/hifrdy/siomclk0 hifrdy pe01/hifrdy/siomclk0 m2 pe02 pe02/hifdreq/ rxd_sio0 hifdreq pe02/hifdreq/ rxd_sio0 l4 hifmd pe03/hifmd hifmd pe03/hifmd m1 pe04 pe04/ hifint /txd_sio0 hifint pe04/ hifint /txd_sio0 l2 pe05 pe05/ hifrd hifrd pe05/ hifrd l1 pe06 pe06/ hifwr /siofsync0 hifwr pe06/ hifwr /siofsync0 l3 pe07 pe07/hifrs hifrs pe07/hifrs e3 pe08 pe08/ hifcs hifcs pe08/ hifcs k3 pe09 pe09/hifd00/d16 hifd00 pe09/hifd00/d16 k4 pe10 pe10/hifd01/d17 hifd01 pe10/hifd01/d17 j2 pe11 pe11/hifd02/d18 hifd02 pe11/hifd02/d18 j3 pe12 pe12/hifd03/d19 hifd03 pe12/hifd03/d19 section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 543 of 794 rej09b0237-0500 not hif boot mode hif boot mode pin no. initial function function settable by pfc initial function function settable by pfc j1 pe13 pe13/hifd04/d20 hifd04 pe13/hifd04//d20 j4 pe14 pe14/hifd05/d21 hifd05 pe14/hifd05/d21 h2 pe15 pe15/hifd06/txd0/d22 hifd06 pe15/hifd06/txd0/d22 h1 pe16 pe16/hifd07/rxd0/d23 hifd07 pe16/hifd07/rxd0/d23 g2 pe17 pe17/hifd08/sck0/d24 hifd08 pe17/hifd08/sck0/d24 g1 pe18 pe18/hifd09/txd1/d25 hifd09 pe18/hifd09/txd1/d25 g3 pe19 pe19/hifd10/rxd1/d26 hifd10 pe19/hifd10/rxd1/d26 f2 pe20 pe20/hifd11/sck1/d27 hifd11 pe20/hifd11/sck1/d27 g4 pe21 pe21/hifd12/rts0/d28 hifd12 pe21/hifd12/rts0/d28 f1 pe22 pe22/hifd13/cts0/d29 hifd13 pe22/hifd13/cts0/d29 f3 pe23 pe23/hifd14/rts1/d30 hifd14 pe23/hifd14/rts1/d30 f4 pe24 pe24/hifd15/cts1/d31 hifd15 pe24/hifd15/cts1/d31 k14 d00 ? d00 ? j13 d01 ? d01 ? j15 d02 ? d02 ? h12 d03 ? d03 ? j14 d04 ? d04 ? h13 d05 ? d05 ? g12 d06 ? d06 ? g15 d07 ? d07 ? e15 d08 ? d08 ? e14 d09 ? d09 ? f14 d10 ? d10 ? f13 d11 ? d11 ? f15 d12 ? d12 ? f12 d13 ? d13 ? g14 d14 ? d14 ? g13 d15 ? d15 ? m14 trst input ? trst input ? n12 tdo output ? tdo output ? section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 544 of 794 rej09b0237-0500 not hif boot mode hif boot mode pin no. initial function function settable by pfc initial function function settable by pfc m12 tdi input ? tdi input ? m13 tms input ? tms input ? p12 tck input ? tck input ? r13 extal input ? extal input ? r14 xtal output ? xtal output ? k15 ckio output ? ckio output ? p11 ck_phy input ? ck_phy input ? l13 asemd input ? asemd input ? l14 testmd input ? testmd input ? r12 md3 input ? md3 input ? j12 md2 input ? md2 input ? l15 md1 input ? md1 input ? n13 md0 input ? md0 input ? m15 res input ? res input ? l12 nmi input ? nmi input ? m11 md5 input ? md5 input ? r11 testout output ? testout output ? section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 545 of 794 rej09b0237-0500 18.1 register descriptions the pfc has the following registers. for details on the addresses of these registers and the states of these registers in each pr ocessing state, see section 24, list of registers. ? port a io register h (paiorh) ? port a control register h1 (pacrh1) ? port a control register h2 (pacrh2) ? port b io register l (pbiorl) ? port b control register l1 (pbcrl1) ? port b control register l2 (pbcrl2) ? port c io register h (pciorh) ? port c io register l (pciorl) ? port c control register h2 (pccrh2) ? port c control register l1 (pccrl1) ? port c control register l2 (pccrl2) ? port d io register l (pdiorl) ? port d control register l2 (pdcrl2) ? port e io register h (peiorh) ? port e io register l (peiorl) ? port e control register h1 (pecrh1) ? port e control register h2 (pecrh2) ? port e control register l1 (pecrl1) ? port e control register l2 (pecrl2) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 546 of 794 rej09b0237-0500 18.1.1 port a io register h (paiorh) paiorh is a 16-bit readable/writable register that selects the input/output directions of the port a pins. bits pa25ior to pa16ior correspond to pins pa25 to pa16 (the pin name abbreviations for multiplexed functions are omitted). paiorh is enabled when a port a pin functions as a general input/output (pa25 to pa16), otherwise, disabled. setting a bit in paiorh to 1 makes the corresponding pin function as an output and clearing a bit in paiorh to 0 makes the pin function as an input. bits 15 to 10 in paiorh are reserved. these bits are always read as 0. the write value should always be 0. the initial value of paiorh is h'0000. 18.1.2 port a control register h1 and h2 (pacrh1 and pacrh2) pacrh1 and pacrh2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port a pins. ? pacrh1 bit bit name initial value r/w description 15 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 pa25md1 pa25md0 0 0 r/w r/w pa25 mode select the function of pin pa25/a25/siofsync0. 00: pa25 input/output (port) 01: a25 output (bsc) 10: siofsync0 input/output (siof) 11: setting prohibited section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 547 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 pa24md1 pa24md0 0 0 r/w r/w pa24 mode select the function of pin pa24/a24/txd_sio0. 00: pa24 input/output (port) 01: a24 output (bsc) 10: txd_sio0 output (bsc) 11: setting prohibited ? pacrh2 bit bit name initial value r/w description 15 14 pa23md1 pa23md0 0 0 r/w r/w pa23 mode select the function of pin pa23/a23/rxd_sio0. 00: pa23 input/output (port) 01: a23 output (bsc) 10: rxd_sio0 input (siof) 11: setting prohibited 13 12 pa22md1 pa22md0 0 0 r/w r/w pa22 mode select the function of pin pa22/a22/siomclk0. 00: pa22 input/output (port) 01: a22 output (bsc) 10: siomclk0 input (siof) 11: setting prohibited 11 10 pa21md1 pa21md0 0 0 r/w r/w pa21 mode select the function of pin pa21/a21/sck_sio0. 00: pa21 input/output (port) 01: a21 output (bsc) 10: sck_sio0 input/output (siof) 11: setting prohibited 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 548 of 794 rej09b0237-0500 bit bit name initial value r/w description 8 pa20md0 0 r/w pa20 mode selects the function of pin pa20/a20. 0: pa20 input/output (port) 1: a20 output (bsc) 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pa19md0 0 r/w pa19 mode selects the function of pin pa19/a19. 0: pa19 input/output (port) 1: a19 output (bsc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pa18md0 0 r/w pa18 mode selects the function of pin pa18/a18. 0: pa18 input/output (port) 1: a18 output (bsc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pa17md0 0 r/w pa17 mode selects the function of pin pa17/a17. 0: pa17 input/output (port) 1: a17 output (bsc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pa16md0 0 r/w pa16 mode selects the function of pin pa16/a16. 0: pa16 input/output (port) 1: a16 output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 549 of 794 rej09b0237-0500 18.1.3 port b io register l (pbiorl) pbiorl is a 16-bit readable/writable register that selects the input/output directions of the port b pins. bits pb13ior to pb0ior correspond to pins pb13 to pb00 (the pin name abbreviations for multiplexed functions are omitted). pbiorl is enabled when a port b pin functions as a general input/output (pb13 to pb00), otherwise, disabled. setting a bit in pbiorl to 1 makes the corresponding pin function as an output and clearing a bit in pbiorl to 0 makes the pin function as an input. bits 15 and 14 in pbiorl are reserved. these bits are always read as 0. the write value should always be 0. the initial value of paibrl is h'0000. 18.1.4 port b control register l1 and l2 (pbcrl1 and pbcrl2) pbcrl1 and pbcrl2 are 16-bit readable/writable re gisters that select the pin functions for the multiplexed port b pins. ? pbcrl1 bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 pb13md0 0 r/w pb13 mode selects the function of pin pb13/ bs . 0: pb13 input/output (port) 1: bs output (bsc) 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 pb12md0 0 r/w pb12 mode selects the function of pin pb12/ cs3 . 0: pb12 input/output (port) 1: cs3 output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 550 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pb11md0 0 r/w pb11 mode selects the function of pin pb11/ cs4 . 0: pb11 input/output (port) 1: cs4 output (bsc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pb10md0 0 r/w pb10 mode selects the function of pin pb10/ cs5b / ce1a . 0: pb10 input/output (port) 1: cs5b / ce1a output (bsc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pb9md0 0 r/w pb9 mode selects the function of pin pb09/ ce2a . 0: pb09 input/output (port) 1: ce2a output (bsc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pb8md0 0 r/w pb8 mode selects the function of pin pb08/ cs6b / ce1b . 0: pb08 input/output (port) 1: cs6b / ce1b output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 551 of 794 rej09b0237-0500 ? pbcrl2 bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 pb7md0 0 r/w pb7 mode selects the function of pin pb07/ ce2b . 0: pb07 input/output (port) 1: ce2b output (bsc) 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 pb6md0 0 r/w pb6 mode selects the function of pin pb06/ we3(be3) /dqmuu/ iciowr . 0: pb06 input/output (port) 1: we3(be3) /dqmuu/ iciowr output (bsc) 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 pb5md0 0 r/w pb5 mode selects the function of pin pb05/ we2(be2) /dqmul/ iciord . 0: pb05 input/output (port) 1: we2(be2) /dqmul/ iciord output (bsc) 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 pb4md0 0 r/w pb4 mode selects the function of pin pb04/ ras . 0: pb04 input/output (port) 1: ras output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 552 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pb3md0 0 r/w pb3 mode selects the function of pin pb03/ cas . 0: pb03 input/output (port) 1: cas output (bsc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pb2md0 0 r/w pb2 mode selects the function of pin pb02/cke. 0: pb02 input/output (port) 1: cke output (bsc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pb1md0 0 r/w pb1 mode selects the function of pin pb01/ iois16 . 0: pb01 input/output (port) 1: iois16 input (bsc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pb0md0 0 r/w pb0 mode selects the function of pin pb00/ wait . 0: pb00 input/output (port) 1: wait input (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 553 of 794 rej09b0237-0500 18.1.5 port c io register h and l (pciorh and pciorl) pciorh and pciorl are 16-bit readable/writable re gisters that select the input/output directions of the port c pins. bits pc20ior to pc0ior correspond to pins pc20 to pc00 (the pin name abbreviations for multiplexed functions are omitt ed). pciorh is enabled when a port c pin functions as a general input/output (pc20 to pc16), otherwise, disabled. pciorl is enabled when a port c pin functions as a general input/output (pc15 to pc00), otherwise, disabled. setting a bit in pciorh and pciorl to 1 makes the corresponding pin function as an output and clearing a bit in pciorh and pciorl to 0 makes the pin function as an input. bits 15 to 5 in pciorh are reserved. these bits are always read as 0. the write value should always be 0. the initial values of pciorh and pciorl are h'0000. 18.1.6 port c control register h2, l1 , and l2 (pccrh2, pccrl1, and pccrl2) pccrh2, pccrl1, and pccrl2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port c pins. ? pccrh2 bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 pc20md0 0 r/w pc20 mode selects the function of pin pc20/wol. 0: pc20 input/output (port) 1: wol output (etherc) 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 554 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 pc19md0 0 r/w pc19 mode selects the function of pin pc19/exout. 0: pc19 input/output (port) 1: exout output (etherc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pc18md0 0 r/w pc18 mode selects the function of pin pc18/lnksta. 0: pc18 input/output (port) 1: lnksta input (etherc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pc17md0 0 r/w pc17 mode selects the function of pin pc17/mdc. 0: pc17 input/output (port) 1: mdc output (etherc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pc16md0 0 r/w pc16 mode selects the function of pin pc16/mdio. 0: pc16 input/output (port) 1: mdio input/output (etherc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 555 of 794 rej09b0237-0500 ? pccrl1 bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 pc15md0 0 r/w pc15 mode selects the function of pin pc15/crs. 0: pc15 input/output (port) 1: crs input (etherc) 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 pc14md0 0 r/w pc14 mode selects the function of pin pc14/col. 0: pc14 input/output (port) 1: col input (etherc) 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 pc13md0 0 r/w pc13 mode selects the function of pin pc13/tx_clk. 0: pc13 input/output (port) 1: tx_clk input (etherc) 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 pc12md0 0 r/w pc12 mode selects the function of pin pc12/tx_en. 0: pc12 input/output (port) 1: tx_en output (etherc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 556 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pc11md0 0 r/w pc11 mode selects the function of pin pc11/tx_er. 0: pc11 input/output (port) 1: tx_er output (etherc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pc10md0 0 r/w pc10 mode selects the function of pin pc10/rx_clk. 0: pc10 input/output (port) 1: rx_clk input (etherc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pc9md0 0 r/w pc9 mode selects the function of pin pc09/rx_er. 0: pc09 input/output (port) 1: rx_er input (etherc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pc8md0 0 r/w pc8 mode selects the function of pin pc08/rx_dv. 0: pc08 input/output (port) 1: rx_dv input (etherc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 557 of 794 rej09b0237-0500 ? pccrl2 bit bit name initial value r/w description 15 14 pc7md1 pc7md0 0 0 r/w r/w pc7 mode select the function of pin pc7/mii_txd3/ duplex . 00: pc07 input/output (port) 01: mii_txd3 output (etherc) 10: setting prohibited 11: duplex output (phy) 13 12 pc6md1 pc6md0 0 0 r/w r/w pc6 mode select the function of pin pc6/mii_txd2/ crs . 00: pc06 input/output (port) 01: mii_txd2 output (etherc) 10: setting prohibited 11: crs output (phy) 11 10 pc5md1 pc5md0 0 0 r/w r/w pc5 mode select the function of pin pc5/mii_txd1/ link . 00: pc05 input/output (port) 01: mii_txd1 output (etherc) 10: setting prohibited 11: link output (phy) 9 8 pc4md1 pc4md0 0 0 r/w r/w pc4 mode select the function of pin pc4/mii_txd0/ speed100 . 00: pc04 input/output (port) 01: mii_txd0 output (etherc) 10: setting prohibited 11: speed100 output (phy) 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 558 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 pc3md0 0 r/w pc3 mode selects the function of pin pc03/mii_rxd3. 0: pc03 input/output (port) 1: mii_rxd3 input (etherc) 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 pc2md0 0 r/w pc2 mode selects the function of pin pc02/mii_rxd2. 0: pc02 input/output (port) 1: mii_rxd2 input (etherc) 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 pc1md0 0 r/w pc1 mode selects the function of pin pc01/mii_rxd1. 0: pc01 input/output (port) 1: mii_rxd1 input (etherc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pc0md0 0 r/w pc0 mode selects the function of pin pc00/mii_rxd0. 0: pc00 input/output (port) 1: mii_rxd0 input (etherc) 18.1.7 port d io register l (pdiorl) pdiorl is a 16-bit readable/writable register that selects the input/output directions of the port d pins. bits pd7ior to pd0ior correspond to pins pd7 to pd0 (the pin name abbreviations for multiplexed functions are omitted). pdiorl is enabled when a port c pin functions as a general input/output (pd7 to pd0), otherwise, disabled. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 559 of 794 rej09b0237-0500 setting a bit in pdiorl to 1 makes the corresponding pin function as an output and clearing a bit in pdiorl to 0 makes the pin function as an input. bits 15 to 8 in pdiorl are reserved. these bits are always read as 0. the write value should always be 0. the initial value of pdiorl is h'0000. 18.1.8 port d control register l2 (pdcrl2) pdcrl2 is a 16-bit readable/writable register that selects the pin functions for the multiplexed port b pins. ? pdcrl2 bit bit name initial value r/w description 15 14 pd7md1 pd7md0 0 0 r/w r/w pd7 mode select the function of pin pd7/irq7/sck2. 00: pd7 input/output (port) 01: irq7 input (intc) 10: sck2 input/output (scif) 11: setting prohibited 13 12 pd6md1 pd6md0 0 0 r/w r/w pd6 mode select the function of pin pd6/irq6/rxd2/dack1. 00: pd6 input/output (port) 01: irq6 input (intc) 10: rxd2 input (scif) 11: dack1 output (dmac) 11 10 pd5md1 pd5md0 0 0 r/w r/w pd5 mode select the function of pin pd5/irq5/txd2/dreq1. 00: pd5 input/output (port) 01: irq5 input (intc) 10: txd2 output (scif) 11: dreq1 input (dmac) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 560 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 8 pd4md1 pd4md0 0 0 r/w r/w pd4 mode select the function of pin pd4/irq4/sck1. 00: pd4 input/output (port) 01: irq4 input (intc) 10: sck1 input/output (scif) 11: setting prohibited 7 6 pd3md1 pd3md0 0 0 r/w r/w pd3 mode select the function of pin pd3/irq3/rxd1/dack0. 00: pd3 input/output (port) 01: irq3 input (intc) 10: rxd1 input (scif) 11: dack0 output (dmac) 5 4 pd2md1 pd2md0 0 0 r/w r/w pd2 mode select the function of pin pd2/irq2/txd1/dreq0. 00: pd2 input/output (port) 01: irq2 input (intc) 10: txd1 output (scif) 11: dreq0 input (dmac) 3 2 pd1md1 pd1md0 0 0 r/w r/w pd1 mode select the function of pin pd1/irq1/tend1. 00: pd1 input/output (port) 01: irq1 input (intc) 10: setting prohibited 11: tend1 output (dmac) 1 0 pd0md1 pd0md0 0 0 r/w r/w pd0 mode select the function of pin pd0/irq0/tend0. 00: pd0 input/output (port) 01: irq0 input (intc) 10: setting prohibited 11: tend0 output (dmac) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 561 of 794 rej09b0237-0500 18.1.9 port e io register h and l (peiorh and peiorl) peiorh and peiorl are 16-bit readable/writable regi sters that select the in put/output directions of the port e pins. bits pe24ior to pe0ior correspond to pins pe24 to pe00 (the pin name abbreviations for multiplexed functions are omitt ed). peiorh is enabled when a port e pin functions as a general input/output (pe24 to pe16), otherwise, disabled. peiorl is enabled when a port e pin functions as a general input/output (pe15 to pe00), otherwise, disabled. setting a bit in peiorh and peiorl to 1 makes the corresponding pin function as an output and clearing a bit in peiorh and peiorl to 0 makes the pin function as an input. bits 15 to 9 in paiorh are reserved. these bits are always read as 0. the write value should always be 0. the initial values of peiorh and peiorl are h'0000. 18.1.10 port e control register h1, h2, l1, and l2 (pecrh1, pecrh2, pecrl1, and pecrl2) pecrh1, pecrh2, pecrl1, and pecrl2 are 16-bit readable/writable registers that select the pin functions for the multiplexed port e pins. ? pecrh1 bit bit name initial value r/w description 15 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 pe24md1 pe24md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe24 mode select the function of pi n pe24/hifd15/cts1/d31. 00: pe24 input/output (port) 01: hifd15 input/output (hif) 10: cts1 input (scif) 11: d31 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 562 of 794 rej09b0237-0500 ? pecrh2 bit bit name initial value r/w description 15 14 pe23md1 pe23md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe23 mode select the function of pi n pe23/hifd14/rts1/d30. 00: pe23 input/output (port) 01: hifd14 input/output (hif) 10: rts1 input (scif) 11: d30 input/output (bsc) 13 12 pe22md1 pe22md0 0 0 (when in non- hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe22 mode select the function of pi n pe22/hifd13/cts0/d29. 00: pe22 input/output (port) 01: hifd13 input/output (hif) 10: cts0 input (scif) 11: d29 input/output (bsc) 11 10 pe21md1 pe21md0 0 0 (when in non- hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe21 mode select the function of pi n pe21/hifd12/rts0/d28. 00: pe21 input/output (port) 01: hifd12 input/output (hif) 10: rts0 output (scif) 11: d28 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 563 of 794 rej09b0237-0500 bit bit name initial value r/w description 9 8 pe20md1 pe20md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe20 mode select the function of pi n pe20/hifd11/sck1/d27. 00: pe20 input/output (port) 01: hifd11 input/output (hif) 10: sck1 input/output (scif) 11: d27 input/output (bsc) 7 6 pe19md1 pe19md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe19 mode select the function of pi n pe19/hifd10/rxd1/d26. 00: pe19 input/output (port) 01: hifd10 input/output (hif) 10: rxd1 output (scif) 11: d26 input/output (bsc) 5 4 pe18md1 pe18md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe18 mode select the function of pi n pe18/hifd09/txd1/d25. 00: pe18 input/output (port) 01: hifd09 input/output (hif) 10: txd1 output (scif) 11: d25 input/output (bsc) 3 2 pe17md1 pe17md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe17 mode select the function of pi n pe17/hifd08/sck0/d24. 00: pe17 input/output (port) 01: hifd08 input/output (hif) 10: sck0 input/output (scif) 11: d24 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 564 of 794 rej09b0237-0500 bit bit name initial value r/w description 1 0 pe16md1 pe16md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe16 mode select the function of pi n pe16/hifd07/rxd0/d23. 00: pe16 input/output (port) 01: hifd07 input/output (hif) 10: rxd0 input (scif) 11: d23 input/output (bsc) ? pecrl1 bit bit name initial value r/w description 15 14 pe15md1 pe15md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe15 mode select the function of pi n pe15/hifd06/txd0/d22. 00: pe15 input/output (port) 01: hifd06 input/output (hif) 10: txd0 output (scif) 11: d22 input/output (bsc) 13 12 pe14md1 pe14md0 0 0 (when in non- hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe14 mode select the function of pin pe14/hifd05/d21. 00: pe14 input/output (port) 01: hifd05 input/output (hif) 10: setting prohibited 11: d21 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 565 of 794 rej09b0237-0500 bit bit name initial value r/w description 11 10 pe13md1 pe13md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe13 mode select the function of pin pe13/hifd04/d20. 00: pe13 input/output (port) 01: hifd04 input/output (hif) 10: setting prohibited 11: d20 input/output (bsc) 9 8 pe12md1 pe12md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe12 mode select the function of pin pe12/hifd03/d19. 00: pe12 input/output (port) 01: hifd03 input/output (hif) 10: setting prohibited 11: d19 input/output (bsc) 7 6 pe11md1 pe11md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe11 mode select the function of pin pe11/hifd02/d18. 00: pe11 input/output (port) 01: hifd02 input/output (hif) 10: setting prohibited 11: d18 input/output (bsc) 5 4 pe10md1 pe10md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe10 mode select the function of pin pe10/hifd01/d17. 00: pe10 input/output (port) 01: hifd01 input/output (hif) 10: setting prohibited 11: d17 input/output (bsc) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 566 of 794 rej09b0237-0500 bit bit name initial value r/w description 3 2 pe9md1 pe9md0 0 0 (when in non- hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe9 mode select the function of pin pe09/hifd00/d16. 00: pe09 input/output (port) 01: hifd00 input/output (hif) 10: setting prohibited 11: d16 input/output (bsc) 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 pe8md0 0 (when in non- hif boot mode) 1 (when in hif boot mode) r/w pe8 mode selects the function of pin pe08/ hifcs . 0: pe08 input/output (port) 1: hifcs input (hif) ? pecrl2 bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 pe7md0 0 (when in non-hif boot mode) 1 (when in hif boot mode) r/w pe7 mode selects the function of pin pe07/hifrs. 0: pe07 input/output (port) 1: hifrs input (hif) section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 567 of 794 rej09b0237-0500 bit bit name initial value r/w description 13 12 pe6md1 pe6md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe6 mode select the function of pin pe06/ hifwr /siofsync0. 00: pe06 input/output (port) 01: hifwr input (hif) 10: siofsync0 input/output (siof) 11: setting prohibited 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 pe5md0 0 (when in non-hif boot mode) 1 (when in hif boot mode) r/w pe5 mode selects the function of pin pe05/ hifrd . 0: pe05 input/output (port) 1: hifrd input (hif) 9 8 pe4md1 pe4md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe4 mode select the function of pin pe04/ hifint /txd_sio0. 00: pe04 input/output (port) 01: hifint input (hif) 10: txd_sio0 output (siof) 11: setting prohibited 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 18 pin function controller (pfc) rev. 5.00 mar. 15, 2007 page 568 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 pe3md0 1 r/w pe3 mode selects the function of pin pe03/hifmd. 0: pe03 input/output (port) 1: hifmd input (hif) 5 4 pe2md1 pe2md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe2 mode select the function of pin pe02/hifdreq/rxd_sio0. 00: pe02 input/output (port) 01: hifdreq output (hif) 10: rxd_sio0 input (siof) 11: setting prohibited 3 2 pe1md0 pe1md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe1 mode select the function of pin pe01/hifrdy/siomclk0. 00: pe01 input/output (port) 01: hifrdy output (hif) 10: siomclk0 input (siof) 11: setting prohibited 1 0 pe0md1 pe0md0 0 0 (when in non-hif boot mode) 0 1 (when in hif boot mode) r/w r/w pe0 mode select the function of pin pe00/hifebl/sck_sio0. 00: pe00 input/output (port) 01: hifebl input (hif) 10: sck_sio0 input/output (siof) 11: setting prohibited section 19 i/o ports rev. 5.00 mar. 15, 2007 page 569 of 794 rej09b0237-0500 section 19 i/o ports this lsi has 26 ports (ports a, b, c, d, and e). port a, port b, port c, port d, and port e are 10- bit, 14-bit, 21-bit, 8-bit, and 25 -bit i/o port, respectively. the pi ns of each port are multiplexed with other functions. the pin function controller (pfc) handles the selection of multiplex pin functions. each port has a data register to store data of pin. 19.1 port a port a of this lsi is an i/o port with ten pins as shown in figure 19.1. pa16 (input/output)/a16 (output) pa17 (input/output)/a17 (output) pa18 (input/output)/a18 (output) pa19 (input/output)/a19 (output) pa20 (input/output)/a20 (output) pa21 (input/output)/a21 (output)/sck_sio0 (input/output) pa22 (input/output)/a22 (output)/siomclk0 (input) pa23 (input/output)/a23 (output)/rxd_sio0 (input) pa24 (input/output)/a24 (output)/txd_sio0 (output) pa25 (input/output)/a25 (output)/siofsync0 (input/output) port a figure 19.1 port a 19.1.1 register description port a is a 10-bit i/o port that has a following register. for details on the address of this register and the states of this register in each processi ng state, see section 24 , list of registers. ? port a data register h (padrh) 19.1.2 port a data register h (padrh) padrh is a 16-bit readable/writable register which stores data for port a. bits pa25dr to pa16dr correspond to pins pa25 to pa16. (description of multiplexed functions is omitted.) section 19 i/o ports rev. 5.00 mar. 15, 2007 page 570 of 794 rej09b0237-0500 when the pin function is general output port, if the value is written to padrh, the value is output from the pin; if padrh is read, the value written to the register is directly read regardless of the pin state. when the pin function is general input port, not the value of register but pin state is directly read if padrh is read. data can be written to padrh but no effect on the pin state. table 19.1 shows the reading/writing function of the port a data register h. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 pa25dr 0 r/w see table 19.1. 8 pa24dr 0 r/w 7 pa23dr 0 r/w 6 pa22dr 0 r/w 5 pa21dr 0 r/w 4 pa20dr 0 r/w 3 pa19dr 0 r/w 2 pa18dr 0 r/w 1 pa17dr 0 r/w 0 pa16dr 0 r/w table 19.1 port a data register h (padrh) read/write operation ? bits 9 to 0 in padrh pin function paiorh read write general input 0 pin state data can be written to padrh but no effect on the pin state. general output 1 padrh value written value is output from the pin. other functions * padrh value data can be written to padrh but no effect on the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 571 of 794 rej09b0237-0500 19.2 port b port b of this lsi is an i/o port wi th 14 pins as shown in figure 19.2. pb09 (input/output)/ ce2a (output) pb08 (input/output)/ cs6b (output)/ ce1b (output) pb07 (input/output)/ ce2b (output) pb06 (input/output)/ we3(be3) /dqmuu/ iciowr (output) pb05 (input/output)/ we2(be2) /dqmul/ iciord (output) pb02 (input/output)/cke (output) pb03 (input/output)/ cas (output) pb04 (input/output)/ ras (output) pb01 (input/output)/ iois16 (input) pb00 (input/output)/ wait (input) pb10 (input/output)/ cs5b (output)/ ce1a (output) pb11 (input/output)/ cs4 (output) pb12 (input/output)/ cs3 (output) pb13 (input/output)/ bs (output) port b figure 19.2 port b 19.2.1 register description port b is a 14-bit i/o port that has a following regi ster. for details on the ad dress of this register and the states of this register in each processi ng state, see section 24 , list of registers. ? port b data register l (pbdrl) 19.2.2 port b data register l (pbdrl) pbdrl is a 16-bit readable/writable register which stores data for port b. bits pb13dr to pb0dr correspond to pins pb13 to pb00. (description of multiplexed functions is omitted.) when the pin function is general output port, if the value is written to pbdrl, the value is output from the pin; if pbdrl is read, the value written to the register is directly read regardless of the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 572 of 794 rej09b0237-0500 when the pin function is general input port, not the value of register but pin state is directly read if pbdrl is read. data can be written to pbdrl but no effect on the pin state. table 19.2 shows the reading/writing function of the port b data register l. bit bit name initial value r/w description 15 14 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. 13 pb13dr 0 r/w see table 19.2. 12 pb12dr 0 r/w 11 pb11dr 0 r/w 10 pb10dr 0 r/w 9 pb9dr 0 r/w 8 pb8dr 0 r/w 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w 0 pb0dr 0 r/w table 19.2 port b data register l (pbdrl) read/write operation ? bits 13 to 0 in pbdrl pin function pbiorl read write general input 0 pin state data can be written to pbdrl but no effect on the pin state. general output 1 pbdrl value writt en value is output from the pin. other functions * pbdrl value data can be written to pbdrl but no effect on the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 573 of 794 rej09b0237-0500 19.3 port c port c of this lsi is an i/o port wi th 21 pins as shown in figure 19.3. pc09 (input/output)/rx_er (input) pc08 (input/output)/rx_dv (input) pc07 (input/output)/mii_txd3 (output)/ duplex (output) pc06 (input/output)/mii_txd2 (output)/ crs (output) pc05 (input/output)/mii_txd1 (output)/ link (output) pc02 (input/output)/mii_rxd2 (input) pc03 (input/output)/mii_rxd3 (input) pc04 (input/output)/mii_txd0 (output)/ speed100 (output) pc01 (input/output)/mii_rxd1 (input) pc00 (input/output)/mii_rxd0 (input) pc10 (input/output)/rx_clk (input) pc11 (input/output)/tx_er (output) pc12 (input/output)/tx_en (output) pc13 (input/output)/tx_clk (input) pc14 (input/output)/col (input) pc15 (input/output)/crs (input) pc16 (input/output)/mdio (input/output) pc17 (input/output)/mdc (output) pc18 (input/output)/lnksta (input) port c pc19 (input/output)/exout (output) pc20 (input/output)/wol (output) figure 19.3 port c section 19 i/o ports rev. 5.00 mar. 15, 2007 page 574 of 794 rej09b0237-0500 19.3.1 register description port c is a 21-bit i/o port that has the following registers. for details on the addresses of these registers and the states of these re gisters in each processing state, see section 24, list of registers. ? port c data register h (pcdrh) ? port c data register l (pcdrl) 19.3.2 port c data registers h and l (pcdrh and pcdrl) pcdrh and pcdrl are 16-bit readable/writable registers that stores data for port c. bits pc20dr to pc0dr correspond to pins pc20 to pc00. (description of multiplexed functions is omitted.) when the pin function is general output port, if the value is written to pcdrh or pcdrl, the value is output from the pin; if pcdrh or pcdr l is read, the value written to the register is directly read regardle ss of the pin state. when the pin function is general input port, not the value of register but pin state is directly read if pcdrh or pcdrl is read. data can be written to pcdrh or pcdrl but no effect on the pin state. table 19.3 shows the reading/writing function of the port c data registers h and l. ? pcdrh bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 pc20dr 0 r/w see table 19.3. 3 pc19dr 0 r/w 2 pc18dr 0 r/w 1 pc17dr 0 r/w 0 pc16dr 0 r/w section 19 i/o ports rev. 5.00 mar. 15, 2007 page 575 of 794 rej09b0237-0500 ? pcdrl bit bit name initial value r/w description 15 pc15dr 0 r/w see table 19.3. 14 pc14dr 0 r/w 13 pc13dr 0 r/w 12 pc12dr 0 r/w 11 pc11dr 0 r/w 10 pc10dr 0 r/w 9 pc9dr 0 r/w 8 pc8dr 0 r/w 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w 0 pc0dr 0 r/w table 19.3 port c data registers h and l (pcdrh and pcdrl) read/write operation ? bits 4 to 0 in pcdrh and bits 15 to 0 in pcdrl pin function pbiorl read write general input 0 pin state data can be written to pcdrh or pcdrl but no effect on the pin state. general output 1 pcdrh or pcdrl value written value is output from the pin. other functions * pcdrh or pcdrl value data can be written to pcdrh or pcdrl but no effect on the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 576 of 794 rej09b0237-0500 19.4 port d port d of this lsi is an i/o port with eight pins as shown in figure 19.4. pd0 (input/output)/irq0 (input)/tend0 (output) pd1 (input/output)/irq1 (input)/tend1 (output) pd2 (input/output)/irq2 (input)/txd1 (output)/dreq0 (input) pd3 (input/output)/irq3 (input)/rxd1 (input)/dack0(output) pd4 (input/output)/irq4 (input)/sck1 (input/output) pd5 (input/output)/irq5 (input)/txd2 (output)/dreq1 (input) pd6 (input/output)/irq6 (input)/rxd2 (input)/dack0(output) pd7 (input/output)/irq7 (input)/sck2 (input/output) port d figure 19.4 port d 19.4.1 register description port d is an 8-bit i/o port that has a following register. for details on the address of this register and the states of this register in each processi ng state, see section 24 , list of registers. ? port d data register l (pddrl) 19.4.2 port d data register l (pddrl) pddrl is a 16-bit readable/writable register which stores data for port d. bits pd7dr to pd0dr correspond to pins pd7 to pd0. (descripti on of multiplexed functions is omitted.) when the pin function is general output port, if the value is written to pddrl, the value is output from the pin; if pddrl is read, the value written to the register is directly read regardless of the pin state. when the pin function is general input port, not the value of register but pin state is directly read if pddrl is read. data can be written to pddrl but no effect on the pin state. table 19.4 shows the reading/writing function of the port d data register l. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 577 of 794 rej09b0237-0500 bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 pd7dr 0 r/w see table 19.4. 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w 0 pd0dr 0 r/w table 19.4 port d data register l (pddrl) read/write operation ? bits 7 to 0 in pddrl pin function pbiorl read write general input 0 pin state data can be written to pddrl but no effect on the pin state. general output 1 pddrl value writt en value is output from the pin. other functions * pddrl value data can be written to pddrl but no effect on the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 578 of 794 rej09b0237-0500 19.5 port e port e of this lsi is an i/o port with 25 pins as shown in figure 19.5. port e pe00 (input/output)/hifebl (input)/sck_sio0 (input/output) pe01 (input/output)/hifrdy (output)/siomclk0 (input) pe02 (input/output)/hifdreq (output)/rxd_sio0 (input) pe03 (input/output)/hifmd (input) pe04 (input/output)/ hifint (output)/txd_sio0 (output) pe05 (input/output)/ hifrd (input) pe06 (input/output)/ hifwr (input)/siofsync (input/output) pe07 (input/output)/hifrs (input) pe08 (input/output)/ hifcs (input) pe09 (input/output)/hifd00 (input/output)/d16 (input/output) pe10 (input/output)/hifd01 (input/output)/d17 (input/output) pe11 (input/output)/hifd02 (input/output)/d18 (input/output) pe12 (input/output)/hifd03 (input/output)/d19 (input/output) pe13 (input/output)/hifd04 (input/output)/d20 (input/output) pe14 (input/output)/hifd05 (input/output)/d21 (input/output) pe15 (input/output)/hifd06 (input/output)/txd0 (output)/d22 (input/output) pe16 (input/output)/hifd07 (input/output)/rxd0 (input)/d23 (input/output) pe17 (input/output)/hifd08 (input/output)/sck0 (input/output)/d24 (input/output) pe18 (input/output)/hifd09 (input/output)/txd1 (output)/d25 (input/output) pe19 (input/output)/hifd10 (input/output)/rxd1 (input)/d26 (input/output) pe20 (input/output)/hifd11 (input/output)/sck1 (input/output)/d27 (input/output) pe21 (input/output)/hifd12 (input/output)/rts0 (output)/d28 (input/output) pe22 (input/output)/hifd13 (input/output)/cts0 (input)/d29 (input/output) pe23 (input/output)/hifd14 (input/output)/rts1 (output)/d30 (input/output) pe24 (input/output)/hifd15 (input/output)/cts1 (input)/d31 (input/output) figure 19.5 port e section 19 i/o ports rev. 5.00 mar. 15, 2007 page 579 of 794 rej09b0237-0500 19.5.1 register description port e is a 25-bit i/o port that has the following registers. for details on the addresses of these registers and the states of these re gisters in each processing state, see section 24, list of registers. ? port e data register h (pedrh) ? port e data register l (pedrl) 19.5.2 port e data registers h and l (pedrh and pedrl) pedrh and pedrl are 16-bit readable/writable registers that store data for port e. bits pe24dr to pe0dr correspond to pins pe24 to pe00. (description of multiplexed functions is omitted.) when the pin function is general output port, if the value is written to pedrh or pedrl, the value is output from the pin; if pedrh or pedr l is read, the value written to the register is directly read regardle ss of the pin state. when the pin function is general input port, not the value of register but pin state is directly read if pedrh or pedrl is read. data can be written to pedrh or pedrl but no effect on the pin state. table 19.5 shows the reading/writing function of the port e data registers h and l. ? pedrh bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 pe24dr 0 r/w see table 19.5. 7 pe23dr 0 r/w 6 pe22dr 0 r/w 5 pe21dr 0 r/w 4 pe20dr 0 r/w 3 pe19dr 0 r/w 2 pe18dr 0 r/w 1 pe17dr 0 r/w 0 pe16dr 0 r/w section 19 i/o ports rev. 5.00 mar. 15, 2007 page 580 of 794 rej09b0237-0500 ? pedrl bit bit name initial value r/w description 15 pe15dr 0 r/w see table 19.5. 14 pe14dr 0 r/w 13 pe13dr 0 r/w 12 pe12dr 0 r/w 11 pe11dr 0 r/w 10 pe10dr 0 r/w 9 pe9dr 0 r/w 8 pe8dr 0 r/w 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w 0 pe0dr 0 r/w table 19.5 port e data re gisters h, l (pedrh, pedr l) read/write operation ? bits 8 to 0 in pedrh and bits 15 to 0 in pedrl pin function pbiorl read write general input 0 pin state data can be written to pedrh or pedrl but no effect on the pin state. general output 1 pedrh or pedrl value written value is output from the pin. other functions * pedrh or pedrl value data can be written to pedrh or pedrl but no effect on the pin state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 581 of 794 rej09b0237-0500 19.6 usage notes 1. when pins that are multiplexed with general i/o is used as output pins for other functions, these pins work as general output pins for the period of 1 t pcyc synchronized with internal power-on reset by wdt overflow. for example, when the pin pb12/ cs3 works as cs3 and the pb12dr bit in pbdrl is set to 0, the pin is driven low for the period of 1 t pcyc and may lead to memory malfunction. to prevent this, port registers that correspond to pins used for the strobe output must be set to strobe non-active level. this case does not apply to the power-on reset from the res pin. 2. the weak keeper circuit is included in all pins except md5, md3, md2, md1, md0, asemd , testmd , extal, and xtal. the weak keeper is a circuit that fixes the input in i/o pins to low or high when the pins are not driven from outside. notes on processing the input pins are as follows: ? when using pins having the weak keeper circuit as input pins and driving these pins to a certain level from outside, adjust the resistance of pull-up/pull-down resistors to let the weak keeper circuit keep the intended levels. (2 k ? and 8 k ? are recommended respectively.) a large resistance may fail to let the weak keeper circuit to keep the intended levels. ? while using the pins having the weak keeper circuit as input pins, if their levels do not matter, there is no need to deal with pins from outside. ? md5, md3, md2, md1, md0, asemd , and testmd . drive these to intended levels from outside. since the weak keeper circuit is not included in those pins, comparatively large resistance in pull-up/pull-down resistors can be used. ? extal, and xtal see section 8.6, notes on board design in section 8, clock pulse generator (cpg). 3. since the hifmd pin is not initially set to function as a general port pin, it must be pulled up or down externally to fix its state. 4. when using a multiplexed pin with a function not selected with its initial value (for example, using the pb12/ cs3 pin, the initial function of which is pb12, as the cs3 pin), the pin must be pulled up or down externally at least after a rese t until its pin function is selected by software to fix its state. section 19 i/o ports rev. 5.00 mar. 15, 2007 page 582 of 794 rej09b0237-0500 section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 583 of 794 rej09b0237-0500 section 20 user break controller (ubc) the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data si ze, data contents, address value, and stop timing in the case of instruction fetch. 20.1 features the ubc has the following features: ? the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break: when channel a and channel b match with break conditions in the different bus cycles in that orde r, a break condition is satisfied). ? address (compares addresses 32 bits): comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc. one of the two address buses (l-bus address (lab) and i-bus address (iab)) can be selected. ? data (only on channel b, 32-bit maskable) one of the two data buses (logic data bus (ldb) and internal data bus (idb)) can be selected. ? bus cycle: instruction fetch or data access ? read/write ? operand size: byte, word, or longword ? user break interrupt is generated upon satisfying break conditions. a user-designed user-break condition interrupt exception processing routine can be run. ? in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. ? maximum repeat times for the break condition (only for channel b): 2 12 ? 1 times. ? four pairs of branch source/destination buffers. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 584 of 794 rej09b0237-0500 figure 20.1 shows a block diagram of the ubc. bbra bara bamra cpu state signal iab lab mdb access comparator address comparator channel a access comparator address comparator data comparator pc trace control channel b bbrb betr barb bamrb bbrb bdmrb brsr brdr brcr user break request ubc location ldb/idb access control bbra: break bus cycle register a bara: break address register a bamra: break address mask register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b bdrb: break data register b bdmrb: break data mask register b betr: execution times break register brsr: branch source register brdr: branch destination register brcr: break control register [legend] figure 20.1 block diagram of ubc section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 585 of 794 rej09b0237-0500 20.2 register descriptions the user break controller has the following regist ers. for details on register addresses and access sizes, refer to section 24, list of registers. ? break address register a (bara) ? break address mask register a (bamra) ? break bus cycle register a (bbra) ? break address register b (barb) ? break address mask register b (bamrb) ? break bus cycle register b (bbrb) ? break data register b (bdrb) ? break data mask register b (bdmrb) ? break control register (brcr) ? execution times break register (betr) ? branch source register (brsr) ? branch destination register (brdr) 20.2.1 break address register a (bara) bara is a 32-bit readable/writable register. bara specifies the addr ess used for a break condition in channel a. bit bit name initial value r/w description 31 to 0 baa31 to baa 0 all 0 r/w break address a store the address on the la b or iab specifying break conditions of channel a. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 586 of 794 rej09b0237-0500 20.2.2 break address ma sk register a (bamra) bamra is a 32-bit readable/writable register. bamr a specifies bits masked in the break address specified by bara. bit bit name initial value r/w description 31 to 0 bama31 to bama 0 all 0 r/w break address mask a specify bits masked in the channel a break address bits specified by bara (baa31 to baa0). 0: break address bit baan of channel a is included in the break condition 1: break address bit baan of channel a is masked and is not included in the break condition note: n = 31 to 0 20.2.3 break bus cycl e register a (bbra) break bus cycle register a (bbra) is a 16-bit read able/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruc tion fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel a. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 cda1 cda0 0 0 r/w r/w l bus cycle/i bus cycle select a select the l bus cycle or i bus cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 587 of 794 rej09b0237-0500 bit bit name initial value r/w description 5 4 ida1 ida0 0 0 r/w r/w instruction fetch/data access select a select the instruction fetch cycle or data access cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwa1 rwa0 0 0 r/w r/w read/write select a select the read cycle or write cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 sza1 sza0 0 0 r/w r/w operand size select a select the operand size of the bus cycle for the channel a break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access 20.2.4 break addres s register b (barb) barb is a 32-bit readable/writable register. barb specifies the addr ess used for a break condition in channel b. bit bit name initial value r/w description 31 to 0 bab31 to bab 0 all 0 r/w break address b store an address of lab or iab which specifies a break condition in channel b. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 588 of 794 rej09b0237-0500 20.2.5 break address ma sk register b (bamrb) bamrb is a 32-bit readable/writable register. bam rb specifies bits masked in the break address specified by barb. bit bit name initial value r/w description 31 to 0 bamb31 to bamb 0 all 0 r/w break address mask b specify bits masked in the break address of channel b specified by barb (bab31 to bab0). 0: break address babn of channel b is included in the break condition 1: break address babn of channel b is masked and is not included in the break condition note: n = 31 to 0 20.2.6 break data register b (bdrb) bdrb is a 32-bit readable/writable register. bd br selects data used for a break condition in channel b. bit bit name initial value r/w description 31 to 0 bdb31 to bdb 0 all 0 r/w break data bit b store data which specifies a break condition in channel b. bdrb specifies the break data on ldb or idb. notes: 1. specify an operated size when includ ing the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte must be set in bits 15 to 8 and 7 to 0 in bdrb as the break data. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 589 of 794 rej09b0237-0500 20.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit readable/writable register. bdmrb specifies bits masked in the break data specified by bdrb. bit bit name initial value r/w description 31 to 0 bdmb31 to bdmb 0 all 0 r/w break data mask b specify bits masked in the break data of channel b specified by bdrb (bdb31 to bdb0). 0: break data bdbn of channel b is included in the break condition 1: break data bdbn of channel b is masked and is not included in the break condition note: n = 31 to 0 notes: 1. specify an operated size when includ ing the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break mask data. 20.2.8 break bus cycl e register b (bbrb) break bus cycle register b (bbrb) is a 16-bit read able/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruct ion fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel b. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 590 of 794 rej09b0237-0500 bit bit name initial value r/w description 7 6 cdb1 cdb0 0 0 r/w r/w l bus cycle/i bus cycle select b select the l bus cycle or i bus cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle 5 4 idb1 idb0 0 0 r/w r/w instruction fetch/data access select b select the instruction fetch cy cle or data access cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwb1 rwb0 0 0 r/w r/w read/write select b select the read cycle or write cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 szb1 szb0 0 0 r/w r/w operand size select b select the operand size of the bus cycle for the channel b break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 591 of 794 rej09b0237-0500 20.2.9 break control register (brcr) brcr sets the following conditions: ? channels a and b are used in two independent channel conditions or under the sequential condition. ? a break is set before or after instruction execution. ? specify whether to include th e number of execution times on channel b in comparison conditions. ? specify whether to include data bus on channel b in comparison conditions. ? enable pc trace. the break control register (brcr) is a 32-bit read able/writable register that has break conditions match flags and bits for setting a variety of break conditions. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 scmfca 0 r/w l bus cycle condition match flag a when the l bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. 0: the l bus cycle condition fo r channel a does not match 1: the l bus cycle conditio n for channel a matches 14 scmfcb 0 r/w l bus cycle condition match flag b when the l bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. 0: the l bus cycle condition fo r channel b does not match 1: the l bus cycle conditio n for channel b matches section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 592 of 794 rej09b0237-0500 bit bit name initial value r/w description 13 scmfda 0 r/w i bus cycle condition match flag a when the i bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. 0: the i bus cycle condition for channel a does not match 1: the i bus cycle condition for channel a matches 12 scmfdb 0 r/w i bus cycle condition match flag b when the i bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1 (not cleared to 0). in order to clear this flag, write 0 into this bit. 0: the i bus cycle condition for channel b does not match 1: the i bus cycle condition for channel b matches 11 pcte 0 r/w pc trace enable 0: disables pc trace 1: enables pc trace 10 pcba 0 r/w pc break select a selects the break timing of th e instruction fetch cycle for channel a as before or after instruction execution. 0: pc break of channel a is set before instruction execution 1: pc break of channel a is set after instruction execution 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 dbeb 0 r/w data break enable b selects whether or not the data bus condition is included in the break condition of channel b. 0: no data bus condition is included in the condition of channel b 1: the data bus condition is included in the condition of channel b section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 593 of 794 rej09b0237-0500 bit bit name initial value r/w description 6 pcbb 0 r/w pc break select b selects the break timing of th e instruction fetch cycle for channel b as before or after instruction execution. 0: pc break of channel b is set before instruction execution 1: pc break of channel b is set after instruction execution 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 seq 0 r/w sequence condition select selects two conditions of channels a and b as independent or sequential conditions. 0: channels a and b are compared under independent conditions 1: channels a and b are compared under sequential conditions (channel a, then channel b) 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 etbe 0 r/w number of execution times break enable enables the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by betr. 0: the execution-times break condition is disabled on channel b 1: the execution-times break condition is enabled on channel b section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 594 of 794 rej09b0237-0500 20.2.10 execution times break register (betr) betr is a 16-bit readable/writable register. when the execution-times break condition of channel b is enabled, this register specifies the numb er of execution times to make the break. the maximum number is 2 12 ? 1 times. every time the break condition is satisfied, betr is decremented by 1. a break is i ssued when the break condition is satisfied after betr becomes h'0001. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 bet11 to bet0 all 0 r/w number of execution times 20.2.11 branch source register (brsr) brsr is a 32-bit read-only register. brsr stores bits 27 to 0 in the address of the branch source instruction. brsr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brsr is read, the setting to enable pc trace is made, or brsr is initialized by a power-on reset. other bits are not initialized by a power-o n reset. the four brsr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 svf 0 r brsr valid flag indicates whether or not the branch source address is stored. when a branch is made, this flag is set to 1. this flag is cleared to 0 by one of the following conditions: when this flag is read from this register, when pc trace is enabled, and when a power-on reset is generated. 0: the value of brsr register is invalid 1: the value of brsr register is valid section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 595 of 794 rej09b0237-0500 bit bit name initial value r/w description 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bsa27 to bsa0 undefined r branch source address store bits 27 to 0 of the branch source address. 20.2.12 branch destination register (brdr) brdr is a 32-bit read-only register. brdr stores bits 27 to 0 in the address of the branch destination instruction. brdr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brdr is read, the setting to enab le pc trace is made, or brdr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the four brdr registers have a queue structure and a stored regi ster is shifted at every branch. bit bit name initial value r/w description 31 dvf 0 r brdr valid flag indicates whether or not the branch source address is stored. when a branch is made, this flag is set to 1. this flag is cleared to 0 by one of the following conditions: when this flag is read from this register, when pc trace is enabled, and when a power-on reset is generated. 0: the value of brdr register is invalid 1: the value of brdr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bda27 to bda0 undefined r branch destination address store bits 27 to 0 of the branch destination address. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 596 of 794 rej09b0237-0500 20.3 operation 20.3.1 flow of user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses are set in the break address registers (bara and barb). the masked addresses are set in th e break address mask registers (b amra and bamrb). the break data is set in the break data register (bdrb). the mask ed data is set in the break data mask register (bdmrb). the bus break conditions are set in the break bus cycle registers (bbra and bbrb). there are three control bit combinations in both bbra and bbrb: bits to select l- bus cycle or i-bus cycle, bits to select instruction fetch or data acce ss, and bits to select read or write. no user break will be generated if one of these combinations is set to b'00. the respective conditions are set in the bits of the br eak control register (brcr). make sure to set all registers related to breaks before setting bbra/bbrb. 2. when the break conditions are satisfied, the ubc sends a user break request to the cpu and sets the l bus condition match flag (scmfca or scmfcb) and the i bus condition match flag (scmfda or scmfdb) for the appropriate channel. 3. the appropriate condition match flags (s cmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags. reset the flags by writing 0 before they are used again. 4. there is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one br eak request to the cpu, but these two break channel match flags could be both set. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 597 of 794 rej09b0237-0500 20.3.2 break on inst ruction fetch cycle 1. when l bus/instruction fetch/read/word or lo ngword is set in the break bus cycle register (bbra/bbrb), the break condition becomes the l bus instruction fetch cycle. whether it breaks before or after the execution of the instruction can then be selected with the pcba/pcbb bit of the break cont rol register (brcr) for the appropriate channel. if an instruction fetch cycle is set as a break condi tion, clear lsb in the break address register (bara/barb) to 0. a break cannot be generated as long as this bit is set to 1. 2. if the condition is matched while a break before execution is selected, a break is generated when it is confirmed that the instruction has been fetched and it will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be ex ecuted). when this kind of break is set in the delay slot of a delayed branch instruction, the break is generated immediately before the execution of the instruc tion that first accepts the break. meanwhile, a break before the execution of the instruction in a delay slot and a break after the execution of the sleep instruction are also prohibited. 3. when a break after execution is selected, the instruction that matches the break condition is executed and then the break is generated prior to the execution of the next instruction. as with a break before execution, this can not be used with overrun fetch instructions. when this kind of break is set for a delayed branch instruction, a break is not generated until the first instruction at which breaks are accepted. 4. when an instruction fetch cycle is set for channel b, the break data register b (bdrb) is ignored. there is thus no need to set break data for the break of the instruction fetch cycle. 20.3.3 break on data access cycle ? the bus cycles in which l bus data acces s breaks occur are from instructions. ? the relationship between the data access cycle address and the comparison condition for each operand size is listed in table 20.1. table 20.1 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31 to 2 to address bus bits 31 to 2 word compares break address register bits 31 to 1 to address bus bits 31 to 1 byte compares break address register bits 31 to 0 to address bus bits 31 to 0 section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 598 of 794 rej09b0237-0500 this means that when address h'00001003 is set in the break address register (bara or barb), for example, the bus cycle in which th e break condition is satisfied is as follows (where other conditions are met). ? longword access at h'00001000 ? word access at h'00001002 ? byte access at h'00001003 ? when the data value is included in the break conditions on channel b: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (bbra and bbrb). in this case, a break is generated when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31 to 16 of bdrb and bdmrb are ignored. 20.3.4 sequential break ? by setting the seq bit in brcr to 1, the sequential break is issued when a channel b break condition matches after a channel a break conditio n matches. a user break is not generated even if a channel b break condition matches before a channel a break condition matches. when channels a and b break conditions match at the same time, the sequential break is not issued. to clear the channel a condition match when a channel a condition match has occurred but a channel b condition match has not yet occurred in a sequential break specification, clear the seq bit in brcr to 0. ? in sequential break specification, the l- or i-bus can be selected and the execution times break condition can be also specifi ed. for example, when the ex ecution times break condition is specified, the break is generated when a channel b condition matches with betr = h'0001 after a channel a condition has matched. 20.3.5 value of saved program counter (pc) when a break occurs, pc is saved onto the stack. the pc value saved is as follows depending on the type of break. ? when a break before execution is selected: the value of the program counter (pc) saved is the address of the instruction that matches the break condition. the fetched instruction is no t executed, and a break occurs before it. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 599 of 794 rej09b0237-0500 ? when a break after execution is selected: the pc value saved is the address of the instruc tion to be executed following the instruction in which the break condition matches. the fetched instruction is executed, and a break occurs before the execution of the next instruction. ? when an address in a data access cycle is specified as a break condition: the pc value is the address of the instruction to be executed following the instruction that matched the break condition. the instruction that matched the condition is executed and the break occurs before the next instruction is executed. ? when an address and data in a data access cycle are specified as a break condition: the pc value is the start address of the instruc tion that follows the instruction already executed when break processing started. when a data value is added to the break conditions, the break will occur before the execution of an instruction that is within two instructions of the instruction that matched the break condition. therefore, where the break will occur cannot be specified exactly. 20.3.6 pc trace ? setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, and interrupt) is generated, the branch source addres s and branch destination address are stored in brsr and brdr, respectively. ? the branch source address has different values due to the kind of branch. ? branch instruction the branch instruction address. ? interrupt and exception the address of the in struction in which the interrupt or exception was accepted. this address is equal to the return address saved onto the stack. the start address of the interrupt or excepti on handling routine is stored in brdr. the trapa instruction belongs to interrupt and exception above. ? brsr and brdr have four pairs of queue structur es. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shif ts after brdr is read. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 600 of 794 rej09b0237-0500 20.3.7 usage examples break condition specified for l bus instruction fetch cycle: ? register specifications bara = h'00000404, bamra = h'00000000, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300400 specified conditions: channel a/channel b independent mode ? channel a address: h'00000404, address mask: h'00000000 bus cycle: l bus/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fe tch (before instruction executi on)/read (operand size is not included in the condition) a user break occurs after an instruction of address h'00000404 is executed or before instructions of addresses h'00008010 to h'00008016 are executed. ? register specifications bara = h'00037226, bamra = h'00000000 , bbra = h'0056, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000008 specified conditions: channel a/channel b sequential mode ? channel a address: h'00037226, address mask: h'00000000 bus cycle: l bus/instruction fetch (before instruction execution)/read/word ? channel b address: h'0003722e, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (b efore instruction execution)/read/word after address h'00037226 is executed, a user break occurs before an instruction of address h'0003722e is executed. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 601 of 794 rej09b0237-0500 ? register specifications bara = h'00027128, bamra = h'000000 00, bbra = h'005a, barb = h'00031415, bamrb = h'00000000, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300000 specified conditions: channel a/channel b independent mode ? channel a address: h'00027128, address mask: h'00000000 bus cycle: l bus/instruction fetch (b efore instruction ex ecution)/write/word the asid check is not included. ? channel b address: h'00031415, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fe tch (before instruction executi on)/read (operand size is not included in the condition) on channel a, no user break occurs since instru ction fetch is not a write cycle. on channel b, no user break occurs since instruction fetch is performed for an even address. ? register specifications bara = h'00037226, bamra = h'000000 00, bbra = h'005a, barb = h'0003722e, bamrb = h'00000000, bbrb = h'0056, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000008 specified conditions: channel a/channel b sequential mode ? channel a address: h'00037226, address mask: h'00000000 bus cycle: l bus/instruction fetch (b efore instruction ex ecution)/write/word ? channel b address: h'0003722e, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (b efore instruction execution)/read/word since instruction fetch is not a write cycle on channel a, a sequential condition does not match. therefore, no user break occurs. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 602 of 794 rej09b0237-0500 ? register specifications bara = h'00000500, bamra = h'00000000, bbra = h'0057, barb = h'00001000, bamrb = h'00000000, bbrb = h'0057, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300001, betr = h'0005 specified conditions: channel a/channel b independent mode ? channel a address: h'00000500, address mask: h'00000000 bus cycle: l bus/instruction fetch (bef ore instruction execu tion)/read/longword the asid check is not included. ? channel b address: h'00001000, address mask: h'00000000 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (bef ore instruction execu tion)/read/longword the number of exec ution-times break enable (5 times) on channel a, a user break occurs before an instruction of address h'00000500 is executed. on channel b, a user break occurs after the instruction of address h'00001000 are executed four times and before the fifth time. ? register specifications bara = h'00008404, bamra = h'00000fff, bbra = h' 0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00000400 specified conditions: channel a/channel b independent mode ? channel a address: h'000 08404, address mask: h'00000fff bus cycle: l bus/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) ? channel b address: h'00008010, address mask: h'00000006 data: h'00000000, data mask: h'00000000 bus cycle: l bus/instruction fetch (before in struction execution)/read (operand size is not included in the condition) a user break occurs after an instruction of addresses h'00008000 to h'00008ffe is executed or before an instruction of addresses h'00008010 to h'00008016 is executed. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 603 of 794 rej09b0237-0500 break condition specified fo r l bus data access cycle: ? register specifications bara = h'00123456, bamra = h'00000000 , bbra = h'0064, barb = h'000abcde, bamrb = h'000000ff, bbrb = h'006a, bdrb = h'0000a512, bdmrb = h'00000000, brcr = h'00000080 specified conditions: channel a/channel b independent mode ? channel a address: h'00123456, address mask: h'00000000, asid = h'80 bus cycle: l bus/data access/ read (operand size is not included in the condition) ? channel b address: h'000abcde, address mask: h'000000ff data: h'0000a512, data mask: h'00000000 bus cycle: l bus/da ta access/write/word on channel a, a user break occurs with longword read from address h'00123454, word read from address h'00123456, or byte read from address h'00123456. on channel b, a user break occurs when word h'a512 is written in addresses h'000abc00 to h'000abcfe. break condition specified fo r i bus data access cycle: ? register specifications: bara = h'00314156, bamra = h'00000000, bbra = h'0094, barb = h'00055555, bamrb = h'00000000, bbrb = h'00a9, bdrb = h'00007878, bdmrb = h'00000f0f, brcr = h'00000080 specified conditions: channel a/channel b independent mode ? channel a address: h'00314156, address mask: h'00000000, asid = h'80 bus cycle: i bus/instruction fetch/read (opera nd size is not included in the condition) ? channel b address: h'00055555, address mask: h'00000000, asid = h'70 data: h'00000078, data mask: h'0000000f bus cycle: i bus/data access/write/byte on channel a, a user break occurs when instruction fetch is performed for address h'00314156 in the memory space. on channel b, a user break occurs when th e i bus writes byte data h'7* in address h'00055555. section 20 user break controller (ubc) rev. 5.00 mar. 15, 2007 page 604 of 794 rej09b0237-0500 20.3.8 notes 1. the cpu reads from or writes to the ubc registers via the i bus. a desired break may not occur until the instruction to rewrite the ubc registers are executed and the actual values are reflected. in order to know the timing the ubc register is changed, read the last written register. instructions after then are valid for the newly written register value. 2. ubc cannot monitor access to the l bu s and i bus in the same channel. 3. note on specification of sequential break: a condition match occurs when a b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no break occurs even if a bus cycle, in which an a-channel match and a channel b match occur simultaneously, is set. 4. when user breaks and other exceptions occur by the same instruction, they are handled according to the priority listed in table 5.1 of section 5, exception handling. when an exception with a higher priority is generated, no user break occurs. ? a break before the execution of an instructio n is accepted with a priority over other exceptions. ? when a break after the execution of an instruction or a data access break occurs simultaneously with a re-execution-type exception with a higher priority (including a break before the execution of an in struction), the re-execution-type exception is accepted and the condition match flag is not set (however, there is an exception as explained in 5. of section 20.3.8, notes). when the exception source of th e re-execution type is cleared by exception handling and the same instruction is executed again and completed, the break is generated again and the flag is set. ? when a break after the execution of an instruction or a data access break occurs simultaneously with a completion-type exception with a higher priority (trapa), no break occurs but the condition match flag is set. 5. note on exception of 4. of section 20.3.8, notes when a break after the execution of an instru ction or a data access break occurs during the execution of the instruct ion in which a cpu address error is generated by data access, the cpu address error has a priority over the break and occurs before the break. the condition match flag is also set at this time. 6. note when a break o ccurs in the delay slot when a break before the execution of an instruction is set to the delay slot instruction of the rte instruction, the break does not occur before executing the branch destination of the rte instruction. 7. user breaks are disabled during usb module standby mode. do not read from or write to the ubc registers during usb module standby mode; the values ar e not guaranteed. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 605 of 794 rej09b0237-0500 section 21 user debu gging interface (h-udi) this lsi incorporates a user debugging interf ace (h-udi) to provide a boundary scan function and emulator support. this section describes the boundary scan function of the h-udi. for details on emulator functions of the h-udi, refer to the user's manual of the re levant emulator. 21.1 features the h-udi is a serial i/o interface which conforms to jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary-scan architecture) specifications. the h-udi in this lsi supports a boundary scan function, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the emulator manual for the method of conn ecting the emulator. figure 21.1 shows a block diagram of the h-udi. sdir sdid tck tdo tdi tms t rst sdbpr mux sdbsr shift register tap controller decoder local bus [legend] sdbpr: bypass register sdbsr: boundary scan register sdir: instruction register sdid: id register figure 21.1 block diagram of h-udi section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 606 of 794 rej09b0237-0500 21.2 input/output pins table 21.1 shows the pin configuration of the h-udi. table 21.1 pin configuration abbr. input/output description tck input serial data input/output clock pin data is serially supplied to the h-udi from the data input pin (tdi) and output from the data output pin (tdo) in synchronization with this clock. tms input mode select input pin the state of the tap control circuit is determined by changing this signal in synchronization with tck. the protocol conforms to the jtag standard (ieee std.1149.1). trst input reset input pin input is accepted asynchronously with respect to tck, and when low, the h-udi is reset. trst must be low for the given period when the power is turned on regardless of using the h- udi function. this is differe nt from the jtag standard. for details on resets, see section 21.4.2, reset configuration. tdi input serial data input pin data transfer to the h-udi is executed by changing this signal in synchronization with tck. tdo output serial data output pin data read from the h-udi is executed by reading this pin in synchronization with tck. the data output timing depends on the command type set in sdir. for details, see section 21.3.2, instruction register (sdir). asemd input ase mode select pin when a low level is input to the asemd pin, ase mode is entered; if a high level is inpu t, normal mode is entered. in ase mode, the emulator functions c an be used. the input level on the asemd pin should be held except during the res pin assertion period. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 607 of 794 rej09b0237-0500 21.3 register descriptions the h-udi has the following registers. for details on the addresses of these registers and the states of these registers in each processing state, see sect ion 24, list of registers. ? bypass register (sdbpr) ? instruction register (sdir) ? boundary scan register (sdbsr) ? id register (sdid) 21.3.1 bypass register (sdbpr) sdbpr is a 1-bit register that cannot be accessed by the cpu. when sdir is set to the bypass mode, sdbpr is connected between h-udi pins (tdi and tdo). the initial value is undefined. 21.3.2 instruction register (sdir) sdir is a 16-bit read-only register . this register is in jtag idcode in its initial state. it is initialized by trst assertion or in the tap test-logic-reset state, and can be written to by the h- udi irrespective of the cpu mode. operation is not guaranteed if a reserved command is set in this register. bit bit name initial value r/w description 15 to 13 ti7 to ti5 all 1 r 12 ti4 0 r 11 to 8 ti3 to ti0 all 1 r test instruction 7 to 0 the h-udi instruction is transferred to sdir by a serial input from tdi. for commands, see table 21.2. 7 to 2 ? all 1 r reserved these bits are always read as 1. 1 ? 0 r reserved this bit is always read as 0. 0 ? 1 r reserved this bit is always read as 1. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 608 of 794 rej09b0237-0500 table 21.2 h-udi commands bits 15 to 8 ti7 ti6 ti5 ti4 ti3 ti 2 ti1 ti0 description 0 0 0 0 ? ? ? ? jtag extest 0 0 1 0 ? ? ? ? jtag clamp 0 0 1 1 ? ? ? ? jtag highz 0 1 0 0 ? ? ? ? jtag sample/preload 0 1 1 0 ? ? ? ? h-udi reset, negate 0 1 1 1 ? ? ? ? h-udi reset, assert 1 0 1 ? ? ? ? ? h-udi interrupt 1 1 1 0 ? ? ? ? jtag idcode (initial value) 1 1 1 1 ? ? ? ? jtag bypass other than above reserved 21.3.3 boundary scan register (sdbsr) sdbsr is a 333-bit shift register, located on the pa d, for controlling the input/output pins of this lsi. the initial value is undefined. this register cannot be accessed by the cpu. using the extest, sample/preload, clamp, and highz commands, a boundary scan test conforming to the jtag standard can be carried out. table 21.3 s hows the correspondence between this lsi's pins and boundary scan register bits. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 609 of 794 rej09b0237-0500 table 21.3 external pins and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 303 pe02/hifdreq/rxd_sio0/- in 332 pd06/irq6/rxd2/dack1 in 302 pe01/hifrdy/siomclk0/- in 331 pd05/irq5/txd2/dreq1 in 301 pe00/hifebl/sck_sio0/- in 330 pd04/irq4/sck1/- in 300 pc17/mdc/-/- in 329 pd03/irq3/rxd1/dack0 in 299 pc16/mdio/-/- in 328 pd02/irq2/txd1/dreq0 in 298 pc15/crs/-/- in 327 pd01/irq1/-/tend1 in 297 pc18/lnksta in 326 pd00/irq0/-/tend0 in 296 pd06/irq6/rxd2/dack1 out 325 pe08/ hifcs in 295 pd05/irq5/txd2/dreq1 out 324 pe24/hifd15/cts1/d31 in 294 pd04/irq4/sck1/- out 323 pe23/hifd14/rts1/d30 in 293 pd03/irq3/rxd1/dack0 out 322 pe22/hifd13/cts0/d29 in 292 pd02/irq2/txd1/dreq0 out 321 pe21/hifd12/rts0/d28 in 291 pd01/irq1/-/tend1 out 320 pe20/hifd11/sck1/d27 in 290 pd00/irq0/-/tend0 out 319 pe19/hifd10/rxd1/d26 in 289 pe08/ hifcs out 318 pe18/hifd09/txd1/d25 in 288 pe24/hifd15/cts1/d31 out 317 pe17/hifd08/sck0/d24 in 287 pe23/hifd14/rts1/d30 out 316 pe16/hifd07/rxd0/d23 in 286 pe22/hifd13/cts0/d29 out 315 pe15/hifd06/txd0/d22 in 285 pe21/hifd12/rts0/d28 out 314 pe14/hifd05/-/d21 in 284 pe20/hifd11/sck1/d27 out 313 pe13/hifd04/-/d20 in 283 pe19/hifd10/rxd1/d26 out 312 pe12/hifd03/-/d19 in 282 pe18/hifd09/txd1/d25 out 311 pe11/hifd02/-/d18 in 281 pe17/hifd08/sck0/d24 out 310 pe10/hifd01/-/d17 in 280 pe16/hifd07/rxd0/d23 out 309 pe09/hifd00/-/d16 in 279 pe15/hifd06/txd0/d22 out 308 pe07/hifrs in 278 pe14/hifd05/-/d21 out 307 pe06/ hifwr /siofsync0/- in 277 pe13/hifd04/-/d20 out 306 pe05/ hifrd in 276 pe12/hifd03/-/d19 out 305 pe04/ hifint /txd_sio0/- in 275 pe11/hifd02/-/d18 out 304 pe03/hifmd in 274 pe10/hifd01/-/d17 out section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 610 of 794 rej09b0237-0500 bit pin name i/o bit pin name i/o 273 pe09/hifd00/-/d16 out 241 pe13/hifd04/-/d20 control 272 pe07/hifrs out 240 pe12/ hifd03/-/d19 control 271 pe06/ hifwr /siofsync0/- out 239 pe11/hifd02/-/d18 control 270 pe05/ hifrd out 238 pe10/hifd01/-/d17 control 269 pe04/ hifint /txd_sio0/- out 237 pe09/hifd00/-/d16 control 268 pe03/hifmd out 236 pe07/hifrs control 267 pe02/hifdreq/rxd_sio0/- out 235 pe06/ hifwr /siofsync0/- control 266 pe01/hifrdy/siomclk0/- out 234 pe05/ hifrd control 265 pe00/hifebl/sck_sio0/- out 233 pe04/ hifint /txd_sio0/- control 264 pc17/mdc/-/- out 232 pe03/hifmd control 263 pc16/mdio/-/- out 231 pe02/hifdreq/rxd_sio0/- control 262 pc15/crs/-/- out 230 pe01/hifrdy/siomclk0/- control 261 pc18/lnksta out 229 pe00/hifebl/sck_sio0/- control 260 pd06/irq6/rxd2/dack1 control 228 pc17/mdc/-/- control 259 pd05/irq5/txd2/dreq1 control 227 pc16/mdio/-/- control 258 pd04/irq4/sck1/- control 226 pc15/crs/ control 257 pd03/irq3/rxd1/dack0 control 225 pc18/lnksta control 256 pd02/irq2/txd1/dreq0 control 224 pc09/rx_er/-/- in 255 pd01/irq1/-/tend1 control 223 pc08/rx_dv/-/- in 254 pd00/irq0/-/tend0 control 222 pc00/miirxd0/-/- in 253 pe08/ hifcs control 221 pc01/miirxd1/-/- in 252 pe24/hifd15/cts1/d31 control 220 pc02/miirxd2/-/- in 251 pe23/hifd14/rts1/d30 control 219 pc03/miirxd3/-/- in 250 pe22/hifd13/cts0/d29 control 218 pc10/rx_clk/-/- in 249 pe21/hifd12/rts0/d28 control 217 pc11/tx_er/-/- in 248 pe20/hifd11/sck1/d27 control 216 pc13/tx_clk/-/- in 247 pe19/hifd10/rxd1/d26 control 215 pc04/miitxd0/-/ speed100 in 246 pe18/hifd09/txd1/d25 control 214 pc05/miitxd1/-/ link in 245 pe17/hifd08/sck0/d24 control 213 pc06/miitxd2/-/ crs in 244 pe16/hifd07/rxd0/d23 control 212 pc07/miitxd3/-/ duplex in 243 pe15/hifd06/txd0/d22 control 211 pc12/tx_en/-/- in 242 pe14/hifd05/-/d21 control 210 pc14/col/-/- in section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 611 of 794 rej09b0237-0500 bit pin name i/o bit pin name i/o 209 pc20/wol in 177 pc04/miitxd0/-/ speed100 control 208 pc19/exout in 176 pc05/miitxd1/-/ link control 207 md3 in 175 pc06/miitxd2/-/ crs control 206 md5 in 174 pc07/miitxd3/-/ duplex control 205 testmd in 173 pc12/tx_en/-/- control 204 pc09/rx_er/-/- out 172 pc14/col/-/- control 203 pc08/rx_dv/-/- out 171 pc20/wol control 202 pc00/miirxd0/-/- out 170 pc19/exout control 201 pc01/miirxd1/-/- out 169 testout control 200 pc02/miirxd2/-/- out 168 md0 in 199 pc03/miirxd3/-/- out 167 nmi in 198 pc10/rx_clk/-/- out 166 md1 in 197 pc11/tx_er/-/- out 165 md2 in 196 pc13/tx_clk/-/- out 164 d00 in 195 pc04/miitxd0/-/ speed100 out 163 d01 in 194 pc05/miitxd1/-/ link out 162 d02 in 193 pc06/miitxd2/-/ crs out 161 d03 in 192 pc07/miitxd3/-/ duplex out 160 d04 in 191 pc12/tx_en/-/- out 159 d05 in 190 pc14/col/-/- out 158 d06 in 189 pc20/wol out 157 d07 in 188 pc19/exout out 156 d15 in 187 testout out 155 d14 in 186 pc09/rx_er/-/- control 154 d13 in 185 pc08/rx_dv/-/- control 153 d12 in 184 pc00/miirxd0/-/- control 152 d11 in 183 pc01/miirxd1/-/- control 151 d10 in 182 pc02/miirxd2/-/- control 150 d09 in 181 pc03/miirxd3/-/- control 149 d08 in 180 pc10/rx_clk/-/- control 148 pb02/cke in 179 pc11/tx_er/-/- control 147 pb03/ cas in 178 pc13/tx_clk/-/- control 146 pb04/ ras in section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 612 of 794 rej09b0237-0500 bit pin name i/o bit pin name i/o 145 d00 out 115 d15 control 144 d01 out 114 d14 control 143 d02 out 113 d13 control 142 d03 out 112 d12 control 141 d04 out 111 d11 control 140 d05 out 110 d10 control 139 d06 out 109 d09 control 138 d07 out 108 d08 control 137 d15 out 107 we0 , dqmll control 136 d14 out 106 we1 , dqmlu, we control 135 d13 out 105 rdwr control 134 d12 out 104 pb02/cke control 133 d11 out 103 pb03/ cas control 132 d10 out 102 pb04/ ras control 131 d09 out 101 pb12/ cs3 in 130 d08 out 100 pb13/ bs in 129 we0 , dqmll out 99 pb11/ cs4 in 128 we1 , dqmlu, we out 98 pb00/ wait in 127 rdwr out 97 pb05/ we2(be2) /dqmul/ iciord in 126 pb02/cke out 96 pb06/ we3(be3) /dqmuu/ iciowr in 125 pb03/ cas out 95 pb01/ iois16 in 124 pb04/ ras out 94 pb09/ ce2a in 123 d00 control 93 pb10/ cs5b , ce1a in 122 d01 control 92 pb07/ ce2b in 121 d02 control 91 pb08/ cs6b , ce1b in 120 d03 control 90 pa16/a16 in 119 d04 control 89 pa17/a17 in 118 d05 control 88 pa18/a18 in 117 d06 control 87 pa19/a19 in 116 d07 control 86 pa20/a20 in section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 613 of 794 rej09b0237-0500 bit pin name i/o bit pin name i/o 85 pa21/a21/sck_sio0/- in 56 pb06/ we3(be3) /dqmuu/ iciowr out 84 pa22/a22/siomclk0/- in 55 pb01/ iois16 out 83 pa23/a23/rxd_sio0/- in 54 pb09/ ce2a out 82 pa24/a24/txd_sio0/- in 53 pb10/ cs5b , ce1a out 81 pa25/a25/siofsync0/- in 52 pb07/ ce2b out 80 pd07/irq7/sck2/- in 51 pb08/ cs6b , ce1b out 79 pb12/ cs3 out 50 pa16/a16 out 78 a00 out 49 pa17/a17 out 77 a01 out 48 pa18/a18 out 76 a02 out 47 pa19/a19 out 75 a03 out 46 pa20/a20 out 74 a04 out 45 pa21/a21/sck_sio0/- out 73 a05 out 44 pa22/a22/siomclk0/- out 72 a06 out 43 pa23/a23/rxd_sio0/- out 71 a07 out 42 pa24/a24/txd_sio0/- out 70 a08 out 41 pa25/a25/siofsync0/- out 69 a09 out 40 pd07/irq7/sck2/- out 68 a10 out 39 pb12/ cs3 control 67 a11 out 38 a00 control 66 a12 out 37 a01 control 65 a13 out 36 a02 control 64 a14 out 35 a03 control 63 a15 out 34 a04 control 62 pb13/ bs out 33 a05 control 61 cs0 out 32 a06 control 60 pb11/ cs4 out 31 a07 control 59 rd out 30 a08 control 58 pb00/ wait out 29 a09 control 57 pb05/ we2(be2) /dqmul/ iciord out 28 a10 control section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 614 of 794 rej09b0237-0500 bit pin name i/o bit pin name i/o 27 a11 control 12 pb07/ ce2b control 26 a12 control 11 pb08/ cs6b , ce1b control 25 a13 control 10 pa16/a16 control 24 a14 control 9 pa17/a17 control 23 a15 control 8 pa18/a18 control 22 pb13/ bs control 7 pa19/a19 control 21 cs0 control 6 pa20/a20 control 20 pb11/ cs4 control 5 pa21/a21/sck_sio0/- control 19 rd control 4 pa22/a22/siomclk0/- control 18 pb00/ wait control 3 pa23/a23/rxd_sio0/- control 17 pb05/ we2(be2) / dqmul/ iciord control 2 pa24/a24/txd_sio0/- control 16 pb06/ we3(be3) / dqmuu/ iciowr control 1 pa25/a25/siofsync0/- control 15 pb01/ iois16 control 0 pd07/irq7/sck2/- control 14 pb09/ ce2a control to tdo 13 pb10/ cs5b , ce1a control note: * control means a low active signal. the corresponding pin is driven with an out value when the control is driven low. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 615 of 794 rej09b0237-0500 21.3.4 id register (sdid) sdid is a 32-bit read-only register in which sd idh and sdidl are connected. each register is a 16-bit that can be read by the cpu. to read this register by the h-udi side, the contents can be read via the tdo pin when the idcode command is set and the tap state is shift-dr. writing is disabled. bit bit name initial value r/w description 31 to 0 did31 to did0 refer to description r device id 31 to device id 0 id register that is sti pulated by jtag. h'0800c447 (initial value) for this lsi. upper four bits may be changed according to the lsi version. sdidh corresponds to bits 31 to 16. sdidl corresponds to bits 15 to 0. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 616 of 794 rej09b0237-0500 21.4 operation 21.4.1 tap controller figure 21.2 shows the internal states of the tap controller. state transiti ons basically conform to the jtag standard. test-logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 0 1 0 1 1 1 0 figure 21.2 tap controller state transitions note: the transition condition is the tms value at the rising edge of the tck signal. the tdi value is sampled at the rising edge of the tck signal and is shifted at the falling edge of the tck signal. for details on change timing of the tdo value, see section 21.4.3, tdo output timing. the tdo pin is high impedance, except in the shift-dr and shift-ir states. a transition to the test-logic-reset state is made asynchronously with tck by driving the trst signal 0. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 617 of 794 rej09b0237-0500 21.4.2 reset configuration table 21.4 reset configuration asemd * 1 res trst lsi state high low low normal reset and h-udi reset high normal reset high low h-udi reset only high normal operation low low low reset hold * 2 high normal reset high low h-udi reset only high normal operation notes: 1. selects to normal mode or ase mode. asemd0 = high: normal mode asemd0 = low: ase mode 2. in ase mode, the reset hold state is entered by driving the res and trst pins low for the given time. in this state, the cpu does not start up, even if the res pin is driven high. after that, when the trst pin is driven high, h-udi operation is enabled, but the cpu does not start up. the reset hold stat e is canceled by the following: another res assert (power-on reset) or trst reassert. 21.4.3 tdo output timing the timing of data output from the tdo differs according to the command type set in sdir. the timing changes at the tck falling edge when jtag commands (extest, clamp, highz, sample/preload, idcode, and bypass) are set. this is a timing of the jtag standard. when the h-udi commands (h-udi reset negate, h-udi reset assert, and h-udi interrupt) are set, the tdo signal is output at the tck rising edge earlier than the jtag standard by a half cycle. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 618 of 794 rej09b0237-0500 tdo (when the h-udi command is set) tck tdo (when the jtag command is set) t tdo t tdo figure 21.3 h-udi data transfer timing 21.4.4 h-udi reset an h-udi reset is generated by setting the h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h- udi reset is released by inputting the h-udi reset negate command. the required time between th e h-udi reset assert command and h-udi reset negate command is the same as time for keeping the resetp pin low to apply a power-on reset. h-udi reset assert h-udi reset negate sdir lsi internal reset cpu state branch to h'a0000000 figure 21.4 h-udi reset 21.4.5 h-udi interrupt the h-udi interrupt function generates an interrupt by setting an h-udi command in sdir. an h-udi interrupt is an interrupt of general exceptions, resulting in a branch to an address based on the vbr value plus offset, and with return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are accepted in sleep mode, but not in standby mode. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 619 of 794 rej09b0237-0500 21.5 boundary scan a command can be set in sdir by the h-udi to place the h-udi pins in boundary scan mode stipulated by jtag. 21.5.1 supported instructions this lsi supports the three mandatory instructions defined in the jtag standard (bypass, sample/preload, and extest) and three op tion instructions (idcode, clamp, and highz). bypass: the bypass instruction is a mandatory instruction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instruction is ex ecuting, the test circuit has no effect on the system circuits. the upper four bits of the instruction code are 1111. sample/preload: the sample/preload instruction inputs data from this lsi's internal circuitry to the boundary scan register, outputs data from the scan path, and loads data onto the scan path. while this instruction is executed, signal s input to this lsi pins are transmitted directly to the internal circuitry, and internal circuit outputs are directly output externally from the output pins. this lsi's system circuits are not affected by execution of this instruction. the upper four bits of the instruction code are 0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rising edge of the tck signal in the capture-dr state. snapshot latching does not affect normal operation of this lsi. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). extest: this instruction is provided to test external circuitry when this lsi is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carri ed out by using the extest instruction n times, the nth test data is scanned-in when test data (n-1) is scanned out. section 21 user debugging interface (h-udi) rev. 5.00 mar. 15, 2007 page 620 of 794 rej09b0237-0500 data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the upper four bits of the instruction code are 0000. idcode: a command can be set in sdir by the h- udi pins to place the h-udi pins in the idcode mode stipulated by jtag. when the h-udi is initialized ( trst is asserted or tap is in the test-logic-reset state), th e idcode mode is entered. clamp, highz: a command can be set in sdir by the h-udi pins to place the h-udi pins in the clamp or highz mode stipulated by jtag. 21.5.2 points for attention ? boundary scan mode does not cover clock-related system signals (extal, xtal, ckio, and ck_phy), e10a-related signals ( res and asemd ), and h-udi-related signals (tck, tdi, tdo, tms, and trst ). ? when the extest, clamp, and highz commands are set, fix the res pin low. ? when a boundary scan test for other than bypass and idcode is carried out, fix the asemd pin high. 21.6 usage notes ? an h-udi command, once set, will not be modified as long as another command is not re- issued from the h-udi. if the same command is given continuously, the command must be set after a command (bypass, etc.) that does not affect lsi operations is once set. ? because lsi operations are suspended in st andby mode, h-udi commands are not accepted. to hold the state of the tap before and afte r standby mode, the tck signal must be high during standby mode transition. ? the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 621 of 794 rej09b0237-0500 section 22 ethernet physical layer transceiver (phy) this lsi has an on-chip phy module. 22.1 features ? fully-integrated ieee 802.3/802.3u compliant 10/100mbps ethernet phy ? phy clock = 25 mhz, 3.3 v analog power supply. ? integrated dsp with adaptive-equalizer an d baseline wander (blw) correction high immunity to crosstalk ? link-configuration automatically determined by auto-negotiation / parallel detection; manual configuration also available ? low power consumption ? half- and full-duplex capable for both 10 and 100 mbps links ? automatic polarity correction in 10base-t ? extended cable length option in 10base-t ? mii interface to the cpu core of this lsi. ? serial management interface (smi) ? link, activity, duplex and speed led outputs section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 622 of 794 rej09b0237-0500 figure 22.1 shows the block diagram around the phy module. cpu phy-if mii phy etc (ether c) tx-er mii_txd3 mii_txd2 mii_txd1 mii_txd0 tx-en tx-clk mdc mdio mdi_dir mii_rxd3 mii_rxd2 mii_rxd1 mii_rxd0 rx-clk crs col rx-dv rx-er co_tx_er co_mii_txd3 co_mii_txd2 co_mii_txd1 co_mii_txd0 co_tx_en co_tx_clk co_mdclk co_mdi co_mdo co_mdio_dir co_mii_rxd3 co_mii_rxd2 co_mii_rxd1 co_mii_rxd0 co_rx_clk co_crs co_col co_rx_dv co_rx_er led (_crs) led (_link) led (_speed100) led (_full-duplex) magnetics cat5 tx/rx this lsi internal bus outside lsi figure 22.1 the block di agram around phy module. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 623 of 794 rej09b0237-0500 22.2 pin configuration phy module has below pins. table 22.1 pin configuration pin name abbreviation i/o function analog power supply 1 for phy vcc1a input analog power supply for phy analog power supply 2 for phy vcc2a input analog power supply for phy analog power supply 3 for phy vcc3a input analog power supply for phy analog ground 1 for phy vss1a input analog ground for phy analog ground 2 for phy vss2a input analog ground for phy phy clock ck_phy input for providing the external clock for phy. of course you can provide a clock from internal clock pulse generator (cpg), but you have to pull up or down this pin in that case. differential transmit output (+) txp output the differential transmit output (+) from phy to ethernet network differential transmit output (-) txm output the differential transmit output (-) from phy to ethernet network differential receive input (+) rxp input the differential receive input (+) from ethernet network to phy differential receive input (-) rxm input the differential rece ive input (-) from ethernet network to phy speed100 signal speed100 output speed10 0 output low shows that the operating speed is 100 mbit/s or during auto negotiation link signal link output link output (low indicates that link is on.) crs signal crs output crs output (low indicates that there is crs (carrier sense), keeps low after inactivation of crs about 128 ms.) duplex signal duplex output duplex output (low indicates full duplex) section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 624 of 794 rej09b0237-0500 pin name abbreviation i/o function reference resistor exres1 input connect to the ground through a resistor of value 12.4kohm, 1%. test input/output tstbusa i/o i/o for test. do not connect anything to this pin. 22.3 top level functional architecture functionally, this phy module can be divided into the following sections: ? 100base-tx transmit and receive ? 10base-t transmit and receive ? mii interface to the on-chip etherc of this lsi ? auto-negotiation to automatically determine the best speed and duplex possible ? management control to read status registers and write control register. auto-negotiation a/d 100m pll 10m pll squelch and filters central bias smi mii bus mii logic 10m tx logic 10m transmitter 100m tx logic 100m transmitter transmit 100m rx logic 10m rx logic receive dsp system: clock data recovery equalizer management control to magnetics from magnetics analog blocks = figure 22.2 arch itectural overview section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 625 of 794 rej09b0237-0500 22.4 phy management control the management control module includes 2 blocks: ? serial management interface (smi) ? management registers set 22.4.1 serial manage ment interface (smi) the serial management interface is used to cont rol this phy core and obtain its status. this interface supports registers 0 th rough 6 as required by clause 22 of the 802.3 standard. non- supported registers (7 to 15) w ill be read as hexadecimal "ffff". at the system level there are 2 signals, mdio and mdc where mdio is bi-directional open-drain and mdc is the clock. in the core there is no notion of bi-directional signals so the mdio signal is implemented as 3 signals: co_mdio_dir, co_mdo and co_mdi. the relationship among these signals is made clear in figure 22.3. mdio enb co_mdio_dir co_mdio co_mdi etherc side phy module side inside of this lsi note: drivers are in open-drain state figure 22.3 how to derive mdio signal from core signals the co_mdc signal is an a-periodic clock provided by the station management controller (smc). the co_mdi signal recei ves serial data (commands) from the controller smc. the co_mdo sends serial data (status) to the smc. the minimum time between edges of the co_mdc is 160 ns. there is no maximum time between edges. the minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. these modest timing requirements allow this interface to be easily driven by the cpu. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 626 of 794 rej09b0237-0500 the data on the co_mdo and co_mdi lines is latched on the rising edge of the co_mdc. the frame structure and timing of the data is shown in figure 22.4 and figure 22.5. ... ... co_mdc co_mdi co_mdio_dir co_mdo 32 1's 0 1 1 0 preamble start of frame op code phy address output on the rising edge latch on the rising edge register address tu r n around data a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 d15 d14 d1 d0 figure 22.4 mdio timing an d frame structure (read cycle) ... co_mdc co_mdi co_mdio_dir co_mdo 32 1's 0 1 0 1 a4 a3 a2 a1 a0 r4 r3 r2 r1 r0 ... d15 d14 d1 d0 preamble start of frame op code phy address register address tu r n around data output on the rising edge latch on the rising edge figure 22.5 mdio timing an d frame structure (write cycle) shown below is an example of coding for mdc cycles implemented by software loops. note: co_mdio_dir in figures 22.4 and 22.5 above has a reverse polarity in relation to the mmd bit in the pir register. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 627 of 794 rej09b0237-0500 /* smi register read */ unsigned short ether_reg_read( unsigned short reg_addr ) { unsigned short data; phy_preamble(); phy_reg_set( reg_addr, phy_read ); phy_ta_z0(); phy_reg_read( &data ); mii_idle(); return( data ); } /* smi register write */ void ether_reg_write( unsigned short reg_addr, unsigned short data ) { phy_preamble(); phy_reg_set( reg_addr, phy_write ); phy_ta_10(); phy_reg_write( data ); mii_idle(); } /* subroutines */ void phy_preamble( void ) { long i; i = 32; while( i > 0 ) { mii_write_1(); i--; } section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 628 of 794 rej09b0237-0500 } void phy_reg_set( unsigned short reg_addr, long option ) { long i; unsigned short data; data = 0; data = (phy_st << 14); /* st code */ if( option == phy_read ) { data |= (phy_read << 12); /* op code(rd) */ } else { data |= (phy_write << 12); /* op code(wt) */ } data |= (phy_addr << 7); /* phy address */ data |= (reg_addr << 2); /* reg address */ i = 14; while( i > 0 ) { if( (data & 0x8000) == 0 ) { mii_write_0(); } else { mii_write_1(); } data <<= 1; i--; } } section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 629 of 794 rej09b0237-0500 #define quata 6 // =25cyc/4 (please define to keep, ?mdc cycle > 400ns?) void phy_reg_read( unsigned short *data ) { long i; long j; unsigned short reg_data; reg_data = 0; i = 16; //preceding ta cycle set pir 0x00000000 while( i > 0 ) { for (j=1;j<=quata;j++) reg_pir = 0x00000000; for (j=1;j<=quata;j++) reg_pir = 0x00000001; reg_data <<= 1; reg_data |= (reg_pir & 0x00000008) >> 3; /* mdi read*/ for (j=1;j<=quata;j++) reg_pir = 0x00000001; for (j=1;j<=quata;j++) reg_pir = 0x00000000; i--; } *data = reg_data; } void phy_reg_write( unsigned short data ) { long i; i = 16; while( i > 0 ) { if( (data & 0x8000) == 0 ) { mii_write_0(); section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 630 of 794 rej09b0237-0500 } else { mii_write_1(); } i--; data <<= 1; } } void phy_ta_z0( void ) { mii_idle(); mii_idle(); } void phy_ta_10( void ) { mii_write_1(); mii_write_0(); } /* output 1 */ void mii_write_1( void ) { int j; unsigned short pre_data; section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 631 of 794 rej09b0237-0500 pre_data = reg_pir&0x00000006; /* mdo,mmd */ for (j=1;j<=quata;j++) reg_pir = 0x00000000 | pre_data; //line 1 for (j=1;j<=quata;j++) reg_pir = 0x00000001 | pre_data; //line 2 for (j=1;j<=quata;j++) reg_pir = 0x00000007; //line 3 for (j=1;j<=quata;j++) reg_pir = 0x00000006; //line 4 } /* output 0 */ void mii_write_0( void ) { int j; unsigned short pre_data; pre_data = reg_pir&0x00000006; /* mdo,mmd */ for (j=1;j<=quata;j++) reg_pir = 0x00000000 | pre_data; for (j=1;j<=quata;j++) reg_pir = 0x00000001 | pre_data; for (j=1;j<=quata;j++) reg_pir = 0x00000003; for (j=1;j<=quata;j++) reg_pir = 0x00000002; } /* idle cycle */ void mii_idle( void ) { int j; unsigned short pre_data; pre_data = reg_pir&0x00000006; /* mdo,mmd */ for (j=1;j<=quata;j++) reg_pir = 0x00000000 | pre_data; for (j=1;j<=quata;j++) reg_pir = 0x00000001 | pre_data; for (j=1;j<=quata;j++) reg_pir = 0x00000001; for (j=1;j<=quata;j++) reg_pir = 0x00000000; } pre_data 1 line 1 line 2 line 3 line 4 mdc mdo example of corresponding waveforms section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 632 of 794 rej09b0237-0500 22.4.2 smi register mapping the following registers ar e supported (register numbers are in decimal): register # description group 0 basic control register basic 1 basic status register basic 2 phy identifier 1 extended 3 phy identifier 2 extended 4 auto-negotiation advertisement register extended 5 auto-negotiation link partner ability register extended 6 auto-negotiation expansion register extended ? smi register format the mode key is as follows: rw = read/write, sc = self clearing, wo = write only, ro = read only lh = latch high, clear on read of register ll = latch low, clear on read of register nasr = not affected by software reset (n,m) = register n, bit m section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 633 of 794 rej09b0237-0500 ? register 0 (basic control) address name description mode default 0.15 reset 1 = software reset. this bit is self-clearing. with this lsi, do not use this bit. rw/sc 0 0.14 loopback 1 = loopback mode, 0 = normal operation rw 0 0.13 speed select 1 = 100mbps, 0 = 10mbps. ignored if auto negotiation is enabled (0.12 = 1). rw set by co_st_mode [2:0] of phyifcr 0.12 auto- negotiation enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8), 0 = disable auto-negotiate process rw set by co_st_mode [2:0] of phyifcr 0.11 power down 1 = general power down mode, 0 = normal operation rw 0 0.10 isolate reserved. (0= norma l operation)the write value should always be 0. rw set by co_st_mode [2:0] of phyifcr 0.9 restart auto- negotiate 1 = restart auto-negotiate process, 0 = normal operation. bit is self-clearing. rw/sc 0 0.8 duplex mode 1 = full duplex, 0 = half duplex . ignored if auto negotiation is enabled (0.12 = 1). rw set by co_st_mode [2:0] of phyifcr 0.7 collision test 1 = enable col te st, 0 = disable col test rw 0 0.6:0 reserved the write valu e should always be 0. ro 0 section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 634 of 794 rej09b0237-0500 ? register 1 (basic status) address name description mode default 1.15 100base-t4 this bit indicates that t4 is available or not, but this module has no capability of t4 and it is fixed to 0.the write value should always be 0. ro 0 1.14 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability ro 1 1.13 100base-tx half duplex 1 = tx with half duplex, 0 = no tx half duplex ability ro 1 1.12 10base-t full duplex 1 = 10mbps with full duplex, 0 = no 10mbps with full duplex ability ro 1 1.11 10base-t half duplex 1 = 10mbps with half duplex, 0 = no 10mbps with half duplex ability ro 1 1.10:6 reserved the write valu e should always be 0. ro 0 1.5 auto- negotiate complete 1 = auto-negotiate process completed, 0 = auto-negotiate process not completed ro 0 1.4 remote fault 1 = remote fault condition detected, 0 = no remote fault ro/lh 0 1.3 auto- negotiate ability 1 = able to perform auto-negotiation function, 0 = unable to perform auto-negotiation function ro 1 1.2 link status 1 = link is up, 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber c ondition detected, 0 = no jabber condition detected ro/lh 0 1.0 extended capabilities 1 = supports extended capabilities registers, 0 = does not support extended capabilities registers ro 1 ? register 2 (phy identifier 1) address name description mode default 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui), respectively. rw co_reg2_oui_in [15:0] of phyifsmir2 section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 635 of 794 rej09b0237-0500 ? register 3 (phy identifier 2) address name description mode default 3.15:10 phy id number b assigned to the 19th through 24th bits of the oui. rw 3.9:4 model number six bit manufacturer's model number. rw 3.3:0 revision number four bit manufacturer's revision number. rw co_reg3_oui_ in[15:0] of phyifsmir3 ? register 4 (auto negotiation advertisement) address name description mode default 4.15 next page this bit indicates next page is available or not, but this core does not support next page ability and it is fixed to 0.the write value should always be 0. ro 0 4.14 reserved the write valu e should always be 0. ro 0 4.13 remote fault 1 = remote fault detected, 0 = no remote fault rw 0 4.12 reserved the write valu e should always be 0. r/w 0 4.11:10 pause operation 00 no pause, 01 asymmetric pause toward link partner, 10 symmetric pause, 11 both symmetric pause and asymmetric pause towa rd local device r/w 00 4.9 100base-t4 reserved. the write value should always be 0. ro 0 4.8 100base-tx full duplex 1 = tx with full duplex, 0 = no tx full duplex ability rw set by co_st_mode [2:0] of phyifcr 4.7 100base-tx 1 = tx able, 0 = no tx ability rw 1 4.6 10base-t full duplex 1 = 10mbps with full duplex, 0 = no 10mbps with full duplex ability rw set by co_st_mode [2:0] of phyifcr section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 636 of 794 rej09b0237-0500 address name description mode default 4.5 10base-t 1 = 10mbps able, 0 = no 10mbps ability rw set by co_st_mode [2:0] of phyifcr 4.4:0 selector field [00001] = ieee 802.3 rw 00001 ? register 5 (auto negotiation link partner ability) address name description mode default 5.15 next page 1 = next page capable 0 = no next page ability. this part does not support next page ability. ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12:11 reserved the write valu e should always be 0. ro 0 5.10 pause operation 1 = pause operation is supported by remote mac 0 = pause operation is not supported by remote mac ro 0 5.9 100base-t4 1 = t4 able, 0 = no t4 ability ro 0 5.8 100base-tx full duplex 1 = tx with full duplex 0 = no tx full duplex ability ro 0 5.7 100base-tx 1 = tx able, 0 = no tx ability ro 0 5.6 10base-t full duplex 1 = 10mbps with full duplex 0 = no 10mbps with full duplex ability ro 0 5.5 10base-t 1 = 10mbps able 0 = no 10mbps ability ro 0 5.4:0 selector field [0000 1] = ieee 802.3 ro 00001 section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 637 of 794 rej09b0237-0500 ? register 6 (auto negotiation expansion) address name description mode default 6.15:5 reserved the write value should always be 0. ro 0 6.4 parallel detection fault 1 = fault detected by parallel detection logic 0 = no fault detected by parallel detection logic ro/lh 0 6.3 link partner next page able 1 = link partner has next page ability 0 = link partner does not have next page ability ro 0 6.2 next page able 1 = local device has next page ability 0 = local device does not have next page ability ro 0 6.1 page received 1 = new page received 0 = new page not yet received ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation ability, 0 = link partner does not have auto-negotiation ability ro 0 section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 638 of 794 rej09b0237-0500 22.5 100base-tx transmit the data path of the 100base-tx is shown in figure 2. each major block is explained below. 100 m pll mac (ether c) mii 25 mhz by 4 bits mii 25 mhz by 5 bits 25 mhz by 4 bits 125 mbps serial nrzi mlt-3 mlt-3 magnetics rj 45 mlt-3 cat-5 mtl-3 co_tx_clk (for mii) 4b/5b encoder scrambler and piso nrzi converter mlt-3 converter tx driver shaded blocks are part of the phy core figure 22.6 100base-tx data path (1) 100m transmit data across the mii the mac controller drives the transmit data onto the co_mii_txd bus and asserts the internal signal (co_tx_en) to indicate valid data. the data is latched by the phy's mii block on the rising edge of co_tx_clk. the data is in the form of 4-bit wide 25mhz data. (2) 4b/5b encoding the transmit data passes from the mii block to the 4b/5b encoder. this block encodes the data from 4-bit nibbles to 5-bit symbols (known as "code-groups") according to table 1. each 4-bit data-nibble is mapped to 16 of the 32 possible code-groups. the remaining 16 code-groups are either used for control in formation or are not valid. the first 16 code-groups are refe rred to by the hexadecimal valu es of their corresponding data nibbles, 0 through f. the remaining code-groups are given letter designations with slashes on either side. for example, an idle code-group is /i/, a transmit error co de-group is /h/, etc. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 639 of 794 rej09b0237-0500 table 22.2 4b/5b code table code group sym receiver interpretation (co_mii_rxd) transmitter interpretation (co_mii_txd) 11110 0 0 0000 data 0 01001 1 1 0001 data 1 10100 2 2 0010 data 2 10101 3 3 0011 data 3 01010 4 4 0100 data 4 01011 5 5 0101 data 5 01110 6 6 0110 data 6 01111 7 7 0111 data 7 10010 8 8 1000 data 8 10011 9 9 1001 data 9 10110 a a 1010 data a 10111 b b 1011 data b 11010 c c 1100 data c 11011 d d 1101 data d 11100 e e 1110 data e 11101 f f 1111 data f 11111 i idle sent after /t/r/ until co_tx_en 11000 j first nibble of ssd, translated to "0101" following idle, else co_rx_er sent for rising co_tx_en 10001 k second nibble of ssd, translated to "0101" following j, else co_rx_er sent for rising co_tx_en 01101 t first nibble of esd, causes de-assertion of crs if followed by /r/, else assertion of co_rx_er sent for falling co_tx_en 00111 r second nibble of esd, causes deassertion of crs if following /t/, else assertion of co_rx_er sent for falling co_tx_en 00100 h transmit error symbol sent for rising co_tx_er 00110 v invalid, co_rx_er if during co_rx_dv invalid 11001 v invalid, co_rx_er if during co_rx_dv invalid 00000 v invalid, co_rx_er if during co_rx_dv invalid section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 640 of 794 rej09b0237-0500 code group sym receiver interpretation (co_mii_rxd) transmitter interpretation (co_mii_txd) 00001 v invalid, co_rx_er if during co_rx_dv invalid 00010 v invalid, co_rx_er if during co_rx_dv invalid 00011 v invalid, co_rx_er if during co_rx_dv invalid 00101 v invalid, co_rx_er if during co_rx_dv invalid 01000 v invalid, co_rx_er if during co_rx_dv invalid 01100 v invalid, co_rx_er if during co_rx_dv invalid 10000 v invalid, co_rx_er if during co_rx_dv invalid (3) scrambling repeated data patterns (especially the idle code-group) can have power spectral densities with large narrow-band peaks. scrambling the data help s eliminate these peaks and spread the signal power more uniformly over the entire channel bandwidth. this uniform spectral density is required by fcc regulations to prevent excessi ve emi from being radiated by the physical routing. the seed for the scrambler is generated from th e phy address. the scrambler also performs the parallel in serial out conversion (piso) of the data. (4) nrzi and mlt3 encoding the scrambler block passes the 5-bit wide parallel data to the nrzi converter where it becomes a serial 125mhz nrzi data stream. the nrzi is encoded to mlt-3. mlt3 is a tri-level code where a change in the logic level represents a co de bit "1" and the logic output remaining at the same level represents a code bit "0". (5) 100m transmit driver the mlt3 data is then passed to the analog tr ansmitter, which launches the differential mlt-3 signal, on outputs txp and txm, to the twisted pair media via a 1:1 ratio isolation transformer. the 10base-t and 100base-tx signals pass thro ugh the same transformer so that common "magnetics" can be used for both. the transmitter drives into the 100 ohm impedance of the cat- 5 cable. cable termination and impedance matching require external components. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 641 of 794 rej09b0237-0500 (6) 100m phase lock loop (pll) the 100m pll locks onto reference clock and generates the 125mhz clock used to drive the 125 mhz logic and the 100base-tx transmitter. 22.6 100base-tx receive mac (ether c) 100m pll mii 25mhz by 4 bits 25mhz by 4 bits 25mhz by 5 bits mii 125mbps serial nrzi mlt-3 mlt-3 mlt-3 mlt-3 mlt-3 magnetics rj45 cat-5 6 bit data co_rx_clk (for mii) 4b/5b decoder descrambler and piso nrzi converter mlt-3 converter dsp: timing recovery, equalize and blw correction a/d converter shaded blocks are part of the phy core figure 22.7 r eceive data path the receive data path is shown in figure 3. detailed descriptions are given below. (1) 100m receive input the mlt-3 from the cable is fed into the core phy (on inputs rxp and rxm) via a 1:1 ratio transformer. the adc samples th e incoming differential signal at a rate of 125m samples per second. using a 64-level quantizer it generates 6 digital bits to represent each sample. the dsp adjusts the gain of the adc according to the obse rved signal levels such that the full dynamic range of the adc can be used. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 642 of 794 rej09b0237-0500 (2) equalizer, baseline wander correctio n and clock and data recovery the 6 bits from the adc are fed into the dsp block. the equalizer in the dsp section compensates for phase and amplitude distortion caused by the physical channel consisting of magnetics, connectors, and cat- 5 cable. the equalizer can restore the signal for any good- quality cat-5 cable between 1m and 150m. if the dc content of the signal is such that the low-frequency components fall below the low frequency pole of the isolation transformer, then the droop characteristics of the transformer will become significant and baseline wander (blw) on the received signal will result. to prevent corruption of the received data, the core ph y corrects for blw and can receive the ansi x3.263-1995 fddi tp-pmd defined "killer packet" with no bit errors. the 100m pll generates multiple phases of the 125mhz clock. a multiplexer, controlled by the timing unit of the dsp, selects the optimum phase for sampling the data. this is used as the received recovered clock. this clock is used to extract the serial data from the received signal. (3) nrzi and mlt-3 decoding the dsp generates the mlt-3 recovered levels that are fed to the mlt-3 converter. the mlt-3 is then converted to an nrzi data stream. (4) descrambling the descrambler performs an inverse function to the scrambler in the transmitter and also performs the serial in parallel ou t (sipo) conversion of the data. during reception of idle (/i/) sy mbols. the descrambler synchroni zes its descrambler key to the incoming stream. once synchronization is achieved, the descrambler locks on this key and is able to descramble incoming data. special logic in the descrambler ensures synchronization with th e remote phy by searching for idle symbols within a window of 4000 bytes (40us). this window ensures that a maximum packet size of 1514 bytes, allo wed by the ieee 802.3 standard, can be received with no interference. if no idle-symbols are detected within this time-period, receive operation is aborted and the descrambler re-starts the synchronization process. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 643 of 794 rej09b0237-0500 (5) alignment the de-scrambled signal is then aligned into 5-bit code-groups by recognizing the /j/k/ start-of- stream delimiter (ssd) pair at the start of a p acket. once the code-word alignment is determined, it is stored and utilized until the next start of frame. (6) 5b/4b decoding the 5-bit code-groups are translat ed into 4-bit data nibbles acco rding to the 4b/5b table. the translated data is presented on the co_mii_rxd[3:0] signal lines. the ssd, /j/k/, is translated to "0101 0101" as the first 2 nibbles of the mac preamble. recep tion of the ssd causes the phy to assert the co_rx_dv signal, indicating that valid data is available on the co_mii_rxd bus. successive valid code-group s are translated to data nibbles. recep tion of either the end of stream delimiter (esd) consisting of the /t/r/ symbols, or at least two /i/ symbol s causes the phy to de- assert carrier sense and co_rx_dv. these symbols are not tr anslated into data. (7) receive data valid signal the receive data valid signal (co_rx_dv) indi cates that recovered and decoded nibbles are being presented on the co_mii_rxd[3:0] outputs synchronous to co_rx_clk. co_rx_dv becomes active after the /j/k/ delimiter has been recognized and co_mii _rxd is aligned to nibble boundaries. it remains active until either the /t/r/ delimiter is recognized or link test indicates failure, etc. co_rx_dv is asserted when the first nibble of tr anslated /j/k/ is ready for transfer over the media independent interface (mii). j data data data data data data data data k555 5 555 5 d d t r idle co_rx_clk co_rx_dv co_rxd figure 22.8 relationship between received data and some mii signals section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 644 of 794 rej09b0237-0500 (8) receiver errors during a frame, unexpected code-groups are consid ered receive errors. exp ected code groups are the data set (0 through f), and the /t/r/ (esd) symbol pair. when a r eceive error occurs, the co_rx_er signal is asserted and arbitrary data is driven onto the co_mii_rxd lines. should an error be detected during the tim e that the /j/k/ delimiter is being decoded (bad ssd error), co_rx_er is asserted true and the value '1110' is driven onto the co_mii_rxd lines. note that the valid data signal is not yet asserted when the bad ssd error occurs. (9) 100m receive data across the mii the 4-bit data nibbles are sent to the mii block. th ese data nibbles are clocked to the controller at a rate of 25mhz. the controller samples the data on the rising edge of co_rx_clk. co_rx_clk is the 25mhz output clock for the mii bu s. it is recovered from the received data to clock the co_mii_rxd bus. if there is no received signal, it is derived from the system reference clock (co_clkin). when tracking the received data, co_rx_clk has a maximum jitter of 0.8ns (provided that the jitter of the input clock, co_clkin, is below 100ps). 22.7 10base-t transmit data to be transmitted comes from the mac laye r controller. the 10base-t transmitter receives 4-bit nibbles from the mii at a rate of 2.5mhz and converts them to a 10mbps serial data stream. the data stream is then manchester-encoded and sent to the analog tran smitter which drives a signal onto the twisted pair via the external magnetics. the 10m transmitter uses the following blocks: ? mii (digital) ? tx 10m (digital) ? 10m transmitter (analog) ? 10m pll (analog) section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 645 of 794 rej09b0237-0500 (1) 10m transmit data across the mii the mac controller (etherc) drives the transm it data onto the co_mii_txd bus. when the controller (etherc) has driven co_tx_en high to indicate valid data, the data is latched by the mii block on the rising edge of co_tx_clk. the data is in the form of 4-bit wide 2.5 mhz data. in order to comply with legacy 10base-t mac/controllers, in half-duplex mode the phy loops back the transmitted data, on the r eceive path. this does not confus e the mac/controller since the co_col signal is not asserted during this ti me. the phy also support the sqe (heart beat) signal. (2) manchester encoding the 4-bit wide data is sent to the tx10m block. the nibbles are converted to a 10mbps serial nrzi data stream. the 10m pll locks onto the exte rnal clock or internal oscillator and produces a 20mhz clock. this is used to manchester encode the nrz data stream. when no data is being transmitted (co_tx_en is low, the tx10m block outputs normal link pulses (nlps) to maintain communications with the remote link partner. 1 1 10 0 data manchester encoded output figure 22.9 manchester encoded output (3) 10m transmit drivers the manchester encoded data is sent to the anal og transmitter where it is shaped and filtered before being driven out as a differential signal across the txp and txm outputs. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 646 of 794 rej09b0237-0500 22.8 10base-t receive the 10base-t receiver gets the manchester- en coded analog signal from the cable via the magnetics. it recovers the receive clock from the signal and uses this clock to recover the nrzi data stream. this 10m serial data is converted to 4-bit data nibbles which are passed to the controller (etherc) across the mii at a rate of 2.5 mhz. this 10m receiver uses the following blocks: ? filter and squelch (analog) ? 10m pll (analog) ? rx 10m (digital) ? mii (digital) (1) 10m receive input and squelch the manchester signal from the cable is fed into the core phy (on inputs rxp and rxm) via 1:1 ratio magnetics. it is first filtered to redu ce any out-of-band noise. it then passes through a squelch circuit. the squelch is a set of am plitude and timing comparators that normally reject differential voltage levels below 300mv and detect and recognize differential voltages above 585mv. (2) manchester decoding the output of the squelch goes to the rx10m block where it is validated as manchester encoded data. the polarity of the signal is also checked. if the polarity is reversed (local rxp is connected to rxm of the remote partner and vice ve rsa), then this is iden tified and corrected. the 10m pll is locked onto the received manchester signal and from this, generates the received 20mhz clock. using this clock, the manchester encoded data is extracted and converted to a 10mhz nrzi data stream. it is then converted from serial to 4-bit wide parallel data. the rx10m block also detects valid 10base-t id le signals, normal li nk pulses (nlps), to maintain the link. (3) 10m receive data across the mii the 4 bit data nibbles are sent to the mii block. these data nibbles are valid on the rising edge of the 2.5 mhz co_rx_clk. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 647 of 794 rej09b0237-0500 (4) jabber detection jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition, that results in holding the co_tx_en input for a long period. special logic is used to de tect the jabber state and ab ort the transmission to the line, within 45ms. once co_tx_en is deasserted, the logic resets the jabber condition. bit 1.1 indicates that a jabber condition was detected. 22.9 mac interface the mii (media independent interface) block is responsible for the communication with the controller (etherc). special sets of hand-shake signals are used to indicate that valid received/transmitted data is present on the 4 b it receive/transmit bus. (1) the mii includes 16 interface signals: ? transmit data: co_mii_txd[3:0] ? transmit strobe: co_tx_en ? transmit: co_tx_clk ? transmit error: co_tx_er ? receive data: co_mii_rxd[3:0] ? receive strobe: co_rx_dv ? receive clock: co_rx_clk ? receive error: co_rx_er ? collision indication: co_col ? carrier sense: co_crs on the transmit path, the phy drives the transmit clock, co_tx_clk, to the controller (etherc). the controller (etherc) synchronizes the transm it data to the rising edge of co_tx_clk. the controller (etherc) drives co_tx_en high to indicate valid transmit data. the controller (etherc) drives co_tx_er high when a transmit error is detected. on the receive path, the phy drives both th e receive data, co_rxd, and the co_rx_clk signal. the controller (etherc) clocks in the r eceive data on the risi ng edge of co_rx_clk when the phy drives co_rx_dv high. the phy drives co_rx_er high when a receive error is detected. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 648 of 794 rej09b0237-0500 (2) auto-negotiation the purpose of the auto-negotiation function is to automatically configure the phy to the optimum link parameters based on the capabilities of its link partner. auto-negotiation is a mechanism for exchanging config uration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. auto-negotiation is fully defined in clause 28 of the ieee 802.3 specification. once auto-negotiation has completed, information about the resolved link can be passed back to the controller (etherc) via the serial management interface (smi). the re sults of the negotiation process are reflected in the link partner ability register (register 5). the auto-negotiation protocol is a purely physical layer activity and proceeds independently of the mac controller (etherc). the advertised capabilities of the phy are stored in register 4 of the smi registers. the default advertised by the core phy is determined by user-defined on-chip signal options. (i.e. the configuration of phy-if) the following blocks are activated during an auto-negotiation session: ? auto-negotiation (digital) ? 100m adc (analog) ? 100m pll (analog) ? 100m equalizer/blw/clock recovery (dsp) ? 10m squelch (analog) ? 10m pll (analog) ? 10m transmitter (analog) when enabled, auto-negotiation is started by the occurrence of one of the following events: ? module reset (co_resetb of phy-if) ? phy power on reset ? software reset ? power-down reset ? link status down ? setting register 0, bit 9 high (auto-negotiation restart) section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 649 of 794 rej09b0237-0500 on detection of one of these events, the phy be gins auto-negotiation by transmitting bursts of fast link pulses (flp). these ar e bursts of link pulses from the 10 m transmitter. they are shaped as normal link pulses and can pass uncorrupte d down cat-3 or cat-5 cable. a fast link pulse burst consists of up to 33 pulses. the 17 odd-numbered pulses, which are always present, frame the flp burst. the 16 even-numbered pulses, which may be present or absent, contain the data word being transmitted. presence of a data pulse re presents a "1", while ab sence represents a "0". the data transmitted by an flp burst is known as a "link code word." these are defined fully in ieee 802.3 clause 28. in summary, the core phy ad vertises 802.3 compliance in its selector field (the first 5 bits of the link code word). it advertises its technol ogy ability according to the bits set in register 4 of the smi registers. there are 4 possible matches of the technology abilities. in the order of priority these are: ? 100m full duplex (highest priority) ? 100m half duplex ? 10m full duplex ? 10m half duplex if the full capabilities of the core phy are advertised (100m, full duplex), and if the link partner is capable of 10m and 100m, then auto-negot iation selects 100m as the highest performance mode. if the link partner is capable of half and full duplex modes, then auto-negotiation selects full duplex as the highest performance operation. once a capability match has been determined , the link code words are repeated with the acknowledge bit set. any difference in the main cont ent of the link code words at this time will cause auto-negotiation to re-start. auto-negotiation w ill also re-start if not all of the required flp bursts are received. the capabilities advertised during auto-negotiation by the core phy are initially determined the co_st_mode[2:0] bits (phyifcr in the phy-if) latched after module reset or phy power on reset completes. this bit can also be used to disable auto-negotiation on power-up. writing register 4 bits [8:5] allows software control of the capabilities advertised by the core phy. writing register 4 does not automatically re-start au to-negotiation. register 0, bit 9 must be set before the new abilities will be advertised. auto-negotiation can also be disabled via software by clearing register 0, bit 12. the phy module does not support the next page capability. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 650 of 794 rej09b0237-0500 (3) parallel detection if the phy module is connected to a device lacking the ability to auto-negotiate (i.e. no flps are detected), it is able to determine the speed of the link based on either 100m mlt-3 symbols or 10m normal link pulses. in this case the link is presumed to be half duplex per the ieee standard. this ability is known as "parallel detec tion. this feature ensures interoperability with legacy link partners. if a link is formed via parallel detection, then bit 0 in register 6 is cleared to indicate that the link partner is not capable of auto-negotiation. the controller (etherc) has access to this information via the management inte rface (smi). if a fault o ccurs during parallel detection, bit 4 of register 6 is set. register 5 is used to store the link partner ab ility information, which is coded in the received flps. if the link partner is not auto-negotiation capable, then register 5 is updated after completion of parallel detection to reflect the speed capability of the link partner. (4) re-starting auto-negotiation auto-negotiation can be re-started at any time by setting register 0, bit 9. auto-negotiation will also re-start if the link is broken at any time. a broken link is caused by signal loss. this may occur because of a cable break, or because of an interruption in th e signal transmitte d by the link partner. auto-negotiation resumes in an attempt to determine the new link configuration. if the management entity re-starts auto-negotiation by writing to bit 9 of the control register, the phy module will respond by stopping all transmission/receiving operations. once the break_link_timer is done, in the auto-negotiation state-machine (approxima tely 1200ms) the auto- negotiation will re-start. the link partner will have also dropped the link due to lack of a received signal, so it too will resume auto-negotiation detection is disabled. (5) auto-negotiation disabling auto-negotiation is disabled by setting the bit 12 in the register 0 to 0. the device forcibly reflects the information in the bit 13 (speed) and bit 8 (duplex) in the register 0 to the operation speed. information in the bit 13 (speed) and bit 8 (dup lex) in the register 0 is ignored while auto- negotiation is enabled. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 651 of 794 rej09b0237-0500 (6) half-duplex and full-duplex half-duplex operation conforms to csma/cd (ca rrier sense multiple access/collision detect) protocol that deals with the network traffic and collision. in this mode, the carrier signal (crs) supports either of transmit/recei ve operation. receiving data du ring phy transmission causes a collision. in full-duplex mode, the phy performs transmit an d receive simultaneously. in this mode, the crs supports only receive. the csma/cd protocol is not applied and the collision detection is disabled. 22.10 miscellaneous functions (1) carrier sense the carrier sense is output on crs (to etherc). crs is a signal defined by the mii specification in the ieee 802.3u standard. the ph y asserts crs based only on receive activity whenever the phy is either in repeater mode or full-duplex mode. otherwise the phy asserts crs based on either transmit or receive activity. the carrier sense logic uses the encoded, unscramb led data to determine carrier activity status. it activates carrier sense with the de tection of 2 non-contiguous zeros within any 10 bit span. carrier sense terminates if a span of 10 consecutive on es is detected before a /j/k/ start-of stream delimiter pair. if an ssd pair is detected, carrier sense is asserted until ei ther /t/r/ end-of-stream delimiter pair or a pair of idle symbols is detected. carrier is negated after the /t/ symbol or the first idle. if /t/ is not followed by /r/, then carri er is maintained. carrier is treated similarly for idle followed by some non-idle symbol. (2) collision detect a collision is the occurrence of simultaneous transmit and receive op erations. the co_col output is asserted to indicate that a collision has been detected. co_col remains active for the duration of the collision. co_col is changed asynchronously to both co_rx_clk and tx_clk. the co_col output becomes inactive during full duplex mode. co_col may be tested by setting register 0, bit 7 high. this enables the collision test. co_col will be asserted within 512 bit times of co_tx_en rising and will be de-asserted within 4 bit times of co_tx_en falling. in 10m mode, co_col pulses for approximately 10 bit times (1us), 2us after each transmitted packet (de-assertion of co_tx_en). this is th e signal quality error (sqe) signal and indicates that the transmission was successful. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 652 of 794 rej09b0237-0500 (3) isolate mode the ordinary external phy lsi has a ability to make phy data paths electrically isolated from the mii by setting register 0, bit 10 to a logic one. but this phy core is on-chip type so that this function is not supported. (4) link integrity test this phy performs the lin k integrity test as outlined in th e ieee 802.3u (cla use 24-15) link monitor state diagram. the link status is multiplexed with the 10mbps link status to form the reportable link status bit in serial management register 1, and is driven to link led. the dsp indicates a valid mlt-3 waveform present on the rxp and rxm signals as defined by the ansi x3.263 tp-pmd standard, to the link monitor state-machine, using internal signal called data_valid. when data_valid is asse rted the control logic moves into a link- ready state, and waits for an enable from the auto negotiation block. when received, the link- up state is entered, and the transmit and r eceive logic blocks become active. should auto negotiation be disabled, the link integrity logic moves immediately to the link-up state, when the data_valid is asserted. note that to allow the line to stabilize, the link integrity logic will wait a minimum of 330 msec from the time data_valid is asserted until the link-ready state is entered. should the data_valid input be negated at any time, this logic will immediately negate the link signal and enter the link-down state. when the 10/100 digital block is in 10base-t mode , the link status is from the 10base-t receiver logic. (5) power-down modes there is a power-down modes for the core: ? power-down this power-down is controlled by register 0, bit 11. in this mode the entire phy, except the management interface, is powered-down and stays in that condition as long as bit 0.11 is high. when bit 0.11 is cleared, the phy powers up and is automatically reset. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 653 of 794 rej09b0237-0500 (6) reset the core phy has 4 reset sources: ? module reset (co_resetb): it is connected to the co_resetb of ph yifcr, and to the internal por signal. if the co_resetb is asserted(write "0"), it should be held "0" for at least 100 us to ensure that the core is properly reset. ? the power-on-reset (por) : por(power-on-reset) signal, which is driven out of the core through the co_pwruprst of phyifsr, is asserted for approximat ely 16 ms after the first time that power is supplied to the chip. ? software (sw) reset: (do not use with this product.) activated by writing register 0, bit 15 high. this signal is self- clearing. after the register- write, internal logic extends the reset by 256s to allow pll-stabilization before releasing the logic from reset. the ieee 802.3u standard, clause 22 (22.2.4.1. 1) states that the reset process should be completed within 0.5s from the setting of this bit. ? power-down reset: automatically activated when the phy comes out of power-down mode. the internal power- down reset is extended by 256s after exiting the power-down mode to allow the plls to stabilize before the logic is released from reset. these 4 reset sources are module reset(low active) and none module reset(phy power on reset, software reset, power down reset(high active) combined together in the digital block to create the internal "general reset", sysrst, which is an asynchronous reset and is active high. this sysrst directly drives the pcs, dsp and mii blocks. it is also input to the central bias block in order to generate a short reset for the plls. the smi mechanism and registers are reset only by the module reset, phy power-on reset and software reset. during power-down, the smi regist ers are not reset. note that some smi register bits are not cleared by software reset - thes e are marked "nasr" in the register tables. for the first 16us after coming out of reset, the mii will run at 2.5 mhz. afte r that it will switch to 25 mhz if auto-negotiation is enabled. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 654 of 794 rej09b0237-0500 (7) led description the phy provides four led signals. these provide a convenient means to determine the mode of operation of the core. all led signals are active low. ? the crs led : its output is driven low when crs is active (high). when crs becomes inactive, the activity led output is extended by 128 ms. ? the link led: its output is driven low whenever the phy de tects a valid link. the use of the 10mbps or 100mbps link test status is determined by the condition of the internally determined speed selection. ? the speed led: its output is driven low when the operating speed is 100mbit/s or during auto-negotiation. this led will go inactive when the operating speed is 10mbit/s. ? the full-duplex led its output is driven low when the link is operating in full-duplex mode. (8) loopback operation the 10/100 digital has an independent loop-back mode: internal loopback. ? internal loopback the internal loopback mode is enabled by setting bit register 0 bit 14 to logic one. in this mode, the scrambled transmit data (output of th e scrambler) is looped into the receive logic (input of the descrambler). the co_col signal will be inactive in this mode, unless collision test (bit 0.7) is active. in this mode, during transmission (co_tx_en is high), nothing is transmitted to the line and the transmitters are powered down. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 655 of 794 rej09b0237-0500 22.11 internal i/o signals the i/o signals interface the logic of the core phy to other modules on this lsi. the input signals can either be connected to other modules on the chip so that they can be connected to pins and driven externally, or they can be tied high or low inside the chip to set the behavior of the core phy. the following abbreviations are used: ? i: input. digital ttl levels. ? o: output. digital ttl levels. ? ai: input. analog levels. ? ao: output. analog levels. ? ai/o: input or output. analog levels. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 656 of 794 rej09b0237-0500 ? mii signals signal name type description co_mii_txd0 i transmit data 0: bit 0 of the 4 data bits that are accepted by the phy for transmission. co_mii_txd1 i transmit data 1: bit 1 of the 4 data bits that are accepted by the phy for transmission. co_mii_txd2 i transmit data 2: bit 2 of the 4 data bits that are accepted by the phy for transmission. co_mii_txd3 i transmit data 3: bit 3 of the 4 data bits that are accepted by the phy for transmission. co_tx_en i transmit enable: indicates that valid data is presented on the co_mii_txd[3:0] signals, for transmission. co_rx_er (rxd4) oo receive error: asserted to indicate that an error was detected somewhere in the frame presently being transferred from the phy. in symbol interface (5b decoding) mode, this signal is the mii receive data 4: the msb of the received 5-bit symbol code-group. co_col o mii collision detect: asserted to indicate detection of collision condition. co_mii_rxd0 o receive data 0: bit 0 of the 4 data bits that are sent by the phy in the receive path. co_mii_rxd1 o receive data 1: bit 1 of the 4 data bits that are sent by the phy in the receive path. co_mii_rxd2 o receive data 2: bit 2 of the 4 data bits that sent by the phy in the receive path. co_mii_rxd3 o receive data 3: bit 3 of the 4 data bits that sent by the phy in the receive path. co_tx_er (txd4) i mii transmit error: when driven high, the 4b/5b encode process substitutes the transmit error code-group (/h/) for the encoded data word. this input is ignored in 10baset operation. in symbol interface (5b decoding) mode, this signal becomes the mii transmit data 4: the msb of the 5-bit symbol code-group. co_crs o carrier sense: indicate detection of carrier. co_rx_dv o receive data valid: indicates that recovered and decoded data nibbles are being presented on co_mii_rxd[3:0]. co_tx_clk o transmit clock: 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. co_rx_clk o receive clock: 25mhz in 100base-tx mode. 2.5mhz in 10base-t mode. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 657 of 794 rej09b0237-0500 ? management signals signal name type description co_mdi i management data input: serial management data input. co_mdo o management data output: serial management data output. co_mdclk i management clock: serial management clock. co_mdio_dir o management data direction: may be used to control output enabled buffer for mdio. ? general signals signal name type description co_clkin i clock input - phy clock. can be 25mhz either from mck of cpg module or from ck_phy pin. 22.12 signals relevant to phy-if this phy core has a part set up by the phy-if module. (1) phy address the phy address initialized by phyifaddr of phy -if, is same as the one that the ordinary external phy lsi has. it gives each phy a unique addr ess. this address is latched into an internal register during module reset and phy power on reset. originally, it enables a function to manage each phy via the unique address in a multi-phy application. about this phy module, you can not connect multiple phys to the mii interface within the lsi. but phy address is also used to seed the scramb ler, so that please accor d the configuration of phyifaddrr and the phy address on the management interface. (2) operation mode the co_st_mode of the phyifcr of phy-if controls the configuration of 10/100 digital block. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 658 of 794 rej09b0237-0500 default register bit values register 0 register 4 co_st_mode[2:0] of phyifcr mode definitions [ 13,12,10,8] [8,7,6,5] 000 10base-t half duplex. auto-negotiation disabled. 0000 n/a 001 10base-t full duplex. auto-negotiation disabled. 0001 n/a 010 100base-tx half duplex. auto-negotiation disabled.crs is active during transmit & receive. 1000 n/a 011 100base-tx full duplex. auto-negotiation disabled.crs is active during receive. 1001 n/a 100 100base-tx half duplex is advertised. auto- negotiation enabled.crs is active during transmit & receive. 1100 0100 101 reserved.(do not set this mode) 1100 0100 110 power down mode. in this mode the phy wake-up in power-down mode. n/a n/a 111 all capable. auto-negotiation enabled. x10x 1111 22.13 usage notes (1) input clock to phy module the initial clock to phy module is internal clock, mck (= ick/4), but it does work only when it is 25mhz, which is acceptable to phy module. it corresponds to power down mode. for example, even in the application which doesn't use the on-chip phy module, you have to set up the clock to the on-chip phy so that it could be low power consumption mode with power down mode. (2) treatment of pins when phy power supply is not used even when the on-chip phy is not used, supply power to the analog power supply pins for the phy (vcc1a, vcc2a, and vcc3a) and connect the analog ground pins for the phy (vss1a and vss2a) to the ground. pull up the ck-phy pin to vccq through a resistor or pull down the ck-phy pin to vssq through a register. connect pins txp, txm, rxp, and rxm to the phy analog ground. connect the exers1 pin to the phy analog power supply without going through a resistor. do not connect an ything to the tstbusa pin. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 659 of 794 rej09b0237-0500 (3) software reset of the phy the software reset of the on-chip phy of this lsi has a defect in ch aracteristics, which can prevent correct resetting of the phy in some cases . because of this, the ph y should be reset by a module reset, which is generated by setting th e phyifcr register (in the phy-if module). note: 1. software reset refers to the reset whic h is executed by bit 15 of register 0 (basic control) described in section 22.4.2, smi register mapping. 2. module reset refers to the reset whic h is executed by bit 14 of phyifcr (phy-if control register) described in section 23.2, register descriptions, in section 23, phy interface (phy-if). (4) waveform adjustment for tx100 output the ethernet phy module of this lsi has test registers for adjustment of differential output waveforms. using these test registers in thei r initial values produces no problem, but their specifications are shown below to facilitate pr inted circuit board design by the customer. (a) adjustment of tx100 waveform output the on-chip phy module of this lsi has the following adjustment registers as sim registers, which allow waveform adjustment in the tx100 operation. these registers have been designed so that they are not accidentally wr itten. to change their values, fo llow the example procedure shown in "how to use" that is described later. ? register 20: register for changing modes ? register 23: register for waveform adjustment (the register numbers are decimal) ? meanings of the value written to register 23 bit bit name initial value r/w description 15 ? 1 ro reserved the write value should always be 1. 14 to 9 ? 0 ro reserved the write value should always be 0. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 660 of 794 rej09b0237-0500 bit bit name initial value r/w description 8 7 d1cmp d0cmp 1 1 r/w r/w these bits adjust the latter half of the slope (from half to the maximum amplitude). 00: three steps up 01: two steps up 10: one step up 11: regular 6 5 4 d2a d1a d0a 1 0 0 r/w r/w r/w these bits adjust the amplitude. 000: amp 4 stp+ 001: amp 3 stp+ 010: amp 2 stp+ 011: amp 1 stp+ 100: regular 101: amp 1 stp- 110: amp 2 stp- 111: amp 3 stp- 3 2 dasl dbsl 1 0 r/w r/w these bits adjust the first half of the slope (from 0 v to half the amplitude). 00: one step up 01: one step down 10: regular 11: two steps down 1, 0 ? 0 ro reserved the write value should always be 0. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 661 of 794 rej09b0237-0500 output voltage time maximum amplitude maximum amplitude/2 slope adjustment by bits dncmp (n = 1, 0) slope adjustment by bits dnsl (n = a, b) maximum amplitude: because of tx100 output, normally around 1.0 v amplitude adjustment by bits dna (n = 2 to 0) figure 22.10 role of each bit field (example of rising waveform) slope is controlled in four segments ? how to use (example) write to the sim registers in the following sequence. step register to be written value for writing description 1 2 3 4 5 6 7 8 9 0 20 20 20 20 20 23 20 20 h'2100 h'0000 h'0000 h'0400 h'0000 h'0400 h'xxxx h'4416 h'0000 select tx100 mode. (this op eration can be omitted if tx100 full-duplex or tx100 half-duplex mode has been selected by auto-negotiation,) * start register write mode setting. register write mode setting (continued) register write mode setting (continued) register write mode setting (continued) finish register write mode setting. write the setting value. (the initia l value of this register is h'81c8. change the setting as necessary.) validate the setting value (always write this value). terminate the register write mode (return to normal mode). note: the setting of this register is initializ ed during the auto-negotiati on process or when the phy module is reset (including a system re set of the lsi). accordingly, when waveform adjustment is to be performed by this regist er, the above steps must be carried out every time the register is initialized. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 662 of 794 rej09b0237-0500 22.14 guidelines for layout 22.14.1 general guidelines the guidelines for four-lay er boards are shown below. (1) configuration of board layers ? layer 1: top layer (component side), which is a signal layer ? layer 2: ground layer ? layer 3: power layer ? layer 4: bottom layer (solder side), which is a signal layer (2) impedance control ideally, impedance control should satisfy the following. ? single ended traces: 51 ohm 10% ? differential pairs: 99 ohm 10% ? no restrictions on the impedance of short power/grand traces (3) vias vias are a source of impedance mi smatches and distorted waveforms on transmission lines, which can cause problems of signal integrity (noise) and emi issues. for differential signals and fast signal traces, avoid using vias on the signal lines whenever possible. if vias are used on such signal traces, ensure that they do not creat e problems by simulation or other means. (4) notes on routing stubs (branching) cause signal reflections, so they should be 12.7 mm (0.5 inch) or shorter for critical nets. stagger is a bad source of crosst alk, so all the signal traces ar ound the phy should be 25.4 mm (1 inch) or shorter. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 663 of 794 rej09b0237-0500 (5) terminations to reduce signal reflections caused by impedance mismatches, provide damper or terminating resistance at the end-points of signal nets. damp er resistance should be placed close to the signal source, while terminating resistan ce should be placed at the farthe st end-points of their nets. the distance from the signal source or farthest end-point must be shorter than 12.7 mm (0.5 inch). 22.14.2 guidelines for layout since the signals of the phy are analog signals w ith high frequencies and small amplitudes, they are susceptible to digital nois e. so, routing and placement must be done with extra care. an example of connection with a pulse transformer (rj45) is shown in figure 22.11. the codes such as c1 and r2 in the following explanation are the part numbers indicated in figure 22.11. (1) example of connection with a pulse transformer (rj45) 1 pvcc pvss pvss pvss 82[ohm] 82[ohm] c1 c2 c3 c4 r2 r4 r5 r1 r3 cn1 pulse transformer equivalent to tla-6t718 12 12 1 49.9[ohm] 0.01uf/16v 22nf/16v 49.9[ohm] 10[ohm] 2 1 2 1 2 1 2 1 2 1 2 1 2 6.8nf/16v 6.8nf/16v 3 2 4 6 5 7 td+ (tx+) tct (nc) td- (tx-) rd+ (rx+) rct (nc) rd- (rx-) nc gnd (fg) 8 sh_txp note: pvcc: analog power supply pvss: analog ground sh_txm sh_rxp sh_rxm figure 22.11 example of connection with a pulse transformer (rj45) section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 664 of 794 rej09b0237-0500 (2) sample placement 1. the pulse transforme r should be placed close to the phy-related pins of this lsi. 2. components should be place d so that the signal traces of differential pairs, txp/txm and rxp/rxm, do not cross each other. 3. r4 and r5, which are terminating resistor s, should be placed close to this lsi. 4. r1 and r2 should be placed clos e to the pulse tr ansformer (rj45). 5. r3 and c4, which form a filter, should be placed close to the pulse transformer (rj45). 6. c4 of the center tap should be placed close to the pulse transformer (rj45). 7. do not place any compon ents on the bottom side. (3) ground planes layer 2 is divided into logic ground plane and frame ground plane. the logic ground is the combination of digital ground and analog ground. the frame ground is connected to the system ground and the shielding of the rj45 socket so that it is grounded. beware that this ground plane cuts impact the routing on adjacent signal layers. signal traces of l1 and l4 should not run across th e cuts in the ground plane to avoid impedance mismatches and emi problems. mini mize the frame ground area so as to make the logic ground as large and solid as possible. connect the logic ground and frame ground by a ferrite bead or thick signal trace to provide a dc path. for safety, excl ude the area near the leads of the rj45 from the ground area. (4) common power plane layer 3 consists of multiple power planes of vcc and vcc for pll1 and pll2, which supply 1.8 v, and vccq and vccna (n = 1 to 3), which supply 3.3 v. vccna is made up of an area of analog power for the rj45 (connector-type pulse transforme r) and an area of analog power for this lsi. (5) sample routing in the above example, the ground layer is simply divided into two planes while the power layer is divided into more planes. therefore, the top layer (component side) is superior to the bottom layer (solder side) in terms of signal integrity. if possibl e, all the critical signals of the phy, differential signal pairs for example, should be wired in the top layer without any vias. another important thing to be noted about differentia l signal pairs is that the pair of traces of a pair must be strictly equal in length to minimize duty cycle distortion and common mode radiation. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 665 of 794 rej09b0237-0500 (6) clock layout in addition to the clock input for the cpu, an external clock for the phy (ckphy) can also be input to this lsi. analog power supply and analog sign als should be placed far away fr om the oscillator, resonator, and digital devices that produce much noise. clock signal lines should be wired in a layer higher than the ground layer (the top layer (component side) in this ex ample). in addition, clock traces should be kept as far away from other traces as possible. the minimum sp acing is three times of the trace width. section 22 ethernet physical layer transceiver (phy) rev. 5.00 mar. 15, 2007 page 666 of 794 rej09b0237-0500 section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 667 of 794 rej09b0237-0500 section 23 phy interface (phy-if) this is an interface for operation of the on-chip phy on this lsi. 23.1 features ? selectable operation to enable the on-chip phy or to disable (= utilizing an external phy lsi) by pin function controller of ports. ? below settings for the on-chip phy are available. the module reset selectable operation clock of the phy module, the internal cl ock or the exclusive external clock for phy. but the clock of the on-chip phy module has 25 mhz, fixed frequency. section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 668 of 794 rej09b0237-0500 figure 23.1 shows the block diagram of phy-if. cpg pfc pfc ether c phyifcr phyifsmir2 phyifsmir3 phyifaddrr phyifsr internal bus pfy-if register module reset (co_resetb) reset reset internal phy ports selection (clksel) internal clock external clock input phy clock txp/m, rxp/m etc. input/output pins port (etherc inputs) etherc function selected etherc function selected led signals mii signals input pins mii signals output pins [legend] phyifsr: phy-if status register phyifcr: phy-if control register phyifsmir2: phy-if smi register 2 phyifsmir3: phy-if smi register 3 phyifaddrr: phy-if address register figure 23.1 block diagram of phy-if section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 669 of 794 rej09b0237-0500 23.2 register descriptions phy-if has below registers. refer to section 24, list of registers, about the addresses and the status under each operating condition. ? phy-if control register (phyifcr) ? phy-if smi register 2 (phyifsmir2) ? phy-if smi register 3 (phyifsmir3) ? phy-if address register (phyifaddrr) ? phy-if status register (phyifsr) 23.2.1 phy-if control register (phyifcr) phyifcr is a 16-bit readable/writeable register , which sets the operation mode of the on-chip phy module. the changed bit values except co_res etb are taken by the module reset of the on- chip phy with co_resetb. phyifcr is initialized by power-on-reset. it is also initialized as h'c000 in the standby mode. bit bit name initial value r/w description 15 ? 1 r reserved. this bit is always read as 1. the write value should always be 1. 14 co_resetb 1 r/w module reset resets the on-chip phy with software. 0: reset state 1: reset state is released (an initial value) 13 clksel 0 r/w clock selection selects which to provide to on-chip phy, the internal clock or the external clock. 0: uses the internal clock(mck) (an initial value) 1: uses the external clock (ck_phy) 12 to 3 ? 0 r/w reserved. these bits are always read as 0. the write value should always be 0. section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 670 of 794 rej09b0237-0500 bit bit name initial value r/w description 2 1 0 co_st_mode[2] co_st_mode[1] co_st_mode[0] 1 1 0 r/w phy mode decides the initial value of the phy mode. 000: 10base-t half duplex. auto-negotiation disabled. 001: 10base-t full duplex. auto-negotiation disabled. 010: 100base-tx half duplex. auto-negotiation disabled. crs is active during transmit & receive. 011: 100base-tx full duplex. auto-negotiation disabled. crs is active during receive. 100: 100base-tx half duplex is advertised. auto- negotiation enabled. crs is active during transmit & receive. 101: reserved. (do not set this mode.) 110: power down mode. in this mode the phy wake-up in power-down mode (an initial value) 111: all capable. auto-negotiation enabled. 23.2.2 phy -if smi register 2 (phyifsmir2) phyifsmir2 is a 16-bit readable/writeable register, which sets the initial value of smi register 2 in the case of the module re set the on-chip phy module. the changes of this register are taken by the on-chip phy module reset with co_resetb. phyifsmir2 is initialized by power-on-reset. it is also initialized as h'0000 in the standby mode. bit bit name initial value r/w description 15 to 0 co_reg2_oui_in[15-0] all 0 r/w the initial value of smi register 2 (= phy identifier 1)[15-0] section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 671 of 794 rej09b0237-0500 23.2.3 phy -if smi register 3 (phyifsmir3) phyifsmir3 is a 16-bit readable/writeable register, which sets the initial value of smi register 3 in the case of the module re set the on-chip phy module. the changes of this register are taken by the on-chip phy module reset with co_resetb. phyifsmir2 is initialized by power-on-reset. it is also initialized as h'0000 in the standby mode. bit bit name initial value r/w description 15 to 0 co_reg3_oui_in[15-0] all 0 r/w the initial value of smi register 3 (= phy identifier 2)[15-0] 23.2.4 phy -if address register (phyifaddrr) phyifaddrr is a 16-bit readable/writeable regist er, which sets the phy address of the on-chip phy module. the changes of this register are taken by the on-chip phy module reset with co_resetb. phyifaddrr is initialized by power-on-reset. it is also initialized as h'0000 in the standby mode. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved. these bits are always read as 0. the write value should always be 0. 4 to 0 co_st_phyadd[4-0] all 0 r/w the initial value of phy address section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 672 of 794 rej09b0237-0500 23.2.5 phy-if status register (phyifsr) phyifsr is a 16-bit read-only register that shows the status of the on-chip phy module. phyifsr is initialized by power-on-reset. bit bit name initial value r/w description 15 co_pwruprst 1 (ref. description) r power up reset this bit goes to "1" only on detection of power up of the on-chip phy power (vcc1a to vcc3a) and stays at "1" for 21 ms, automatically. 14 to 0 ? 0 r reserved. these bits are always read as 0. the write value should always be 0. section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 673 of 794 rej09b0237-0500 23.3 phy-if operation phy-if is basically for initializing the on-chop phy module. following the procedures described in the following sections, please set up the on-chip phy module with the mii interface like as for the ex ternal phy lsi. the phy module itself goes to power down mode with the initial values of co_st_mode of phyifcr after power-on-reset of the whole lsi at power-up. 23.3.1 the procedures of setting up the on-chip phy please set up with below procedures. 1. release of module stop first of all, release the module stop (mstp20 of stbcr4), if phy-if is in module stop mode. 2. power up reset check the release of power up reset mode, shown in the co_pwruprst-bit of phyifsr with value "0". 3. activation of the on-chip phy module to activate the on-chip phy module, set the pin function registers of port c as something but etherc function, that is, i/o ports and led outputs of the on-chip phy. ? pccrh = h'0000 ? pccrl1 = h'0000 ? pccrl2 = h'ff00 in this case, the lnksta input pin of the etherc is deselected. as the link output of the on- chip phy and link input of the etherc are conn ected in this lsi, the link signal change interrupt can be generated in the same way as the external phy lsi is used. 4 set up of the clock in the case of utilizing the internal clock from cpg, you have to set up the mclkcr during the reset period of the on-chip phy. set the input clock of the phy module as 25 mhz by adjusting the frqcr and mclkcr. do this set up before module reset of the on-chip phy. section 23 phy interface (phy-if) rev. 5.00 mar. 15, 2007 page 674 of 794 rej09b0237-0500 5 the reset of the on-chip phy before you reset the on-chip phy module, please se t the register sets of phy-if parts as you need, except phyifcr. af ter that, set the co_resetb of phyi fcr as zero, to make the on-chip phy reset state. at this moment, you should set the other bits of phyifcr, which corresponds to the operating mode of the on-chip phy. please adjust the waiting time with soft ware-loop, etc., so that you can keep the reset period is over 100 s. 6. release of the reset of the on-chip phy. set only the co_resetb of phyifcr as "1", for releasing the reset stat e of the on-chip phy. after releasing the reset, adjust the waiting time with software loops, etc. as over 20 ms for propagation of reset signal within the phy. 7. set up the on-chip phy module with the mii management frame. the procedures after this step are set up by the mii management frame like an external phy lsi on the market. please refer the section of phy mo dule about the each settings of it. 23.3.2 the procedures of se t up the external phy lsi in the case of utilizing the external phy lsi, select the etherc function of the pin function controllers and then set up the internal register s of the phy lsi with the mii management frame. 1. activation of the external phy lsi. select the etherc functions with pin function controller. ? pccrh = h'0155 ? pccrl1 = h'5555 ? pccrl2 = h'5555 2. set up the external phy lsi with the mii management frame. following procedures are set up by the mii management frame. about the each settings of the phy lsi that you utilize, please refer the documents of it. section 24 list of registers rev. 5.00 mar. 15, 2007 page 675 of 794 rej09b0237-0500 section 24 list of registers the register list gives information on the on-chip i/o register addresses, how the register bits are configured, and the register states in each operating mode. the information is given as shown below. 1. register addresses (address order) ? registers are listed from the lower allocation addresses. ? reserved addresses are indicated by ? in the register name column. do not access the reserved addresses. ? when registers consist of 16 or 32 bits, the addresses of the msbs are given. ? registers are classified accordi ng to functional modules. ? the numbers of access cycles are given. 2. register bits ? bit configurations of the registers are listed in the same order as the register addresses. ? reserved bits are indicated by ? in the bit name column. ? space in the bit name field indicates that the entire register is allo cated to either the counter or data. ? for the registers of 16 or 32 bits, the msb is listed first. 3. register states in each operating mode ? register states are listed in the same order as the register addresses. ? the register states shown here ar e for the basic operating modes. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. section 24 list of registers rev. 5.00 mar. 15, 2007 page 676 of 794 rej09b0237-0500 24.1 register addresses (address order) entries under access size in dicates numbers of bits. the number of access cycles indicate the number of cy cles of the given reference clock. b, w, and l indicate values for 8-, 16-, and 32-bit accesses, respectively. note: access to undefined or reserved addresses is prohibited. since operation or continued operation is not guaranteed when these regist ers are accessed, do not attempt such access. register name abbreviation number of bits address module access size dma source address register_0 sar_0 32 h'f8010020 dmac 16/32 dma destination address register_0 dar_0 32 h'f8010024 dmac 16/32 dma transfer count register_0 dmatcr_0 32 h'f8010028 dmac 16/32 dma channel control register_0 chcr_0 32 h'f801002c dmac 8/16/32 dma source address register_1 sar_1 32 h'f8010030 dmac 16/32 dma destination address register_1 dar_1 32 h'f8010034 dmac 16/32 dma transfer count register_1 dmatcr_1 32 h'f8010038 dmac 16/32 dma channel control register_1 chcr_1 32 h'f801003c dmac 8/16/32 dma source address register_2 sar_2 32 h'f8010040 dmac 16/32 dma destination address register_2 dar_2 32 h'f8010044 dmac 16/32 dma transfer count register_2 dmatcr_2 32 h'f8010048 dmac 16/32 dma channel control register_2 chcr_2 32 h'f801004c dmac 8/16/32 dma source address register_3 sar_3 32 h'f8010050 dmac 16/32 dma destination address register_3 dar_3 32 h'f8010054 dmac 16/32 dma transfer count register_3 dmatcr_3 32 h'f8010058 dmac 16/32 dma channel control register_3 chcr_3 32 h'f801005c dmac 8/16/32 dma operation register dmaor 16 h'f8010060 dmac 16 port a data register h padrh 16 h'f8050000 i/o 8/16 port a io register h paiorh 16 h'f8050004 i/o 8/16 port a control register h1 pacrh1 16 h'f8050008 i/o 8/16 port a control register h2 pacrh2 16 h'f805000a i/o 8/16 port b data register l pbdrl 16 h'f8050012 i/o 8/16 port b io register l pbiorl 16 h'f8050016 i/o 8/16 section 24 list of registers rev. 5.00 mar. 15, 2007 page 677 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size port b control register l1 pbcrl1 16 h'f805001c i/o 8/16 port b control register l2 pbcrl2 16 h'f805001e i/o 8/16 port c data register h pcdrh 16 h'f8050020 i/o 8/16 port c data register l pcdrl 16 h'f8050022 i/o 8/16 port c io register h pciorh 16 h'f8050024 i/o 8/16 port c io register l pciorl 16 h'f8050026 i/o 8/16 port c control register h2 pccrh2 16 h'f805002a i/o 8/16 port c control register l1 pccrl1 16 h'f805002c i/o 8/16 port c control register l2 pccrl2 16 h'f805002e i/o 8/16 port d data register l pddrl 16 h'f8050032 i/o 8/16 port d io register l pdiorl 16 h'f8050036 i/o 8/16 port d control register l2 pdcrl2 16 h'f805003e i/o 8/16 port e data register h pedrh 16 h'f8050040 i/o 8/16 port e data register l pedrl 16 h'f8050042 i/o 8/16 port e io register h peiorh 16 h'f8050044 i/o 8/16 port e io register l peiorl 16 h'f8050046 i/o 8/16 port e control register h1 pecrh1 16 h'f8050048 i/o 8/16 port e control register h2 pecrh2 16 h'f805004a i/o 8/16 port e control register l1 pecrl1 16 h'f805004c i/o 8/16 port e control register l2 pecrl2 16 h'f805004e i/o 8/16 interrupt priority register c iprc 16 h'f8080000 intc 16 interrupt priority register d iprd 16 h'f8080002 intc 16 interrupt priority register e ipre 16 h'f8080004 intc 16 interrupt priority register f iprf 16 h'f8080006 intc 16 interrupt priority register g iprg 16 h'f8080008 intc 16 dma extended resource selector 0 dmars0 16 h'f8090000 dmac 16 dma extended resource selector 1 dmars1 16 h'f8090004 dmac 16 standby control register 3 stbcr3 8 h'f80a0000 power- down mode 8 section 24 list of registers rev. 5.00 mar. 15, 2007 page 678 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size standby control register 4 stbcr4 8 h'f80a0004 power- down mode 8 phy-lsi clock frequency control register mclkcr 8 h'f80a000c cpg 8/16 * instruction register sdir 16 h'f8100200 h-udi 16 id register sdid 32 h'f8100214 h-udi 32/16 interrupt control register 0 icr0 16 h'f8140000 intc 8/16 irq control register irqcr 16 h'f8140002 intc 8/16 irq status register irqsr 16 h'f8140004 intc 8/16 interrupt priority register a ipra 16 h'f8140006 intc 8/16 interrupt priority register b iprb 16 h'f8140008 intc 8/16 frequency control register frqcr 16 h'f815ff80 cpg 16 standby control register stbcr 8 h'f815ff82 power- down mode 8 watch dog timer counter wtcnt 8 h'f815ff84 wdt 8/16 * watch dog timer control/status register wtcsr 8 h'f815ff86 wdt 8/16 * standby control register 2 stbcr2 8 h'f815ff88 power- down mode 8 serial mode register_0 scsmr_0 16 h'f8400000 scif_0 16 bit rate register_0 scbrr_0 8 h'f8400004 scif_0 8 serial control register_0 scscr_0 16 h'f8400008 scif_0 16 transmit fifo data register_0 scftdr_0 8 h'f840000c scif_0 8 serial status register_0 scfsr_0 16 h'f8400010 scif_0 16 receive fifo data register_0 scfrdr_0 8 h'f8400014 scif_0 8 fifo control register_0 scfcr_0 16 h'f8400018 scif_0 16 fifo data count register_0 scfdr_0 16 h'f840001c scif_0 16 serial port register_0 scsptr_0 16 h'f8400020 scif_0 16 line status register_0 sclsr_0 16 h'f8400024 scif_0 16 section 24 list of registers rev. 5.00 mar. 15, 2007 page 679 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size serial mode register_1 scsmr_1 16 h'f8410000 scif_1 16 bit rate register_1 scbrr_1 8 h'f8410004 scif_1 8 serial control register_1 scscr_1 16 h'f8410008 scif_1 16 transmit fifo data register_1 scftdr_1 8 h'f841000c scif_1 8 serial status register_1 scfsr_1 16 h'f8410010 scif_1 16 receive fifo data register_1 scfrdr_1 8 h'f8410014 scif_1 8 fifo control register_1 scfcr_1 16 h'f8410018 scif_1 16 fifo data count register_1 scfdr_1 16 h'f841001c scif_1 16 serial port register_1 scsptr_1 16 h'f8410020 scif_1 16 line status register_1 sclsr_1 16 h'f8410024 scif_1 16 serial mode register_2 scsmr_2 16 h'f8420000 scif_2 16 bit rate register_2 scbrr_2 8 h'f8420004 scif_2 8 serial control register_2 scscr_2 16 h'f8420008 scif_2 16 transmit fifo data register_2 scftdr_2 8 h'f842000c scif_2 8 serial status register_2 scfsr_2 16 h'f8420010 scif_2 16 receive fifo data register_2 scfrdr_2 8 h'f8420014 scif_2 8 fifo control register_2 scfcr_2 16 h'f8420018 scif_2 16 fifo data count register_2 scfdr_2 16 h'f842001c scif_2 16 serial port register_2 scsptr_2 16 h'f8420020 scif_2 16 line status register_2 sclsr_2 16 h'f8420024 scif_2 16 mode register simdr 16 h'f8480000 siof 16 clock select register siscr 16 h'f8480002 siof 16 transmit data assign register sitdar 16 h'f8480004 siof 16 receive data assign register sirdar 16 h'f8480006 siof 16 control data assign register sicdar 16 h'f8480008 siof 16 control register sictr 16 h'f848000c siof 16 fifo control register sifctr 16 h'f8480010 siof 16 status register sistr 16 h'f8480014 siof 16 interrupt enable register siier 16 h'f8480016 siof 16 transmit data register sitdr 32 h'f8480020 siof 32 receive data register sirdr 32 h'f8480024 siof 32 section 24 list of registers rev. 5.00 mar. 15, 2007 page 680 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size transmit control data register sitcr 32 h'f8480028 siof 32 receive control data register sircr 32 h'f848002c siof 32 spi control register spicr 16 h'f8480030 siof 16 phy-if control register ph yifcr 16 h'f8490000 phy-if 8/16 phy-if smi register 2 phyifsmir2 16 h'f8490004 phy-if 8/16 phy-if smi register 3 phyifsmir3 16 h'f8490008 phy-if 8/16 phy-if address register phyifaddrr 16 h'f849000c phy-if 8/16 phy-if status register phyifsr 16 h'f8490010 phy-if 8/16 compare match timer start register cmstr 16 h'f84a0070 cmt 8/16 compare match timer control/status register_0 cmcsr_0 16 h'f84a0072 cmt 8/16 compare match counter_0 cmcnt_0 16 h'f84a0074 cmt 8/16 compare match timer constant register_0 cmcor_0 16 h'f84a0076 cmt 8/16 compare match timer control/status register_1 cmcsr_1 16 h'f84a0078 cmt 8/16 compare match counter_1 cmcnt_1 16 h'f84a007a cmt 8/16 compare match timer constant register_1 cmcor_1 16 h'f84a007c cmt 8/16 hif index register hifidx 32 h'f84d0000 hif 32 hif general status register hifgsr 32 h'f84d0004 hif 32 hif status/control register hifscr 32 h'f84d0008 hif 32 hif memory control register hifmcr 32 h'f84d000c hif 32 hif internal interrupt control register hifiicr 32 h'f84d0010 hif 32 hif external interrupt control register hifeicr 32 h'f84d0014 hif 32 hif address register hifadr 32 h'f84d0018 hif 32 hif data register hifdata 32 h'f84d001c hif 32 hifdreq trigger register hifdtr 32 h'f84d0020 hif 32 hif bank interrupt control register hifbicr 32 h'f84d0024 hif 32 hif boot control register hifbcr 32 h'f84d0040 hif 32 section 24 list of registers rev. 5.00 mar. 15, 2007 page 681 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size common control register cmncr 32 h'f8fd0000 bsc 32 bus control register for area 0 cs0bcr 32 h'f8fd0004 bsc 32 bus control register for area 3 cs3bcr 32 h'f8fd000c bsc 32 bus control register for area 4 cs4bcr 32 h'f8fd0010 bsc 32 bus control register for area 5b cs5bbcr 32 h'f8fd0018 bsc 32 bus control register for area 6b cs6bbcr 32 h'f8fd0020 bsc 32 wait control register for area 0 cs0wcr 32 h'f8fd0024 bsc 32 wait control register for area 3 cs3wcr 32 h'f8fd002c bsc 32 wait control register for area 4 cs4wcr 32 h'f8fd0030 bsc 32 wait control register for area 5b cs5bwcr 32 h'f8fd0038 bsc 32 wait control register for area 6b cs6bwcr 32 h'f8fd0040 bsc 32 sdram control register sdcr 32 h'f8fd0044 bsc 32 refresh timer control/status register rtcsr 32 h'f8fd0048 bsc 32 refresh timer counter rtcnt 32 h'f8fd004c bsc 32 refresh time constant register rtcor 32 h'f8fd0050 bsc 32 e-dmac mode register edmr 32 h'fb000000 e-dmac 32 e-dmac transmit request register edtrr 32 h'fb000004 e-dmac 32 e-dmac receive request register edrrr 32 h'fb000008 e-dmac 32 transmit descriptor list start address register tdlar 32 h'fb00000c e-dmac 32 receive descriptor list start address register rdlar 32 h'fb000010 e-dmac 32 etherc/e-dmac status register eesr 32 h'fb000014 e-dmac 32 etherc/e-dmac status interrupt permission register eesipr 32 h'fb000018 e-dmac 32 transmit/receive status copy enable register trscer 32 h'fb00001c e-dmac 32 receive missed-frame counter register rmfcr 32 h'fb000020 e-dmac 32 transmit fifo threshold register tftr 32 h'fb000024 e-dmac 32 fifo depth register fdr 32 h'fb000028 e-dmac 32 receiving method control register rmcr 32 h'fb00002c e-dmac 32 section 24 list of registers rev. 5.00 mar. 15, 2007 page 682 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size e-dmac operation control register edocr 32 h'fb000030 e-dmac 32 flow control fifo threshold register fcftr 32 h'fb000034 e-dmac 32 transmit interrupt setting register trimd 32 h'fb00003c e-dmac 32 receive buffer write address register rbwar 32 h'fb000040 e-dmac 32 receive descriptor fetch address register rdfar 32 h'fb000044 e-dmac 32 transmit buffer read address register tbrar 32 h'fb00004c e-dmac 32 transmit descriptor fetch address register tdfar 32 h'fb000050 e-dmac 32 etherc mode register ecmr 32 h'fb000160 etherc 32 etherc status register ecsr 32 h'fb000164 etherc 32 etherc interrupt permission regist er ecsipr 32 h'fb000168 etherc 32 phy interface register pir 32 h'fb00016c etherc 32 mac address high register mahr 32 h'fb000170 etherc 32 mac address low register malr 32 h'fb000174 etherc 32 receive frame length register rflr 32 h'fb000178 etherc 32 phy status register psr 32 h'fb00017c etherc 32 transmit retry over counter register trocr 32 h'fb000180 etherc 32 delayed collision detect counter register cdcr 32 h'fb000184 etherc 32 lost carrier counter register lccr 32 h'fb000188 etherc 32 carrier not detect counter register cndcr 32 h'fb00018c etherc 32 crc error frame receive counter register cefcr 32 h'fb000194 etherc 32 frame receive error counter register frecr 32 h'fb000198 etherc 32 too-short frame receive counter register tsfrcr 32 h'fb00019c etherc 32 too-long frame receive counter register tlfrcr 32 h'fb0001a0 etherc 32 residual-bit frame counter register rfcr 32 h'fb0001a4 etherc 32 multicast address frame receive counter register mafcr 32 h'fb0001a8 etherc 32 ipg setting register ipgr 32 h'fb0001b4 etherc 32 section 24 list of registers rev. 5.00 mar. 15, 2007 page 683 of 794 rej09b0237-0500 register name abbreviation number of bits address module access size automatic pause frame set register apr 32 h'fb0001b8 etherc 32 manual pause frame set register mpr 32 h'fb0001bc etherc 32 automatic pause frame retransfer count set register tpauser 32 h'fb0001c4 etherc 32 break data register b bdrb 32 h'ffffff90 ubc 32 break data mask register b bdmrb 32 h'ffffff94 ubc 32 break control register brcr 32 h'ffffff98 ubc 32 execution times break register betr 16 h'ffffff9c ubc 16 break address register b barb 32 h'ffffffa0 ubc 32 break address mask register b bamrb 32 h'ffffffa4 ubc 32 break bus cycle register b bbrb 16 h'ffffffa8 ubc 16 branch source register brsr 32 h'ffffffac ubc 32 break address register a bara 32 h'ffffffb0 ubc 32 break address mask register a bamra 32 h'ffffffb4 ubc 32 break bus cycle register a bbra 16 h'ffffffb8 ubc 16 branch destination register brdr 32 h'ffffffbc ubc 32 cache control register 1 ccr1 32 h'ffffffec cache 32 note: * the numbers of access cycles are eight bits when reading and 16 bits when writing. section 24 list of registers rev. 5.00 mar. 15, 2007 page 684 of 794 rej09b0237-0500 24.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module sar_0 dmac dar_0 dmatcr_0 chcr_0 ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_1 dar_1 section 24 list of registers rev. 5.00 mar. 15, 2007 page 685 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dmatcr_1 dmac chcr_1 ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_2 dar_2 dmatcr_2 chcr_2 ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_3 section 24 list of registers rev. 5.00 mar. 15, 2007 page 686 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dar_3 dmac dmatcr_3 chcr_3 ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de dmaor ? ? cms1 cms0 ? ? pr1 pr0 ? ? ? ? ? ae nmif dme padrh ? ? ? ? ? ? pa25dr pa24dr i/o pa23dr pa22dr pa21dr pa20dr pa19dr pa18dr pa17dr pa16dr paiorh ? ? ? ? ? ? pa25ior pa24ior pa23ior pa22ior pa21ior pa20ior pa19ior pa18ior pa17ior pa16ior pacrh1 ? ? ? ? ? ? ? ? ? ? ? ? pa25md1 pa25md0 pa24md1 pa24md0 pacrh2 pa23md1 pa23md0 pa22md1 pa22md0 pa21md1 pa21md0 ? pa20md0 ? pa19md0 ? pa18md0 ? pa17md0 ? pa16md0 pbdrl ? ? pb13dr pb12dr pb11dr pb10dr pb9dr pb8dr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr pbiorl ? ? pb13ior pb12ior pb11ior pb10ior pb9ior pb8ior pb7ior pb6ior pb5ior pb4ior pb3ior pb2ior pb1ior pb0ior pbcrl1 ? ? ? ? ? pb13md0 ? pb12md0 ? pb11md0 ? pb10md0 ? pb9md0 ? pb8md0 pbcrl2 ? pb7md0 ? pb6md0 ? pb5md0 ? pb4md0 ? pb3md0 ? pb2md0 ? pb1md0 ? pb0md0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 687 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pcdrh ? ? ? ? ? ? ? ? i/o ? ? ? pc20dr pc19dr pc18dr pc17dr pc16dr pcdrl pc15dr pc14dr pc13dr pc12d r pc11dr pc10dr pc9dr pc8dr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr pciorh ? ? ? ? ? ? ? ? ? ? ? pc20ior pc19ior pc18i or pc17ior pc16ior pciorl pc15ior pc14ior pc 13ior pc12ior pc11ior pc 10ior pc9ior pc8ior pc7ior pc6ior pc5ior pc4ior pc3ior pc2i or pc1ior pc0ior pccrh2 ? ? ? ? ? ? ? pc20md0 ? pc19md0 ? pc18md0 ? pc17md0 ? pc16md0 pccrl1 ? pc15md0 ? pc14md0 ? pc13md0 ? pc12md0 ? pc11md0 ? pc10md0 ? pc9md0 ? pc8md0 pccrl2 pc7md1 pc7md0 pc6md1 pc6md0 pc5md1 pc5md0 pc4md1 pc4md0 ? pc3md0 ? pc2md0 ? pc1md0 ? pc0md0 pddrl ? ? ? ? ? ? ? ? pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr pdiorl ? ? ? ? ? ? ? ? pd7ior pd6ior pd5ior pd4ior pd3ior pd2i or pd1ior pd0ior pdcrl2 pd7md1 pd7md0 pd6md1 pd6md0 pd5md1 pd5md0 pd4md1 pd4md0 pd3md1 pd3md0 pd2md1 pd2md0 pd1md1 pd1md0 pd0md1 pd0md0 pedrh ? ? ? ? ? ? ? pe24dr pe23dr pe22dr pe21dr pe20dr pe19dr pe18dr pe17dr pe16dr pedrl pe15dr pe14dr pe13dr pe12 dr pe11dr pe10dr pe9dr pe8dr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr peiorh ? ? ? ? ? ? ? pe24ior pe23ior pe22ior pe21ior pe20ior pe19ior pe18ior pe17ior pe16ior peiorl pe15ior pe14ior pe13ior pe12i or pe11ior pe10ior pe9ior pe8ior pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior pecrh1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? pe24md1 pe24md0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 688 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pecrh2 pe23md1 pe23md0 pe22md1 pe22md0 pe21md1 pe21md0 pe20md1 pe20md0 i/o pe19md1 pe19md0 pe18md1 pe18md0 pe17md1 pe17md0 pe16md1 pe16md0 pecrl1 pe15md1 pe15md0 pe14md1 pe14md0 pe13md1 pe13md0 pe12md1 pe12md0 pe11md1 pe11md0 pe10md1 pe10md0 pe9md1 pe9md0 ? pe8md0 pecrl2 ? pe7md0 pe6md1 pe6md0 ? pe5md0 pe4md1 pe4md0 ? pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 iprc iprc15 iprc14 iprc13 iprc12 iprc11 iprc10 iprc9 iprc8 intc iprc7 iprc6 iprc5 iprc4 iprc3 iprc2 iprc1 iprc0 iprd iprd15 iprd14 iprd13 iprd 12 iprd11 iprd10 iprd9 iprd8 iprd7 iprd6 iprd5 iprd4 ? ? ? ? ipre ipre15 ipre14 ipre13 ipre12 ipre11 ipre10 ipre9 ipre8 ? ? ? ? ? ? ? ? iprf iprf15 iprf14 iprf13 iprf 12 iprf11 iprf10 iprf9 iprf8 iprf7 iprf6 iprf5 iprf4 iprf3 iprf2 iprf1 iprf0 iprg iprg15 iprg14 iprg13 iprg12 ? ? ? ? ? ? ? ? ? ? ? ? dmars0 c1mid5 c1mid4 c1 mid3 c1mid2 c1mid1 c1mi d0 c1rid1 c1rid0 dmac c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 c0rid1 c0rid0 dmars1 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 c3rid1 c3rid0 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 c2rid1 c2rid0 stbcr3 ? ? ? mstp15 ? mstp13 mstp12 mstp11 stbcr4 ? ? ? mstp23 ? mstp21 mstp20 mstp19 power- down mode mclkcr flscs1 flscs0 ? ? ? fldivs2 fldivs1 fldivs0 cpg sdir ti7 ti6 ti5 ti4 ti3 ti2 ti1 ti0 h-udi ? ? ? ? ? ? ? ? sdid did31 did30 did29 did28 did27 did26 did25 did24 did23 did22 did21 did20 did19 did18 did17 did16 did15 did14 did13 did12 did11 did10 did9 did8 did7 did6 did5 did4 did3 did2 did1 did0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 689 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module icr0 nmil ? ? ? ? ? ? nmie intc ? ? ? ? ? ? ? ? irqcr irq71s irq70s ir q61s irq60s irq51s irq50s irq41s irq40s irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s irqsr irq7l irq6l irq5l irq 4l irq3l irq2l irq1l irq0l irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f ipra ipra15 ipra14 ipra13 ipra12 ipra11 ipra10 ipra9 ipra8 ipra7 ipra6 ipra5 ipra4 ipra3 ipra2 ipra1 ipra0 iprb iprb15 iprb14 iprb13 iprb12 iprb11 iprb10 iprb9 iprb8 iprb7 iprb6 iprb5 iprb4 iprb3 iprb2 iprb1 iprb0 frqcr ? ? ? ckoen ? stc2 stc1 stc0 cpg ? ? ? ? ? pfc2 pfc1 pfc0 stbcr stby ? ? ? mdchg ? ? ? power- down mode wtcnt bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdt wtcsr tme wt/it ? wovf iovf cks2 cks1 cks0 stbcr2 mstp10 mstp9 mstp8 ? ? mstp5 mstp4 ? power- down mode scsmr_0 ? ? ? ? ? ? ? ? scif_0 c/a chr pe o/e stop ? cks1 cks0 scbrr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scscr_0 ? ? ? ? ? ? ? ? tie rie te re reie ? cke1 cke0 scftdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfsr_0 per3 per2 per1 per0 fer3 fer2 fer1 fer0 er tend tdfe brk fer per rdf dr scfrdr_0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfcr_0 ? ? ? ? ? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop section 24 list of registers rev. 5.00 mar. 15, 2007 page 690 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module scfdr_0 ? ? ? t4 t3 t2 t1 t0 scif_0 ? ? ? r4 r3 r2 r1 r0 scsptr_0 ? ? ? ? ? ? ? ? rtsio rtsdt ctsio ctsd t sckio sckdt spbio spbdt sclsr_0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? orer scsmr_1 ? ? ? ? ? ? ? ? scif_1 c/a chr pe o/e stop ? cks1 cks0 scbrr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scscr_1 ? ? ? ? ? ? ? ? tie rie te re reie ? cke1 cke0 scftdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfsr_1 per3 per2 per1 per0 fer3 fer2 fer1 fer0 er tend tdfe brk fer per rdf dr scfrdr_1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfcr_1 ? ? ? ? ? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scfdr_1 ? ? ? t4 t3 t2 t1 t0 ? ? ? r4 r3 r2 r1 r0 scsptr_1 ? ? ? ? ? ? ? ? rtsio rtsdt ctsio ctsd t sckio sckdt spbio spbdt sclsr_1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? orer scsmr_2 ? ? ? ? ? ? ? ? scif_2 c/a chr pe o/e stop ? cks1 cks0 scbrr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scscr_2 ? ? ? ? ? ? ? ? tie rie te re reie ? cke1 cke0 scftdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfsr_2 per3 per2 per1 per0 fer3 fer2 fer1 fer0 er tend tdfe brk fer per rdf dr section 24 list of registers rev. 5.00 mar. 15, 2007 page 691 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module scfrdr_2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scif_2 scfcr_2 ? ? ? ? ? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scfdr_2 ? ? ? t4 t3 t2 t1 t0 ? ? ? r4 r3 r2 r1 r0 scsptr_2 ? ? ? ? ? ? ? ? ? (reserved) ? (reserved) ? (reserved) ? (reserved) sckio sckdt spbio spbdt sclsr_2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? orer simdr trmd1 trmd0 syncat re dg fl3 fl2 fl1 fl0 siof txdiz rcim syncac syncdl ? ? ? ? siscr mssel msimm ? brps4 brps3 brps2 brps1 brps0 ? ? ? ? ? brdv2 brdv1 brdv0 sitdar tdle ? ? ? tdla3 tdla2 tdla1 tdla0 tdre tlrep ? ? tdra3 tdra2 tdra1 tdra0 sirdar rdle ? ? ? rdla3 rdla2 rdla1 rdla0 rdre ? ? ? rdra3 rdra2 rdra1 rdra0 sicdar cd0e ? ? ? cd0a3 cd0a2 cd0a1 cd0a0 cd1e ? ? ? cd1a3 cd1a2 cd1a1 cd1a0 sictr scke fse ? ? ? ? txe rxe ? ? ? ? ? ? txrst rxrst sifctr tfwm2 tfwm1 tfwm0 tfua4 tfua3 tfua2 tfua1 tfua0 rfwm2 rfwm1 rfwm0 rfua4 rfua3 rfua2 rfua1 rfua0 sistr ? tcrdy tfemp tdreq ? rcrdy rfful rdreq ? ? saerr fserr tfovf tfudf rfudf rfovf siier tdmae tcrdye tfempe tdreqe rdmae rcrdye rffule rdreqe ? ? saerre fserre tfovfe tfudfe rfudfe rfovfe section 24 list of registers rev. 5.00 mar. 15, 2007 page 692 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module sitdr sitdl15 sitdl14 si tdl13 sitdl12 sitdl11 sitd l10 sitdl9 sitdl8 siof sitdl7 sitdl6 sitdl5 sitdl4 sitdl3 sitdl2 sitdl1 sitdl0 sitdr15 sitdr14 sitdr1 3 sitdr12 sitdr11 sitd r10 sitdr9 sitdr8 sitdr7 sitdr6 sitdr5 sitdr4 sitdr3 sitdr2 si tdr1 sitdr0 sirdr sirdl15 sirdl14 si rdl13 sirdl12 sirdl11 si rdl10 sirdl9 sirdl8 sirdl7 sirdl6 sirdl5 sirdl4 sirdl3 sirdl2 sirdl1 sirdl0 sirdr15 sirdr14 sirdr13 sirdr12 sirdr11 sirdr10 sirdr9 sirdr8 sirdr7 sirdr6 sirdr5 sirdr4 sirdr3 sirdr2 sirdr1 sirdr0 sitcr sitc015 sitc014 si tc013 sitc012 sitc011 si tc010 sitc09 sitc08 sitc07 sitc06 sitc05 sitc04 sitc03 sitc02 sitc01 sitc00 sitc115 sitc114 sitc113 sitc112 sitc111 sitc110 sitc19 sitc18 sitc17 sitc16 sitc15 sitc14 sitc13 sitc12 sitc11 sitc10 sircr sirc015 sirc014 si rc013 sirc012 sirc011 si rc010 sirc09 sirc08 sirc07 sirc06 sirc05 sirc04 sirc03 sirc02 sirc01 sirc00 sirc115 sirc114 sirc113 sirc112 sirc111 sirc110 sirc19 sirc18 sirc17 sirc16 sirc15 sirc14 sirc13 sirc12 sirc11 sirc10 spicr spim ? cpha cpol ? ? ? ss0e ? ? ssast1 ssast0 ? ? fld1 fld0 phyifcr ? co_resetb cksel ? ? ? ? ? phy-if ? ? ? ? ? co_st_ mode[2] co_st_ mode[1] co_st_ mode[0] phyifsmir2 co_reg2_o ui_in[15] co_reg2_o ui_in[14] co_reg2_o ui_in[13] co_reg2_o ui_in[12] co_reg2_o ui_in[11] co_reg2_o ui_in[10] co_reg2_o ui_in[9] co_reg2_o ui_in[8] co_reg2_o ui_in[7] co_reg2_o ui_in[6] co_reg2_o ui_in[5] co_reg2_o ui_in[4] co_reg2_o ui_in[3] co_reg2_o ui_in[2] co_reg2_o ui_in[1] co_reg2_o ui_in [0] phyifsmir3 co_reg3_o ui_in[15] co_reg3_o ui_in[14] co_reg3_o ui_in[13] co_reg3_o ui_in[12] co_reg3_o ui_in[11] co_reg3_o ui_in[10] co_reg3_o ui_in[9] co_reg3_o ui_in[8] co_reg3_o ui_in[7] co_reg3_o ui_in[6] co_reg3_o ui_in[5] co_reg3_o ui_in[4] co_reg3_o ui_in[3] co_reg3_o ui_in[2] co_reg3_o ui_in[1] co_reg3_o ui_in[0] phyifaddrr ? ? ? ? ? ? ? ? ? ? ? co_st_phy add[4] co_st_phy add[3] co_st_phy add[2] co_st_phy add[1] co_st_phy add[0] section 24 list of registers rev. 5.00 mar. 15, 2007 page 693 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module phyifsr co_pwrupr st ? ? ? ? ? ? ? phy-if ? ? ? ? ? ? ? ? cmstr ? ? ? ? ? ? ? ? cmt ? ? ? ? ? ? str1 str0 cmcsr_0 ? ? ? ? ? ? ? ? cmf cmie ? ? ? ? cks1 cks0 cmcnt_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmcor_0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmcsr_1 ? ? ? ? ? ? ? ? cmf cmie ? ? ? ? cks1 cks0 cmcnt_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmcor_1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hifidx ? ? ? ? ? ? ? ? hif ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reg5 reg4 reg3 reg2 reg1 reg0 byte1 byte0 hifgsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? status15 status14 status13 status12 status11 status10 status9 status8 status7 status6 status5 status4 status3 status2 status1 status0 hifscr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dmd dpol bmd bsel ? ? md1 ? ? wbswp edn bo section 24 list of registers rev. 5.00 mar. 15, 2007 page 694 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module hifmcr ? ? ? ? ? ? ? ? hif ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? lock ? wt ? rd ? ? ai/ad hifiicr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iic6 iic5 iic4 iic3 iic2 iic1 iic0 iir hifeicr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? eic6 eic5 eic4 eic3 eic2 eic1 eic0 eir hifadr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a9 a8 a7 a6 a5 a4 a3 a2 ? ? hifdata d31 d30 d29 d 28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hifdtr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dtrg hifbicr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bie bif section 24 list of registers rev. 5.00 mar. 15, 2007 page 695 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module hifbcr ? ? ? ? ? ? ? ? hif ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ac cmncr ? ? ? ? ? ? ? ? bsc ? ? ? ? ? ? ? ? ? ? ? map ? ? ? ? ? ? ? ? endian ? hizmem hizcnt cs0bcr ? ? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs3bcr ? ? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs4bcr ? ? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs5bbcr ? ? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs6bbcr ? ? iww1 iww0 ? iwrwd1 iwrwd0 ? iwrws1 iwrws0 ? iwrrd1 iwrrd0 ? iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? section 24 list of registers rev. 5.00 mar. 15, 2007 page 696 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cs0wcr ? ? ? ? ? ? ? ? bsc ? ? ? ? ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs3wcr ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? ? ? wr3 wr2 wr1 wr0 wm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cs3wcr (when sdram is in use) ? wtrp1 wtrp0 ? wtrcd1 wtrcd0 ? a3cl1 a3cl0 ? ? trwl1 trwl0 ? wtrc1 wtrc0 cs4wcr ? ? ? ? ? ? ? ? ? ? ? bas ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs5bwcr ? ? ? ? ? ? ? ? ? ? ? ? ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 ? ? ? ? ? ? ? ? ? ? sa1 sa0 ? ? ? ? cs5bwcr (when pcmcia is in use) ? ted3 ted2 ted1 ted0 pcw3 pcw2 pcw1 pcw0 wm ? ? teh3 teh2 teh1 teh0 cs6bwcr ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 697 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ? ? ? ? ? ? ? ? bsc ? ? sa1 sa0 ? ? ? ? cs6bwcr (when pcmcia is in use) ? ted3 ted2 ted1 ted0 pcw3 pcw2 pcw1 pcw0 wm ? ? teh3 teh2 teh1 teh0 sdcr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rfsh rmode ? bactv ? ? ? a3row1 a3row0 ? a3col1 a3col0 rtcsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmf ? cks2 cks1 cks0 rrc2 rrc1 rrc0 rtcnt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtcor ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 edmr ? ? ? ? ? ? ? ? e-dmac ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? de dl1 dl0 ? ? ? swr edtrr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tr section 24 list of registers rev. 5.00 mar. 15, 2007 page 698 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module edrrr ? ? ? ? ? ? ? ? e-dmac ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rr tdlar tdla31 tdla30 tdla29 tdla 28 tdla27 tdla26 tdla25 tdla24 tdla23 tdla22 tdla21 tdla20 tdla19 tdla18 tdla17 tdla16 tdla15 tdla14 tdla13 tdla12 tdla11 tdla10 tdla9 tdla8 tdla7 tdla6 tdla5 tdla4 tdla3 tdla2 tdla1 tdla0 rdlar rdla31 rdla30 rdla29 rdla28 rdla27 rdla26 rdla25 rdla24 rdla23 rdla22 rdla21 rdla20 rdla19 rdla18 rdla17 rdla16 rdla15 rdla14 rdla13 rdla12 rdla11 rdla10 rdla9 rdla8 rdla7 rdla6 rdla5 rdla4 rdla3 rdla2 rdla1 rdla0 eesr ? twb ? ? ? tabt rabt rfcof ade eci tc tde tfuf fr rde rfof ? ? ? ? cnd dlc cd tro rmaf ? ? rrf rtlf rtsf pre cerf eesipr ? twbip ? ? ? tabtip rabtip rfcofip adeip eciip tcip tdeip tfu fip frip rdeip rfofip ? ? ? ? cndip dlcip cdip troip rmafip ? ? rrfip rtlfip rtsfip preip cerfip trscer ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cndce dlcce cdce troce rmafce ? ? rrfce rtlfce rtsfce prece cerfce rmfcr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mfc15 mfc14 mfc13 mfc12 mfc11 mfc10 mfc9 mfc8 mfc7 mfc6 mfc5 mfc4 mfc3 mfc2 mfc1 mfc0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 699 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tftr ? ? ? ? ? ? ? ? e-dmac ? ? ? ? ? ? ? ? ? ? ? ? ? tft10 tft9 tft8 tft7 tft6 tft5 tft4 tft3 tft2 tft1 tft0 fdr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tfd2 tfd1 tfd0 ? ? ? ? ? rfd2 rfd1 rfd0 rmcr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rnc edocr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fec aec edh ? fcftr ? ? ? ? ? ? ? ? ? ? ? ? ? rff2 rff1 rff0 ? ? ? ? ? ? ? ? ? ? ? ? ? rfd2 rfd1 rfd0 trimd ? ? ? ? ? ? ? ? etherc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tis rbwar rbwa31 rbwa30 rbwa29 rbwa28 rbwa27 rbwa26 rbwa25 rbwa24 rbwa23 rbwa22 rbwa21 rbwa20 rbwa19 rbwa18 rbwa17 rbwa16 rbwa15 rbwa14 rbwa13 rbwa12 rbwa11 rbwa10 rbwa9 rbwa8 rbwa7 rbwa6 rbwa5 rbwa4 rbwa3 rbwa2 rbwa1 rbwa0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 700 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module rdfar rdfa31 rdfa30 rdfa29 rdfa28 rdfa27 rdfa26 rdfa25 rdfa24 etherc rdfa23 rdfa22 rdfa21 rdfa20 rdfa19 rdfa18 rdfa17 rdfa16 rdfa15 rdfa14 rdfa13 rdfa12 rdfa11 rdfa10 rdfa9 rdfa8 rdfa7 rdfa6 rdfa5 rdfa4 rdfa3 rdfa2 rdfa1 rdfa0 tbrar tbra31 tbra30 tbra29 tbra 28 tbra27 tbra26 tbra25 tbra24 tbra23 tbra22 tbra21 tbra20 tbra19 tbra18 tbra17 tbra16 tbra15 tbra14 tbra13 tbra12 tbra11 tbra10 tbra9 tbra8 tbra7 tbra6 tbra5 tbra4 tbra3 tbra2 tbra1 tbra0 tdfar tdfa31 tdfa30 tdfa29 tdfa28 tdfa27 tdfa26 tdfa25 tdfa24 tdfa23 tdfa22 tdfa21 tdfa20 tdfa19 tdfa18 tdfa17 tdfa16 tdfa15 tdfa14 tdfa13 tdfa12 tdfa11 tdfa10 tdfa9 tdfa8 tdfa7 tdfa6 tdfa5 tdfa4 tdfa3 tdfa2 tdfa1 tdfa0 ecmr ? ? ? ? ? ? ? ? ? ? ? ? zpf pfr rxf txf ? ? ? prcef ? ? mpde ? ? pe te ? ilb elb dm prm ecsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? psrto ? lchng mpd icd ecsipr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? psrtoip ? lchngip mpdip icdip pir ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mdi mdo mmd mdc section 24 list of registers rev. 5.00 mar. 15, 2007 page 701 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module mahr ma47 ma46 ma45 ma44 ma43 ma42 ma41 ma40 etherc ma39 ma38 ma37 ma36 ma35 ma34 ma33 ma32 ma31 ma30 ma29 ma28 ma27 ma26 ma25 ma24 ma23 ma22 ma21 ma20 ma19 ma18 ma17 ma16 malr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ma15 ma14 ma13 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 rflr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rfl11 rfl10 rfl9 rfl8 rfl7 rfl6 rfl5 rfl4 rfl3 rfl2 rfl1 rfl0 psr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? lmon trocr troc31 troc30 troc29 troc28 troc27 troc26 troc25 troc24 troc23 troc22 troc21 troc20 tr oc19 troc18 troc17 troc16 troc15 troc14 troc13 troc12 troc11 troc10 troc9 troc8 troc7 troc6 troc5 troc4 troc3 troc2 troc1 troc0 cdcr cosdc31 cosdc30 cosdc29 cosdc 28 cosdc27 cosdc26 cosdc25 cosdc24 cosdc23 cosdc22 cosdc21 cosdc 20 cosdc19 cosdc18 cosdc17 cosdc16 cosdc15 cosdc14 cosdc13 cosdc12 cosdc11 cosdc10 cosdc9 cosdc8 cosdc7 cosdc6 cosdc5 cosdc4 cosdc3 cosdc2 co sdc1 cosdc0 lccr lcc31 lcc30 lcc29 lcc28 lcc27 lcc26 lcc25 lcc24 lcc23 lcc22 lcc21 lcc20 lcc19 lcc18 lcc17 lcc16 lcc15 lcc14 lcc13 lcc12 lcc11 lcc10 lcc9 lcc8 lcc7 lcc6 lcc5 lcc4 lcc3 lcc2 lcc1 lcc0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 702 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cndcr cndc31 cndc30 cndc29 cndc28 cndc 27 cndc26 cndc25 cndc24 etherc cndc23 cndc22 cndc21 cndc20 cndc19 cndc18 cndc17 cndc16 cndc15 cndc14 cndc13 cndc12 cndc11 cndc10 cndc9 cndc8 cndc7 cndc6 cndc5 cndc4 cndc3 cndc2 cndc1 cndc0 cefcr cefc31 cefc30 cefc29 cefc28 cefc27 cefc26 cefc25 cefc24 cefc23 cefc22 cefc21 cefc20 cefc19 cefc18 cefc17 cefc16 cefc15 cefc14 cefc13 cefc12 cefc11 cefc10 cefc9 cefc8 cefc7 cefc6 cefc5 cefc4 cefc3 cefc2 cefc1 cefc0 frecr frec31 frec30 frec29 frec 28 frec27 frec26 frec25 frec24 frec23 frec22 frec21 frec20 frec19 frec18 frec17 frec16 frec15 frec14 frec13 frec12 frec11 frec10 frec9 frec8 frec7 frec6 frec5 frec4 frec3 frec2 frec1 frec0 tsfrcr tsfc31 tsfc30 tsfc29 tsfc28 tsfc27 tsfc26 tsfc25 tsfc24 tsfc23 tsfc22 tsfc21 tsfc20 tsfc19 tsfc18 tsfc17 tsfc16 tsfc15 tsfc14 tsfc13 tsfc12 tsfc11 tsfc10 tsfc9 tsfc8 tsfc7 tsfc6 tsfc5 tsfc4 tsfc3 tsfc2 tsfc1 tsfc0 tlfrcr tlfc31 tlfc30 tlfc29 tlfc28 tlfc27 tlfc26 tlfc25 tlfc24 tlfc23 tlfc22 tlfc21 tlfc20 tlfc19 tlfc18 tlfc17 tlfc16 tlfc15 tlfc14 tlfc13 tlfc12 tlfc11 tlfc10 tlfc9 tlfc8 tlfc7 tlfc6 tlfc5 tlfc4 tlfc3 tlfc2 tlfc1 tlfc0 rfcr rfc31 rfc30 rfc29 rfc28 rfc27 rfc26 rfc25 rfc24 rfc23 rfc22 rfc21 rfc20 rfc19 rfc18 rfc17 rfc16 rfc15 rfc14 rfc13 rfc12 rfc11 rfc10 rfc9 rfc8 rfc7 rfc6 rfc5 rfc4 rfc3 rfc2 rfc1 rfc0 mafcr mafc31 mafc30 mafc29 mafc28 mafc27 mafc26 mafc25 mafc24 mafc23 mafc22 mafc21 mafc20 mafc19 mafc18 mafc17 mafc16 mafc15 mafc14 mafc13 mafc12 mafc11 mafc10 mafc9 mafc8 mafc7 mafc6 mafc5 mafc4 mafc3 mafc2 mafc1 mafc0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 703 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ipgr ? ? ? ? ? ? ? ? etherc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ipg4 ipg3 ipg2 ipg1 ipg0 apr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ap15 ap14 ap13 ap12 ap11 ap10 ap9 ap8 ap7 ap6 ap5 ap4 ap3 ap2 ap1 ap0 mpr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mp15 mp14 mp13 mp12 mp11 mp10 mp9 mp8 mp7 mp6 mp5 mp4 mp3 mp2 mp1 mp0 tpauser ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tpause 15 tpause 14 tpause 13 tpause 12 tpause 11 tpause 10 tpause 9 tpause 8 tpause7 tpause6 tpau se5 tpause4 tpause3 tpau se2 tpause1 tpause0 bdrb bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 ubc bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 bdmrb bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 bdmb23 bdmb22 bdmb21 bdmb20 bd mb19 bdmb18 bdmb17 bdmb16 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 brcr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? scmfca scmfcb scmfda scmfdb pcte pcba ? ? dbeb pcbb ? ? seq ? ? etbe section 24 list of registers rev. 5.00 mar. 15, 2007 page 704 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module betr ? ? ? ? ? ? ? ? ubc ? ? ? ? ? ? ? ? ? ? ? ? bet11 bet10 bet9 bet8 bet7 bet6 bet5 bet4 bet3 bet2 bet1 bet0 barb bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bamrb bamb31 bamb30 bamb29 bamb 28 bamb27 bamb26 bamb25 bamb24 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 bbrb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 brsr svf ? ? ? bsa27 bsa26 bsa25 bsa24 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 bara baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 bamra bama31 bama30 bama29 bama 28 bama27 bama26 bama25 bama24 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 section 24 list of registers rev. 5.00 mar. 15, 2007 page 705 of 794 rej09b0237-0500 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module bbra ? ? ? ? ? ? ? ? ubc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 brdr dvf ? ? ? bda27 bda26 bda25 bda24 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 ccr1 ? ? ? ? ? ? ? ? cache ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cf cb wt ce section 24 list of registers rev. 5.00 mar. 15, 2007 page 706 of 794 rej09b0237-0500 24.3 register states in each processing state module abbr. address power-on reset software standby module standby sleep dmac sar_0 h'f8010020 initialized retained retained retained dar_0 h'f8010024 initialized retained retained retained dmatcr_0 h'f8010028 initialized retained retained retained chcr_0 h'f801002c initialized retained retained retained sar_1 h'f8010030 initialized retained retained retained dar_1 h'f8010034 initialized retained retained retained dmatcr_1 h'f8010038 initialized retained retained retained chcr_1 h'f801003c initialized retained retained retained sar_2 h'f8010040 initialized retained retained retained dar_2 h'f8010044 initialized retained retained retained dmatcr_2 h'f8010048 initialized retained retained retained chcr_2 h'f801004c initialized retained retained retained sar_3 h'f8010050 initialized retained retained retained dar_3 h'f8010054 initialized retained retained retained dmatcr_3 h'f8010058 initialized retained retained retained chcr_3 h'f801005c initialized retained retained retained dmaor h'f8010060 initialized retained retained retained i/o padrh h'f8050000 initialized retained ? * 3 retained paiorh h'f8050004 initialized retained ? * 3 retained pacrh1 h'f8050008 initialized retained ? * 3 retained pacrh2 h'f805000a initialized retained ? * 3 retained pbdrl h'f8050012 initialized retained ? * 3 retained pbiorl h'f8050016 initialized retained ? * 3 retained pbcrl1 h'f805001c initialized retained ? * 3 retained pbcrl2 h'f805001e initialized retained ? * 3 retained pcdrh h'f8050020 initialized retained ? * 3 retained pcdrl h'f8050022 initialized retained ? * 3 retained pciorh h'f8050024 initialized retained ? * 3 retained pciorl h'f8050026 initialized retained ? * 3 retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 707 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep i/o pccrh2 h'f805002a initialized retained ? * 3 retained pccrl1 h'f805002c initialized retained ? * 3 retained pccrl2 h'f805002e initialized retained ? * 3 retained pddrl h'f8050032 initialized retained ? * 3 retained pdiorl h'f8050036 initialized retained ? * 3 retained pdcrl2 h'f805003e initialized retained ? * 3 retained pedrh h'f8050040 initialized retained ? * 3 retained pedrl h'f8050042 initialized retained ? * 3 retained peiorh h'f8050044 initialized retained ? * 3 retained peiorl h'f8050046 initialized retained ? * 3 retained pecrh1 h'f8050048 initialized retained ? * 3 retained pecrh2 h'f805004a initialized retained ? * 3 retained pecrl1 h'f805004c initialized retained ? * 3 retained pecrl2 h'f805004e initialized retained ? * 3 retained intc iprc h'f8080000 initialized retained ? * 3 retained iprd h'f8080002 initialized retained ? * 3 retained ipre h'f8080004 initialized retained ? * 3 retained iprf h'f8080006 initialized retained ? * 3 retained iprg h'f8080008 initialized retained ? * 3 retained dmac dmars0 h'f8090000 initialized retained retained retained dmars1 h'f8090004 initialized retained retained retained stbcr3 h'f80a0000 initialized retained ? * 3 retained power-down mode stbcr4 h'f80a0004 initialized retained ? * 3 retained cpg mclkcr h'f80a000c initialized retained ? * 3 retained h-udi sdir h'f8100200 initialized retained retained retained sdid h'f8100214 initialized retained retained retained intc icr0 h'f8140000 initialized * 1 retained ? * 3 retained irqcr h'f8140002 initialized retained ? * 3 retained irqsr h'f8140004 initialized * 1 retained ? * 3 retained ipra h'f8140006 initialized retained ? * 3 retained iprb h'f8140008 initialized retained ? * 3 retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 708 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep cpg frqcr h'f815ff80 initialized * 2 retained ? * 3 retained power-down mode stbcr h'f815ff82 initialized retained ? * 3 retained wdt wtcnt h'f815ff84 initialized * 2 retained ? * 3 retained wtcsr h'f815ff86 initialized * 2 retained ? * 3 retained power-down mode stbcr2 h'f815ff88 initialized retained ? * 3 retained scif_0 scsmr_0 h'f8400000 initialized retained retained retained scbrr_0 h'f8400004 initialized retained retained retained scscr_0 h'f8400008 initialized retained retained retained scftdr_0 h'f840000c undefined retained retained retained scfsr_0 h'f8400010 initialized retained retained retained scfrdr_0 h'f8400014 undefined retained retained retained scfcr_0 h'f8400018 initialized retained retained retained scfdr_0 h'f840001c initialized retained retained retained scsptr_0 h'f8400020 initialized * 1 retained retained retained sclsr_0 h'f8400024 initialized retained retained retained scif_1 scsmr_1 h'f8410000 initialized retained retained retained scbrr_1 h'f8410004 initialized retained retained retained scscr_1 h'f8410008 initialized retained retained retained scftdr_1 h'f841000c undefined retained retained retained scfsr_1 h'f8410010 initialized retained retained retained scfrdr_1 h'f8410014 undefined retained retained retained scfcr_1 h'f8410018 initialized retained retained retained scfdr_1 h'f841001c initialized retained retained retained scsptr_1 h'f8410020 initialized * 1 retained retained retained sclsr_1 h'f8410024 initialized retained retained retained scif_2 scsmr_2 h'f8420000 initialized retained retained retained scbrr_2 h'f8420004 initialized retained retained retained scscr_2 h'f8420008 initialized retained retained retained scftdr_2 h'f842000c undefined retained retained retained scfsr_2 h'f8420010 initialized retained retained retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 709 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep scif_2 scfrdr_2 h'f8420014 undefined retained retained retained scfcr_2 h'f8420018 initialized retained retained retained scfdr_2 h'f842001c initialized retained retained retained scsptr_2 h'f8420020 initialized * 1 retained retained retained sclsr_2 h'f8420024 initialized retained retained retained siof simdr h'f8480000 initialized retained retained retained siscr h'f8480002 initialized retained retained retained sitdar h'f8480004 initialized retained retained retained sirdar h'f8480006 initialized retained retained retained sicdar h'f8480008 initialized retained retained retained sictr h'f848000c initialized retained retained retained sifctr h'f8480010 initialized retained retained retained sistr h'f8480014 initialized retained retained retained siier h'f8480016 initialized retained retained retained sitdr h'f8480020 initialized retained retained retained sirdr h'f8480024 initialized retained retained retained sitcr h'f8480028 initialized retained retained retained sircr h'f848002c initialized retained retained retained spicr h'f8480030 initialized retained retained retained phy-if phyifcr h'f8490000 initia lized initialized retained retained phyifsmir2 h'f8490004 initialized initialized retained retained phyifsmir3 h'f8490008 initialized initialized retained retained phyifaddrr h'f849000c initialized initialized retained retained phyifsr h'f8490010 initialized * 4 initialized retained retained cmt cmstr h'f84a0070 initialized initialized retained retained cmcsr_0 h'f84a0072 initialized initialized retained retained cmcnt_0 h'f84a0074 initialized initialized retained retained cmcor_0 h'f84a0076 initialized initialized retained retained cmcsr_1 h'f84a0078 initialized initialized retained retained cmcnt_1 h'f84a007a initialized initialized retained retained cmcor_1 h'f84a007c initializ ed initialized retained retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 710 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep hif hifidx h'f84d0000 initialized retained retained retained hifgsr h'f84d0004 initialized retained retained retained hifscr h'f84d0008 initialized * 1 retained retained retained hifmcr h'f84d000c initialized retained retained retained hifiicr h'f84d0010 initialized retained retained retained hifeicr h'f84d0014 initialized retained retained retained hifadr h'f84d0018 initialized retained retained retained hifdata h'f84d001c initialized retained retained retained hifdtr h'f84d0020 initialized retained retained retained hifbicr h'f84d0024 initialized retained retained retained hifbcr h'f84d0040 initialized * 1 retained retained retained bsc cmncr h'f8fd0000 initialized * 1 retained ? * 3 retained cs0bcr h'f8fd0004 initialized retained ? * 3 retained cs3bcr h'f8fd000c initialized retained ? * 3 retained cs4bcr h'f8fd0010 initialized retained ? * 3 retained cs5bbcr h'f8fd0018 initialized retained ? * 3 retained cs6bbcr h'f8fd0020 initialized retained ? * 3 retained cs0wcr h'f8fd0024 initialized retained ? * 3 retained cs3wcr h'f8fd002c initialized retained ? * 3 retained cs3wcr (sdram in use) h'f8fd002c initialized retained ? * 3 retained cs4wcr h'f8fd0030 initialized retained ? * 3 retained cs5bwcr h'f8fd0038 initialized retained ? * 3 retained cs5bwcr (pcmcia in use) h'f8fd0038 initialized retained ? * 3 retained cs6bwcr h'f8fd0040 initialized retained ? * 3 retained cs6bwcr (pcmcia in use) h'f8fd0040 initialized retained ? * 3 retained sdcr h'f8fd0044 initialized retained ? * 3 retained rtcsr h'f8fd0048 initialized retained ? * 3 retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 711 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep e-dmac rtcnt h'f8fd004c initialized retained ? * 3 retained rtcor h'f8fd0050 initialized retained ? * 3 retained edmr h'fb000000 initialized retained retained retained edtrr h'fb000004 initialized retained retained retained edrrr h'fb000008 initialized retained retained retained tdlar h'fb00000c initialized retained retained retained rdlar h'fb000010 initialized retained retained retained eesr h'fb000014 initialized retained retained retained eesipr h'fb000018 initialized retained retained retained trscer h'fb00001c initialized retained retained retained rmfcr h'fb000020 initialized retained retained retained tftr h'fb000024 initialized retained retained retained fdr h'fb000028 initialized retained retained retained rmcr h'fb00002c initialized retained retained retained edocr h'fb000030 initialized retained retained retained fcftr h'fb000034 initialized retained retained retained trimd h'fb00003c initialized retained retained retained rbwar h'fb000040 initialized retained retained retained rdfar h'fb000044 initialized retained retained retained tbrar h'fb00004c initialized retained retained retained tdfar h'fb000050 initialized retained retained retained etherc ecmr h'fb000160 initialized retained retained retained ecsr h'fb000164 initialized retained retained retained ecsipr h'fb000168 initialized retained retained retained pir h'fb00016c initialized * 1 retained retained retained mahr h'fb000170 initialized retained retained retained malr h'fb000174 initialized retained retained retained rflr h'fb000178 initialized retained retained retained psr h'fb00017c initialized * 1 retained retained retained trocr h'fb000180 initialized retained retained retained cdcr h'fb000184 initialized retained retained retained section 24 list of registers rev. 5.00 mar. 15, 2007 page 712 of 794 rej09b0237-0500 module abbr. address power-on reset software standby module standby sleep etherc lccr h'fb000188 initialized retained retained retained cndcr h'fb00018c initialized retained retained retained cefcr h'fb000194 initialized retained retained retained frecr h'fb000198 initialized retained retained retained tsfrcr h'fb00019c initialized retained retained retained tlfrcr h'fb0001a0 initialized retained retained retained rfcr h'fb0001a4 initialized retained retained retained mafcr h'fb0001a8 initialized retained retained retained ipgr h'fb0001b4 initialized retained retained retained apr h'fb0001b8 initialized retained retained retained mpr h'fb0001bc initialized retained retained retained tpauser h'fb0001c4 initialized retained retained retained ubc bdrb h'ffffff90 initialized retained retained retained bdmrb h'ffffff94 initialized retained retained retained brcr h'ffffff98 initialized retained retained retained betr h'ffffff9c initialized retained retained retained barb h'ffffffa0 initialized retained retained retained bamrb h'ffffffa4 initialized retained retained retained bbrb h'ffffffa8 initialized retained retained retained brsr h'ffffffac initialized retained retained retained bara h'ffffffb0 initialized retained retained retained bamra h'ffffffb4 initialized retained retained retained bbra h'ffffffb8 initialized retained retained retained brdr h'ffffffbc initialized * 1 retained retained retained cache ccr1 h'ffffffec initialized retained retained retained notes: 1. some bits are not initialized. 2. not initialized by a power-on reset caused by the wdt. 3. this module does not ent er the module standby mode. 4. initialization by applying the phy power supply, not by a reset through power-on reset pin section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 713 of 794 rej09b0237-0500 section 25 electrical characteristics 25.1 absolute maximum ratings table 25.1 shows the absolute maximum ratings. table 25.1 absolute maximum ratings item symbol value unit power supply voltage (i/o) v cc q ?0.3 to +3.8 v power supply voltage (internal) v cc , v cc (pll1), v cc (pll2) ?0.3 to +2.1 v input voltage v in ?0.3 to v cc q + 0.3 v analog power supply (phy) v cc 1a v cc 2a v cc 3a ?0.3 to +3.8 v operating temperature t opr see the operating temperatures given in appendix b, product code lineup. c storage temperature t stg ?55 to +125 c caution: permanent damage to the lsi may resu lt if absolute maximum ratings are exceeded. section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 714 of 794 rej09b0237-0500 25.2 power-on and power-off order ? order of turning on 1.8-v system power (vcc, vcc (pll1), and vcc (pll2)) and 3.3-v system power (vccq, vcc1a, vcc2a, and vcc3a) ? first turn on the 3.3-v system power, then turn on the 1.8-v system power within 1 ms. this time should be as short as possible. the sy stem design must ensure that the states of pins or undefined period of an internal state do not cause erroneous system operation. ? until voltage is applied to all power supplies and a low level is input to the res pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. waveforms at power-on are shown in the following figure. vccq (min.) power vccna (min.) power * 2 vcc (min.) vcc/2 vccq: 3.3-v system power vccna: 3.3-v system power * 2 vcc: 1.8-v system power t pwu t unc gnd pin states undefined normal operation period input low level in advance power-on reset state pin states undefined res other pins * 1 notes: 1. except power/gnd and clock related pins 2. n = 1 to 3 table 25.2 recommended timing at power-on item symbol maximum value unit time difference between turning on vccq, vccna (n = 1 to 3), and vcc t pwu 1 ms time over which the internal state is undefined t unc 100 ms note: * the values shown in table 25.2 are recommended values, so they represent guidelines rather than strict requirements. section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 715 of 794 rej09b0237-0500 the time over which the internal state is undefined means th e time taken to reach vcc (min.). the pin states become settled when vccq and vccna (n = 1 to 3) reached the vccq (min.). the timing when a power-on reset ( res ) is normally accepted is afte r vcc reaches vcc (min.) and oscillation becomes stable (when using the on-chip oscillator). ensure that the time over which the internal state is undefined is less than or equal to 100 ms. ? power-off order ? in the reverse order of power-on, first turn off the 1.8-v system power, then turn off the 3.3-v system power within 10 ms. this time should be as short as possible. the system design must ensure that the states of pins or undefined period of an internal state do not cause erroneous system operation. ? pin states are undefined while only the 1.8- v system power is turn ed off. the system design must ensure that these undefined states do not cause erroneous system operation. vccna: 3.3-v system power * note: * n = 1 to 3 vccq: 3.3-v system power vcc : 1.8-v system power t pwd gnd operation stopped normal operation period vcc/2 table 25.3 recommended timing in power-off item symbol maximum value unit time difference between turn ing off vccq, vccna (n = 1 to 3), and vcc t pwd 10 ms note: * the table shown above is recommended values, so they represent guidelines rather than strict requirements. section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 716 of 794 rej09b0237-0500 25.3 dc characteristics tables 25.4 and 25.5 show the dc characteristics. table 25.4 dc characteristics (1) conditions: for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. typ. max. unit test conditions current consumption normal operation i cc ? 250 300 ma i cc q ? 60 100 ma v cc = 1.8 v v cc q = 3.3 v i = 125 mhz b = 62.5 mhz i stby (v cc ) ? 700 * ? standby mode i stby (v cc q, v cc na (n = 1 to 3)) ? 20 * ? a t a = 25 c v cc = 1.8 v v cc q = 3.3 v * : reference value sleep mode i sleep ? 70 150 ma v cc = 1.8 v v cc q = 3.3 v b = 62.5 mhz input leakage current all pins | i in | ? ? 1.0 a v in = 0.5 to v cc q ? 0.5 v tri-state leakage current i/o pins, all output pins (off state) | i sti | ? ? 1.0 a v in = 0.5 to v cc q ? 0.5 v rxp/m ? ? 30 input capacitance other than above c ? ? 10 pf section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 717 of 794 rej09b0237-0500 table 25.4 dc characteristics (2) conditions: for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. typ. max. unit test conditions v cc q 3.0 3.3 3.6 v v cc , v cc (pll1), v cc (pll2) 1.71 1.8 1.89 power supply v cc 1a v cc 2a v cc 3a 3.0 3.3 3.6 note: the voltage should be the same as v cc q. input high voltage res , nmi, irq7 to irq0, md5, md3 to md0, asemd , testmd , hifmd, trst v ih v cc q 0.9 ? v cc q + 0.3 v extal, ck_phy v cc q ? 0.3 ? v cc q + 0.3 other input pins 2.0 ? v cc q + 0.3 input low voltage res , nmi, irq7 to irq0, md5, md3 to md0, asemd , testmd , hifmd, trst v il ?0.3 ? v cc q 0.1 extal, ck_phy ?0.3 ? v cc q 0.2 other input pins ?0.3 ? v cc q 0.2 2.4 ? ? v v cc q = 3.0 v i oh = ?200 a output high voltage all output pins v oh 2.0 ? ? v cc q = 3.0 v i oh = ?2 ma output low voltage all output pins v ol ? ? 0.55 v v cc q = 3.6 v i ol = 2.0 ma notes: 1. the vcc and vss pins must be connected to the v cc and v ss . 2. current consumption values are for v ih min. = v cc q ? 0.5 v and v il max. = 0.5 v with all output pins unloaded. section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 718 of 794 rej09b0237-0500 table 25.5 permissible output currents conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. typ. max. unit permissible output low current (per pin) i ol ? ? 2.0 ma permissible output low current (total) i ol ? ? 120 ma permissible output high current (per pin) ?i oh ? ? 2.0 ma permissible output high current (total) ?i oh ? ? 40 ma caution: to protect the lsi's re liability, do not exceed the output current values in table 25.5. 25.4 ac characteristics signals input to this lsi are basically handled as signals synchronized with the clock. unless otherwise noted, setup and hold times for individual signals must be followed. table 25.6 maximum operating frequency conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. typ. max. unit test conditions cpu, cache (i ) f 20 ? 125 mhz external bus (b ) 20 ? 62.5 operating frequency on-chip peripheral module (p ) 5 ? 31.25 section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 719 of 794 rej09b0237-0500 25.4.1 clock timing table 25.7 clock timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup; external bus operating frequency (max.) = 62.5 mhz item symbol min. max. unit. reference figures extal clock input frequency f ex 10 25 mhz figure 25.1 extal clock input cycle time t excyc 40 100 ns extal clock input low pulse width t exl 10 ? ns extal clock input high pulse width t exh 10 ? ns extal clock rising time t exr ? 4 ns extal clock falling time t exf ? 4 ns ckio clock output frequency f op 20 62.5 mhz figure 25.2 ckio clock output cycle time t cyc 16 50 ns ckio clock low pulse width t ckol 3.5 ? ns ckio clock high pulse width t ckoh 3.5 ? ns ckio clock rising time t ckor ? 4.5 ns ckio clock falling time t ckof ? 4.5 ns ck_phy clock input frequency f ckphy 25 ? 100 ppm 25 + 100 ppm mhz ck_phy clock input cycle time t ckphycyc 39.996 40.004 ns ck_phy clock input low pulse width t ckphyl 12 ? ns ck_phy clock input high pulse width t ckphyh 12 ? ns ck_phy clock input rising time t ckphyr ? 6 ns ck_phy clock input falling time t ckphyf ? 6 ns oscillation settling time (power- on) t osc1 10 ? ms figure 25.3 res setup time t ress 25 ? ns res assert time t resw 20 ? t bcyc * figures 25.3 and 25.4 section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 720 of 794 rej09b0237-0500 item symbol min. max. unit. reference figures oscillation settling time 1 (leaving standby mode) t osc2 10 ? ms figure 25.4 oscillation settling time 2 (leaving standby mode) t osc3 ? 10 ms figure 25.5 pll synchronize settling time t pll ? 100 s figure 25.6 note: * t bcyc indicates the period of the external bus clock (b ). t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v cc 1/2 v cc v il v il note: * when the clock is input to the extal pin extal * (input) figure 25.1 external clock input timing t cyc t ckol t ckoh v oh 1/2 v cc 1/2 v cc t ckor t ckof v oh v ol v ol v oh ckio (output) t ckphycyc t ckphyl t ckphyh v oh 1/2 v cc 1/2 v cc t ckphyr t ckphyf v oh v ol v ol v oh ck_phy figure 25.2 ckio clock output ti ming and ck_phy clock input timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 721 of 794 rej09b0237-0500 v cc min. t resw t ress t osc1 v cc res ckio, internal clock oscillation settled note: oscillation settling time when the internal oscillator is in use figure 25.3 oscillation settling timing after power-on t osc2 t resw res ckio, internal clock oscillation settled note: oscillation settling time when the internal oscillator is in use standby mode figure 25.4 oscillation settling timing after standby mode (by reset) t osc3 nmi ckio, internal clock oscillation settled note: oscillation settling time when the internal oscillator is in use standby mode figure 25.5 oscillation settling timing after standby mode (by nmi or irq) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 722 of 794 rej09b0237-0500 t pll pll output, ckio output input clock settled note: pll oscillation settling time when the clock is input to the extal pin extal input reset or nmi interrupt request pll synchronization internal clock pll synchronization input clock settled standby mode figure 25.6 pll synchronize se ttling timing by reset or nmi section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 723 of 794 rej09b0237-0500 25.4.2 control signal timing table 25.8 control signal timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures res pulse width t resw 20 * 2 ? t bcyc * 3 res setup time * 1 t ress 25 ? ns figures 25.7 and 25.8 res hold time t resh 15 ? ns nmi setup time * 1 t nmis 12 ? ns figure 25.8 nmi hold time t nmih 10 ? ns irq7 to irq0 setup time * 1 t irqs 12 ? ns irq7 to irq0 hold time t irqh 10 ? ns bus tri-state delay time 1 t boff1 ? 20 ns figure 25.9 bus tri-state delay time 2 t boff2 ? 20 ns bus buffer on time 1 t bon1 ? 20 ns bus buffer on time 2 t bon2 ? 20 ns notes: 1. the res , nmi, and irq7 to irq0 signals are a synchronous signals. when the setup time is satisfied, a signal change is detect ed at the rising edge of the clock signal. when the setup time is not satisfied, a signal change may be delayed to the next rising edge. 2. in standby mode, t resw = t osc2 (10 ms). when changing the clock multiplication, t resw = t pll1 (100 s). 3. t bcyc indicates the period of the external bus clock (b ). ckio t ress t ress res t resw figure 25.7 reset input timing section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 724 of 794 rej09b0237-0500 ckio res t resh t ress v ih v il nmi t nmih t nmis v ih v il irq7 to irq0 t irqh t irqs v ih v il figure 25.8 int errupt input timing ckio t boff2 t boff1 t bon2 t bon1 a25 to a0, d15 to d0 r d , rd/ wr , ras , cas , csn , wen , bs , cke normal mode standby mode normal mode figure 25.9 pin drive timing in standby mode section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 725 of 794 rej09b0237-0500 25.4.3 ac bus timing table 25.9 bus timing conditions: clock mode = 1/2/5/6, v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures address delay time 1 t ad1 1 14 ns figures 25.10 to 25.36 address setup time t as 3 ? ns figures 25.10 to 25.13 address hold time t ah 3 ? ns figures 25.10 to 25.13 bs delay time t bsd ? 14 ns figures 25.10 to 25.29 and 25.33 to 25.36 cs delay time 1 t csd1 1 14 ns figures 25.10 to 25.36 read write delay time t rwd1 1 14 ns figures 25.10 to 25.36 read strobe time t rsd 1/2 t bcyc 1/2 t bcyc + 13 ns figures 25.10 to 25.15, 25.33, and 25.34 read data setup time 1 t rds1 1/2 t bcyc + 10 ? ns figures 25.10 to 25.15 and 25.33 to 25.36 read data setup time 2 t rds2 10 ? ns figures 25.16 to 25.19, figures 25.24 to 25.26 read data hold time 1 t rdh1 0 ? ns figures 25.10 to 25.15 and 25.33 to 25.36 read data hold time 2 t rdh2 2 ? ns figures 25.16 to 25.19 and 25.24 to 25.26 write enable delay time 1 t wed1 1/2 t bcyc 1/2 t bcyc + 10 ns figures 25.10 to 25.14, 25.33, and 25.34 write enable delay time 2 t wed2 ? 13 ns figure 25.15 write data delay time 1 t wdd1 ? 18 ns figures 25.10 to 25.15 and 25.33 to 25.36 write data delay time 2 t wdd2 ? 14 ns figures 25.20 to 25.23 and 25.27 to 25.29 write data hold time 1 t wdh1 2 ? ns figures 25.10 to 25.15 and 25.33 to 25.36 section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 726 of 794 rej09b0237-0500 item symbol min. max. unit reference figures write data hold time 2 t wdh2 2 ? ns figures 25.20 to 25.23 and 25.27 to 25.29 write data hold time 3 t wdh3 0 ? ns figures 25.10 to 25.13 wait setup time t wts1 1/2 t bcyc + 11 ? ns figures 25.12 to 25.15, 25.34, and 25.36 wait hold time t wth1 1/2 t bcyc + 10 ? ns figures 25.12 to 25.15, 25.34, and 25.36 ras delay time t rasd1 1 14 ns figures 25.16 to 25.27 and 25.29 to 25.32 cas delay time t casd1 1 14 ns figures 25.16 to 25.32 dqm delay time t dqmd1 1 14 ns figures 25.16 to 25.29 cke delay time t cked1 ? 14 ns figure 25.31 iciord delay time t icrsd 1/2 t bcyc 1/2 t bcyc + 15 ns figures 25.35 and 25.36 iciowr delay time t icwsd 1/2 t bcyc 1/2 t bcyc + 15 ns figures 25.35 and 25.36 iois16 setup time t io16s 1/2 t bcyc + 11 ? ns figure 25.36 iois16 hold time t io16h 1/2 t bcyc + 10 ? ns figure 25.36 section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 727 of 794 rej09b0237-0500 25.4.4 basic timing t1 t ad1 t as t csd1 t2 t ad1 t rwd1 t rwd1 t csd1 t rsd t rsd t ah t rdh1 t rds1 t wed1 t wed1 t ah t bsd t bsd t dacd t dacd t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen bs dackn * d31 to d0 t wdh3 t wdh1 read write note : * dackn is the waveform when active low is selected. figure 25.10 basic bus timing: no wait cycle section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 728 of 794 rej09b0237-0500 t1 t ad1 t as t csd1 tw t2 t ad1 t rwd1 t rwd1 t csd1 t rsd t rsd t ah t rdh1 t rds1 t wed1 t wed1 t ah t bsd t bsd t wth1 t wts1 t dacd t dacd t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 read wen bs wait dackn * d31 to d0 write t wdh1 t wdh3 note : * dackn is the waveform when active low is selected. figure 25.11 basic bus timi ng: one software wait cycle section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 729 of 794 rej09b0237-0500 t1 t ad1 t as t csd1 tw x t2 t ad1 t rwd1 t rwd1 t csd1 t rsd t rsd t ah t rdh1 t rds1 t wed1 t wed1 t ah t bsd t bsd t wth1 t wts1 t wth1 t wts1 t dacd t dacd t wdd1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen bs wait dackn * d31 to d0 t wdh1 t wdh3 read write note : * dackn is the waveform when active low is selected. figure 25.12 basic bus timi ng: one external wait cycle section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 730 of 794 rej09b0237-0500 t ad1 t ad1 t1 t rwd1 t rsd t wed1 t wed1 t wed1 t rds1 t rds1 t rdh1 t rdh1 t as t rsd t rsd t ah t rsd t ah t wed1 t ah t ah t csd1 t wdd1 t wdh1 t wdh1 t wdd1 t bsd t bsd t dacd t dacd t dacd t dacd t bsd t bsd t rwd1 t rwd1 t rwd1 t csd1 t csd1 t csd1 t as t ad1 t ad1 tw t 2 ta w t 1 tw t 2 taw dackn * a25 to a0 d15 to d0 csn rd/ wr rd wait d15 to d0 we n bs ckio t wth1 t wts1 t wth1 t wts1 read write t wdh3 t wdh3 note : * dackn is the waveform when active low is selected. figure 25.13 basic bus timing : one software wait cycle, external wait enabled (wm bit = 0), no idle cycle section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 731 of 794 rej09b0237-0500 th t ad1 t rsd t rsd t rds1 t csd1 t rwd1 t1 twx t2 tf t wdd1 t bsd t wdh1 t rdh1 t ad1 t csd1 ckio a25 to a0 csn wen rd d31 to d0 d31 to d0 read rd/ wr rd/ wr bs wait dackn * tendn write t dacd t dacd t bsd t wts1 t wts1 t rwd1 t rwd1 t rwd1 t wed1 t wed1 t wth1 t wth1 note : * dackn and tendn are the waveforms when active low is selected. figure 25.14 byte contro l sram timing: sw = 1 cycle, hw = 1 cycle, one asynchronous external wait cycle, csnwcr.bas = 0 (ub-/ lb-controlled write cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 732 of 794 rej09b0237-0500 th t ad1 t rsd t rsd t rds1 t csd1 t1 twx t2 tf t rwd1 t wdd1 t bsd t rwd1 t rwd1 t wdh1 t rdh1 t ad1 t csd1 ckio a25 to a0 csn wen rd d31 to d0 d31 to d0 read rd/ wr rd/ wr bs wait dackn * tendn write t dacd t dacd t bsd t wts1 t wts1 t wed2 t wed2 t rwd1 t wth1 t wth1 note : * dackn and tendn are the waveforms when active low is selected. figure 25.15 byte contro l sram timing: sw = 1 cycle, hw = 1 cycle, one asynchronous external wait cycle, csnw cr.bas = 1 (we-controlled write cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 733 of 794 rej09b0237-0500 25.4.5 synchronous dram timing tc1 tr tcw td1 tde t ad1 t ad1 t csd1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio a25 to a0 csn rd/ wr a11 * 1 d15 to d0 t rasd t rasd ras row address read a command column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t dacd t dacd dackn * 2 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.16 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 0 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 734 of 794 rej09b0237-0500 tr w tr tc1 tcw td1 tde tap t ad1 t ad1 t csd1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address read a command column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.17 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 1 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 735 of 794 rej09b0237-0500 tc1 tc2 td1 td2 td3 td4 tr tc3 tc4 tde t ad1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address read a command read command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t rdh2 t rds2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.18 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 1 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 736 of 794 rej09b0237-0500 tc1 tc2 td1 td2 td3 td4 tr trw tc3 tc4 tde t ad1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 t ad1 t ad1 t rdh2 t rds2 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address read a command read command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t rdh2 t rds2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.19 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 0 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 737 of 794 rej09b0237-0500 tr w l tr tc1 t ad1 t csd1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address write a command column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.20 synchronous d ram single write bus cycle (auto-precharge, trwl = 1 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 738 of 794 rej09b0237-0500 tr w t c 1 tr w l tr tr w t ad1 t csd1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address write a command column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t dacd t dacd dakcn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.21 synchronous d ram single write bus cycle (auto-precharge, wtrcd = 2 cycles, trwl = 1 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 739 of 794 rej09b0237-0500 tc2 tc3 tc4 trwl tr tc1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address write a command write command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.22 synchronous dram bu rst write bus cycle (single write 4) (auto-precharge, wtrcd = 0 cycle, trwl = 1 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 740 of 794 rej09b0237-0500 tc2 tc3 tc4 trwl tr tc1 tr w t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address write a command write command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.23 synchronous dram bu rst write bus cycle (single write 4) (auto-precharge, wtrcd = 1 cycle, trwl = 1 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 741 of 794 rej09b0237-0500 tc3 tc4 tde tr tc2 td1 td2 td3 td4 tc1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address read command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t rdh2 t rds2 t rdh2 t rds2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.24 synchronous dram burst read bus cycle (single read 4) (bank active mode: act + read commands , cas latency = 2, wtrcd = 0 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 742 of 794 rej09b0237-0500 tc2 tc4 tde tc1 tc3 td1 td2 td3 td4 t csd1 t ad1 t ad1 t ad1 t rwd t rwd t csd1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd ras read command column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t rdh2 t rds2 t rdh2 t rds2 t ad1 column address t ad1 column address t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.25 synchronous dram burst read bus cycle (single read 4) (bank active mode: read command, same row address, cas latency = 2, wtrcd = 0 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 743 of 794 rej09b0237-0500 tc3 tc4 tde tc2 td1 td2 td3 td4 tc1 tr tpw tp t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd t rasd t rasd ras read command column address column address column address column address row address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t rdh2 t rds2 t rdh2 t rds2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.26 synchronous dram burst read bus cycle (single read 4) (bank active mode: pre + act + read commands, different row addresses, cas latency = 2, wtrcd = 0 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 744 of 794 rej09b0237-0500 tc2 tc3 tc4 tr tc1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 t rasd t rasd ras row address write command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.27 synchronous dram bu rst write bus cycle (single write 4) (bank active mode: act + write commands, wtrcd = 0 cycle, trwl = 0 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 745 of 794 rej09b0237-0500 tc2 tc3 tc4 tnop tc1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 ras write command column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.28 synchronous dram bu rst write bus cycle (single write 4) (bank active mode: write command, same row address, wtrcd = 0 cycle, trwl = 0 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 746 of 794 rej09b0237-0500 tc2 tc3 tc4 tr tpw tp tc1 t ad1 t csd1 t ad1 t ad1 t ad1 t rwd t rwd t rwd t rwd t csd1 t rasd t rasd t rasd t rasd t ad1 t ad1 t ad1 t ad1 ckio csn rd/ wr a11 * 1 ras write command row address t ad1 t ad1 column address column address column address column address t casd t casd cas t bsd t bsd (high) bs cke t dqmd t dqmd dqmxx t wdh2 t wdd2 t wdh2 t wdd2 t dacd t dacd dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.29 synchronous dram bu rst write bus cycle (single write 4) (bank active mode: pre + act + write commands, different row addresses, wtrcd = 0 cycle, trwl = 0 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 747 of 794 rej09b0237-0500 tr c tr c tr r tpw tp trc t csd1 t ad1 t ad1 t rwd t rwd t rwd t csd1 t csd1 t csd1 t rasd t rasd t rasd t rasd t ad1 t ad1 ckio csn rd/ wr a11 * 1 ras t casd t casd cas (high) (weak keeper retained) bs cke dqmxx dackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.30 synchronous d ram auto-refreshing timing (wtrp = 1 cycle, wtrc = 3 cycles) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 748 of 794 rej09b0237-0500 trc trc trc tr r tpw tp trc t csd1 t ad1 t ad1 t rwd t rwd t rwd1 t csd1 t csd1 t csd1 t rasd t rasd t rasd t rasd t ad1 t ad1 ckio csn rd/ wr a11 * 1 ras t casd t casd cas (weak keeper retained) bs cke dqmxx t cked t cked d ackn * 2 a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.31 synchronous dram self -refreshing timing (wtrp = 1 cycle) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 749 of 794 rej09b0237-0500 trc trc trc tmw tde tr r tr r tpw tp trc t csd1 t ad1 t ad1 t ad1 pall ref ref mrs t rwd t rwd t rwd t csd1 t csd1 t csd1 t rasd t rasd t rasd t rasd t ad1 t ad1 ckio csn rd/ wr a11 * 1 ras t casd t casd cas (weak keeper retained) bs cke dqmxx dackn * 2 t csd1 t csd1 t rasd t rasd t casd t casd t csd1 t csd1 t rwd t rwd t rasd t rasd t casd t casd a25 to a0 d15 to d0 notes: * 1. address pins connected to a10 in sdram 2. dackn is the waveform when active low is selected. figure 25.32 synchronous dram mode register write timing (wtrp = 1 cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 750 of 794 rej09b0237-0500 25.4.6 pcmcia timing read write d15 to d0 d15 to d0 a25 to a0 ckio cexx rd/ wr rd we bs t rwd1 t rwd1 t wdd1 t wdh1 t bsd t bsd t rsd t wed t wed t wdh5 t rsd t rdh1 t rds1 tpcm1w tpcm2 tpcm1 tpcm1w tpcm1w t ad1 t csd1 figure 25.33 pcmcia memory card interface bus timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 751 of 794 rej09b0237-0500 read write d15 to d0 d15 to d0 a25 to a0 ckio cexx rd/ wr rd we bs wait t wts t ad1 t csd1 t rwd1 t ad1 t csd1 t rwd1 t bsd t bsd t wdh1 t wdd1 t wed t wed t wdh5 t rsd t rsd t rdh1 t rds1 t wth t wth t wts tpcm1w tpcm2 tpcm0 tpcm1 tpcm1w tpcm0w tpcm2w tpcm1w tpcm1w figure 25.34 pcmcia memory card interface bus timing (ted = 2.5 cycles, teh = 1.5 cycles, one software wa it cycle, one external wait cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 752 of 794 rej09b0237-0500 read write d15 to d0 d15 to d0 a25 to a0 ckio cexx rd/ wr iciord iciowr bs t ad1 t csd1 t rwd1 t ad1 t csd1 t rwd1 t bsd t bsd t wdh1 t wdd1 t icwsd t icwsd t wdh5 t icrsd t icrsd t rdh1 t rds1 tpci1w tpci2 tpci1 tpci1w tpci1w figure 25.35 pcmcia i/o card interface bus timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 753 of 794 rej09b0237-0500 read write d15 to d0 d15 to d0 a25 to a0 ckio cexx rd/ wr iciord iciowr bs t ad1 t csd1 t rwd1 t ad1 t csd1 t rwd1 t bsd t io16s t io16h t bsd t wdh1 t wdd1 t icwsd t icwsd t wdh5 t icrsd t icrsd t rdh1 t rds1 t wth t wth t wts t wts tpci1w tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w iois16 wait figure 25.36 pcmcia i/o card interface bus timing (ted = 2.5 cycles, teh = 1.5 cycles, one software wa it cycle, one external wait cycle) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 754 of 794 rej09b0237-0500 25.4.7 dmac signal timing table 25.10 dmac signal timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures dreqn set-up time t drqs 10 ? ns figure 25.37 dreqn hold time t drqh 10 ? ns figure 25.37 tendn, dackn delay time t dacd ? 10 ns figure 25.38 t drqs t drqh ckio dreqn figure 25.37 dreq input timing ckio tendn dackn t dacd t dacd figure 25.38 tendn, dackn output timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 755 of 794 rej09b0237-0500 25.4.8 scif timing table 25.11 scif timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures clock synchronous 12 ? input clock cycle asynchronous t scyc 4 ? t pcyc figures 25.39 and 25.40 input clock rising time t sckr ? 0.8 t pcyc figure 25.39 input clock falling time t sckf ? 0.8 t pcyc input clock pulse width t sckw 0.4 0.6 t scyc transmit data delay time t txd ? 3 t pcyc * + 50 ns figure 25.40 receive data setup time (clocked synchronous) t rxs 3 ? t pcyc receive data hold time (clocked synchronous) t rxh 3 ? t pcyc rts delay time t rtsd ? 100 ns cts setup time (clocked synchronous) t ctss 100 ? ns cts hold time (clocked synchronous) t ctsh 100 ? ns note: * t pcyc indicates the period of the peripheral module clock (p ). t sckw t sckr t sckf t scyc sck figure 25.39 sck input clock timing section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 756 of 794 rej09b0237-0500 t scyc t txd sck txd (data transmission) rxd (data reception) t rxh t rxs t rtsd rts cts t ctsh t ctss figure 25.40 sci input/output timing in clocked synchronous mode 25.4.9 siof modul e signal timing table 25.12 scif timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures siomclk clock input cycle time t mcyc 32 ? ns figure 25.41 siomclk input high pulse width t mwh 0.4 t mcyc ? siomclk input low pulse width t mwl 0.4 t mcyc ? sck_sio clock cycle time t sicyc 2 t pcyc * ? figures 25.42 to 25.46 sck_sio output high pulse width t swho 0.4 t sicyc ? sck_sio output low pulse width t swlo 0.4 t sicyc ? figures 25.42 to 25.45 siofsync output delay time t fsd ? 20 sck_sio input high pulse width t swhi 0.4 t sicyc ? figure 25.46 sck_sio input low pulse width t swli 0.4 t sicyc ? siofsync input set-up time t fss 20 ? siofsync input hold time t fsh 20 ? section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 757 of 794 rej09b0237-0500 item symbol min. max. unit reference figures txd_sio output delay time t stdd ? 20 rxd_sio input set-up time t srds 20 ? figures 25.42 to 25.46 rxd_sio input hold time t srdh 20 ? note: * t pcyc indicates the period of the peripheral module clock (p ). t mwh t mwl t mcyc siomclk figure 25.41 siomclk input timing t sicyc t swlo t swho t fsd t stdd t stdd t srds t srdh t fsd sck_sio (output) siofsync (output) txd_sio rxd_sio figure 25.42 siof tr ansmit/receive timing (master mode 1/falling edge sampling) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 758 of 794 rej09b0237-0500 sck_sio (output) siofsync (output) txd_sio rxd_sio t sicyc t swlo t swho t fsd t stdd t stdd t srds t srdh t fsd figure 25.43 siof tr ansmit/receive timing (master mode 1/risi ng edge sampling) sck_sio (output) siofsync (output) txd_sio rxd_sio t sicyc t swlo t swho t fsd t stdd t stdd t stdd t srds t stdd t srdh t fsd figure 25.44 siof tr ansmit/receive timing (master mode 2/falling edge sampling) section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 759 of 794 rej09b0237-0500 sck_sio (output) t sicyc t swlo t swho t fsd t stdd t stdd t stdd t srds t stdd t srdh t fsd siofsync (output) txd_sio rxd_sio figure 25.45 siof tr ansmit/receive timing (master mode 2/risi ng edge sampling) t stdd t srds t srdh sck_sio (input) t sicyc t swli t swhi t stdd t fsh t fss siofsync (input) txd_sio rxd_sio figure 25.46 siof tr ansmit/receive timing (slave mode 1/ slave mode 2) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 760 of 794 rej09b0237-0500 25.4.10 port timing table 25.13 port timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures output data delay time t portd ? 20 ns figure 25.47 input data setup time t ports 16 ? ns input data hold time t porth 10 ? ns t ports ckio t porth t portd ports a to e (read) ports a to e (write) figure 25.47 i/o port timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 761 of 794 rej09b0237-0500 25.4.11 hif timing table 25.14 hif timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures read bus cycle time t hifcycr 4 ? t pcyc figure 25.48 write bus cycle time t hifcycw 4 ? t pcyc address setup time (hifscr.dmd = 0) t hifas 16 ? ns address setup time (hifscr.dmd = 1) t hifas 0 ? ns address hold time (hifscr.dmd = 0) t hifah 16 ? ns address hold time (hifscr.dmd = 1) t hifah 0 ? ns read low width (read) t hifwrl 2.5 ? t pcyc write low width (write) t hifwwl 2.5 ? t pcyc read/write high width t hifwrwh 2.0 ? t pcyc read data delay time t hifrdd ? 2 t pcyc + 16 ns read data hold time t hifrdh 0 ? ns write data setup time t hifwds t pcyc + 10 ? ns write data hold time t hifwdh 10 ? ns hifint output delay time t hifitd ? 20 ns figure 25.49 hifrdy output delay time t hifryd ? 10 t pcyc figure 25.50 hifdreq output delay time t hifdqd ? 20 ns figure 25.49 hif pin enable delay time t hifebd ? 20 ns figure 25.50 hif pin disable delay time t hifdbd ? 20 ns notes: 1. t pcyc indicates the period of the peripheral module clock (p ). 2. t hifas is given from the start of the time over which both the hifcs and hifrd (or hifwr ) signals are low levels. 3. t hifah is given from the end of the time over which both the hifcs and hifrd (or hifwr ) signals are low levels. 4. t hifwrl is given as the time over which both the hifcs and hifrd signals are low levels. 5. t hifwwl is given as the time over which both the hifcs and hifwr signals are low levels. 6. when reading the register specified by bits reg5 to reg0 after writing to the hif index register (hifidx), t hifwrwh (min.) = 2 t pcyc + 5 ns. section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 762 of 794 rej09b0237-0500 hifrs hifcs hifrd hifwr hifd15 to hifd00 t hifwrl t hifcycr t hifcycw t hifwwl t hifwrwh t hifwds t hifrdh t hifrdd t hifas t hifas t hifah t hifah t hifwdh read data write data figure 25.48 hif access timing ckio hifint t hifdqd t hifitd hifdreq figure 25.49 hifint and hifdreq timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 763 of 794 rej09b0237-0500 t hifdbd t hifebd t hifryd t hifryd hifd15 to hifd0 hifebl hifrdy res hifint hifdreq hifrdy figure 25.50 hifrdy and hi f pin enable/disable timing section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 764 of 794 rej09b0237-0500 25.4.12 etherc timing table 25.15 etherc timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures tx-clk cycle time t tcyc 40 ? ns ? tx-en output delay time t tend 1 20 ns figure 25.51 mii_txd[3:0] output delay time t mtdd 1 20 ns crs setup time t crss 10 ? ns crs hold time t crsh 10 ? ns col setup time t cols 10 ? ns figure 25.52 col hold time t colh 10 ? ns rx-clk cycle time t rcyc 40 ? ns ? rx-dv setup time t rdvs 10 ? ns figure 25.53 rx-dv hold time t rdvh 10 ? ns mii_rxd[3:0] setup time t mrds 10 ? ns mii_rxd[3:0] hold time t mrdh 10 ? ns rx-er setup time t rers 10 ? ns figure 25.54 rx-er hold time t rerh 10 ? ns mdio setup time t mdios 10 ? ns figure 25.55 mdio hold time t mdioh 10 ? ns mdio output data hold time t mdiodh 5 18 ns figure 25.56 wol output delay time t wold 1 20 ns figure 25.57 exout output delay time t exoutd 1 20 ns figure 25.58 section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 765 of 794 rej09b0237-0500 t crss t crsh t tend t mtdd tx-clk tx-en mii_txd[3:0] tx-er crs col data sfd crc preamble figure 25.51 mii transmission timing (normal operation) t colh t cols tx-clk tx-en mii_txd[3:0] tx-er crs col jam preamble figure 25.52 mii transmissi on timing (collision occurred) section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 766 of 794 rej09b0237-0500 t rdvs t rdvh t mrdh t mrds rx-clk rx-en mii_rxd[3:0] rx-er data sfd crc preamble figure 25.53 mii reception timing (normal operation) t rers t rerh rx-clk rx-en mii_rxd[3:0] rx-er data sfd xxxx preamble figure 25.54 mii reception timing (error occurred) mdc mdio t mdios t mdioh figure 25.55 mdio input timing mdc mdio t mdiodh figure 25.56 mdio output timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 767 of 794 rej09b0237-0500 rx-clk wol t wold figure 25.57 wol output timing ckio exout t exoutd figure 25.58 exout output timing 25.4.13 h-udi related pin timing table 25.16 h-udi related pin timing conditions: v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. max. unit reference figures tck cycle time t tckcyc 50 ? ns figure 25.59 tck high pulse width t tckh 19 ? ns tck low pulse width t tckl 19 ? ns tck rising/falling time t tckrf ? 4 ns trst setup time t trsts 10 ? t bcyc * figure 25.60 trst hold time t trsth 50 ? t bcyc * tdi setup time t tdis 10 ? ns figure 25.61 tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ? 19 ns note: * t bcyc indicates the period of the external bus clock (b ). section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 768 of 794 rej09b0237-0500 t tckcyc v ih 1/2 v ccq 1/2 v ccq v ih v il v il v ih t tckl t tckrf t tckrf t tckh figure 25.59 tck input timing t trsts t trsth trst res figure 25.60 tck input timing in reset hold state tck tms tdi tdo t tdis t tdih t tckcyc t tmss t tmsh t tdod figure 25.61 h-udi data transmission timing section 25 electrical characteristics rev. 5.00 mar. 15, 2007 page 769 of 794 rej09b0237-0500 25.4.14 ac characteristic test conditions ? i/o signal reference level: v cc q/2 (v cc q = 3.0 v to 3.6 v, v cc = 1.71 v to 1.89 v) ? input pulse level: v ss to v cc q ( res , nmi, irq7 to irq0, md5, md3 to md0, asemd , testmd , hifmd , trst , and extal), v ss to 3.0 v (other pins) ? input rising and falling times: 1 ns i ol i oh c l v ref lsi output pin dut output notes: 1. c l is the total value that includes the capacitance of measurement instruments, etc., and is set for all pins as 30 pf. 2. i ol and i oh are shown in table 25.5. figure 25.62 output load circuit section 25 electric al characteristics rev. 5.00 mar. 15, 2007 page 770 of 794 rej09b0237-0500 25.5 physical layer ttransceiver (p hy) characteristics (reference values) table 25.17 shows the characteristics of the physical layer transceiver (phy) table 25.17 phy characteristics conditions: v cc 1a = v cc 2a = v cc 3a = 3.3 v; for ta, see the operating temperatures given in appendix b, product code lineup. item symbol min. typ. max. unit test conditions 100base-tx output high level v oh100 +0.95 ? +1.05 v ? 100base-tx output middle level v om100 -50 ? +50 mv ? 100base-tx output low level v ol100 -1.05 ? -0.95 v ? transformer secondary-side differential output voltage 10base-tx output high level v oh10 2.2 ? 2.8 v ? appendix rev. 5.00 mar. 15, 2007 page 771 of 794 rej09b0237-0500 appendix a. port states in each pin state table a.1 port states in each pin state reset state power-down mode classifi- cation abbr. power-on (hifmd = low) power-on (hifmd = high) software standby sleep h-udi module standby clock extal i i i i i xtal o * 1 o * 1 o * 1 o * 1 o * 1 ckio o * 1 o * 1 zo * 5 o * 1 o * 1 ck_phy i i i i i system control res i i i i i operating mode control md5, md3 to md0 i i i i i interrupt nmi i i i i i irq7 to irq0 ? ? i i i a25 to a16 ? ? zhl * 4 o o address bus a15 to a0 o o zhl * 4 o o d31 to d16 ? ? z io io data bus d15 to d0 z z z io io wait ? ? z i i iois16 ? ? z i i cke ? ? zo * 2 o o cas , ras ? ? zo * 2 o o we0 /dqmll h h zh * 4 o o we1 /dqmlu/ we h h zh * 4 o o bus control we2 /dqmul/ iciord ? ? zh * 4 o o appendix rev. 5.00 mar. 15, 2007 page 772 of 794 rej09b0237-0500 reset state power-down mode classifi- cation abbr. power-on (hifmd = low) power-on (hifmd = high) software standby sleep h-udi module standby we3 /dqmuu/ iciowr ? ? zh * 4 o o rd h h zh * 4 o o rdwr h h zh * 4 o o ce2b , ce2a ? ? zh * 4 o o cs6b / ce1b , cs5b / ce1a ? ? zh * 4 o o cs4 , cs3 ? ? zh * 4 o o cs0 h h zh * 4 o o bus control bs ? ? zh * 4 o o ethernet controller erxd3 to erxd0 ? ? i i i etxd3 to etxd0 ? ? o o o rx_dv ? ? i i i rx_er ? ? i i i rx_clk ? ? i i i tx_er ? ? o o o tx_en ? ? o o o tx_clk ? ? i i i col ? ? i i i crs ? ? i i i mdio ? ? io io io mdc ? ? o o o lnksta ? ? z i i exout ? ? z o o wol ? ? z o o appendix rev. 5.00 mar. 15, 2007 page 773 of 794 rej09b0237-0500 reset state power-down mode classifi- cation abbr. power-on (hifmd = low) power-on (hifmd = high) software standby sleep h-udi module standby dmac dreq1, dreq0 ? ? z i i dack1, dack0 ? ? z o o tend1, tend0 ? ? z o o scif txd2 to txd0 ? ? z o o rxd2 to rxd0 ? ? z i i sck2, sck1 ? ? z o o sck0 ? ? z i i rts1, rts0 ? ? z o o cts1, cts0 ? ? z i i siof siomclk0 ? ? z i i sck_sio0 ? ? z o o siofsync0 ? ? z o o txd_sio0 ? ? z o o rxd_sio0 ? ? z i i hifebl ? z z i i hifrdy ? o o o * 3 o * 3 hifdreq ? z z o * 3 o * 3 hifmd i i i i * 3 i * 3 hifint ? z z o * 3 o * 3 hifrd ? z z i * 3 i * 3 hifwr ? z z i * 3 i * 3 hifrs ? z z i * 3 i * 3 hifcs ? z z i * 3 i * 3 host interface hifd15 to hifd0 ? z z io * 3 io * 3 appendix rev. 5.00 mar. 15, 2007 page 774 of 794 rej09b0237-0500 reset state power-down mode classifi- cation abbr. power-on (hifmd = low) power-on (hifmd = high) software standby sleep h-udi module standby trst i i i i i tck i i i i i tms i i i i i tdi i i i i i tdo z z zo * 6 zo * 6 z user debugging interface (h-udi) asemd i i i i i i/o port pa25 to pa16 z z z p i/o pb13 to pb0 z z z p i/o pc20 to pc0 z z z p i/o pd7 to pd0 z z z p i/o pe24 to pe4, pe2 to pe0 z ? z p i/o pe3 ? ? z p i/o testmd i i i i i test mode testout o o o o o phy txp o o o o o txm o o o o o rxp i i i i i rxm i i i i i speed100 ? ? o o o link ? ? o o o crs ? ? o o o duplex ? ? o o o exres1 i i i i i tstbusa z z z z z [legend] ? : this pin function is not selected as an initial state. i: input o: output io: input/output h: high level output l: low level output appendix rev. 5.00 mar. 15, 2007 page 775 of 794 rej09b0237-0500 z: high-impedance p: input or output dependi ng on the register setting notes: 1. depends on the clock mode (setting of pins md2 to md0). 2. depends on the hizcnt bit in cmncr. 3. high-impedance when hifebl = low 4. depends on the hizmem bit in cmncr. 5. depends on the hizcnt bit in cmncr or the ckoen bit in frqcr. 6. this pin becomes output state only when reading data from the h-udi and retains high- impedance state when the pi n is not output state. appendix rev. 5.00 mar. 15, 2007 page 776 of 794 rej09b0237-0500 b. product code lineup product code ca talogue code operating temperature solder ball composition package code ds76190b125bgv r4s76190b125bgv ? 20 to 70c pb-free solder ds76190n125bgv r4s76190n125bgv ? 20 to 85c pb-free solder ds76190w125bgv r4s76190w125bgv ? 20 to 85c pb-free solder DS76190D125BGV r4s76190d125bgv ? 40 to 85c pb-free solder ds76190b125bg r4s76190b125bg ? 20 to 70c non-pb-free solder ds76190n125bg r4s76190n125bg ? 20 to 85c non-pb-free solder ds76190w125bg r4s76190w125bg ? 20 to 85c non-pb-free solder ds76190d125bg r4s76190d125bg ? 40 to 85c non-pb-free solder plbg0176ga-a appendix rev. 5.00 mar. 15, 2007 page 777 of 794 rej09b0237-0500 c. package dimensions jeita package code renesas code previous code mass[typ.] p-lfbga176-13x13-0.80 plbg0176ga-a bp-176/bp-176v 0.45g d e wsa ws b x4 v y 1 s y s s a 1 a a b 1 2 3 4 5 6 7 8 9 10 111213141 5 e e z e z d a b c d e f g h j k l m n p r xm s a b b dimension in millimeters min nom max reference symbol d e v w a a 1 e b x y y 1 s d s e z d z e 13.0 13.0 0.15 0.20 1.40 0.35 0.40 0.45 0.80 0.50 0.55 0.45 0.08 0.10 0.2 0.90 0.90 figure c.1 package dimensions (bp-176) appendix rev. 5.00 mar. 15, 2007 page 778 of 794 rej09b0237-0500 rev. 5.00 mar. 15, 2007 page 779 of 794 rej09b0237-0500 main revisions and add itions in this edition item page revision (see manual for details) amended mode input clock frequency range (p must be equal to or lower than 31.25 mhz) table 8.3 possible combination of clock modes and frqcr values 205 amended mode description 5 transmit fifo data empty indicates that data has been transferred from the transmit fifo data register (scftdr) to the tran smit shift register (sctsr), the quantity of data in scftdr has become less than the transmission trigger number specified by the ttrg1 and ttrg0 bits in the fifo control register (scfcr), and writing of transmit data to scftdr is enabled. 0: the quantity of transmit data written to scftdr is greater than the specified transmission trigger number [clearing conditions] ? tdfe is cleared to 0 when data exceeding the specified transmission trigger number is written to scftdr after 1 is read from tdfe and then 0 is written ? tdfe is cleared to 0 when dmac write data exceeding the specified transmission trigger number to scftdr 1: the quantity of transmit data in scftdr is equal to or less than the specified transmission trigger number * [setting conditions] ? tdfe is set to 1 by a power-on reset ? tdfe is set to 1 when the quantity of transmit data in scftdr has become equal to or less than the specified transmission trigger number as a result of transmission note: * since scftdr is a 16-byte fifo register, the maximum quantity of data that can be written when tdfe is 1 is "16 minus the specified transmission trigger number". if an attempt is made to write additional data, the data is ignored. the quantity of data in scftdr is indicated by the upper 8 bits of scfdr. 15.3.7 serial status register (scfsr) 389 rev. 5.00 mar. 15, 2007 page 780 of 794 rej09b0237-0500 item page revision (see manual for details) 15.4.3 synchronous operation clock 424 amended : when only receiving, the clock signal outputs while the re bit of scscr is 1 and the number of data in receive fifo is less than the receive fifo data trigger number. in this case, 8 (16 + 1) = 136 pulses of synchronous clock are output. to perform reception of n characters of data, select an external clock as the clock source. if an internal clock should be used, set re = 1 and te = 1 and receive n characters of data simultaneously with the transmission of n characters of dummy data. figure 15.13 sample flowchart for transmitting serial data 426 amended start of transmission read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr read tdfe and tend flags in scfsr while they are 1, then clear them to 0 no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr. read the tdfe and tend flags while they are 1, then clear them to 0. [2] serial transmission continuation procedeure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, them write data to [1] figure 15.18 sample flowchart for transmitting/receiving serial data 430 amended start of transmission and reception initialization read tdfe flag in scfsr tdfe = 1? write transmit data to scftdr read tdfe and tend flags in scfsr while they are 1, then clear them to 0 no yes [1] scif status check and transmit data write: read scfsr and check that the tdfe flag is set to 1, then write transmit data to scftdr. read the tdfe and tend flags while they are 1, then clear them to 0. the transition of the tdfe flag from 0 to 1 can also be identified by a txi interrupt. [2] receive error handling: read the orer flag in sclsr to identify any error, perform the appropriate error handling, then clear the orer flag to 0. reception cannot be resumed while the orer flag is set to 1. [3] scif status check and receive data read: [1] amended bit description 13 12 pc6 mode select the function of pin pc6/mii_txd2/ crs . 00: pc06 input/output (port) 01: mii_txd2 output (etherc) 10: setting prohibited 11: crs output (phy) 18.1.6 port c control register h2, l1, and l2 (pccrh2, pccrl1, and pccrl2) ? pccrl2 557 rev. 5.00 mar. 15, 2007 page 781 of 794 rej09b0237-0500 item page revision (see manual for details) 19.6 usage notes 581 added 3. since the hifmd pin is not initially set to function as a general port pin, it must be pulled up or down externally to fix its state. 4. when using a multiplexed pin with a function not selected with its initial valu e (for example, using the pb12/ cs3 pin, the initial func tion of which is pb12, as the cs3 pin), the pin must be pulled up or down externally at least after a reset until its pin function is selected by software to fix its state. figure 22.4 mdio timing and frame structure (read cycle) 626 amended ... ... ter address tu r n around data r2 r1 r0 d15 d14 d1 d0 output on the rising edge latch on the rising edge figure 22.5 mdio timing and frame structure (write cycle) 626 amended ... r2 r1 r0 ... d15 d14 d1 d0 ter address tu r n around data output on the rising edge latch on the rising edge 22.4.1 serial management interface (smi) 626 to 631 added shown below is an example of coding for mdc cycles implemented by software loops. note: co_mdio_dir in figures 22.4 and 22.5 above has a reverse polarity in relation to the mmd bit in the pir register. (example code listing added below.) rev. 5.00 mar. 15, 2007 page 782 of 794 rej09b0237-0500 item page revision (see manual for details) amended, added step description 1 2 3 4 5 6 7 8 9 select tx100 mode. (this operation can be omitted if tx100 full- duplex or tx100 half-duplex mode has been selected by auto- negotiation,) * start register write mode setting. register write mode setting (continued) register write mode setting (continued) register write mode setting (continued) finish register write mode setting. write the setting value. (the initial value of this register is h'81c8. change the setting as necessary.) validate the setting value (always write this value). terminate the register write mode (return to normal mode). ? how to use (example) 661 note: the setting of this register is initialized during the auto-negotiation process or when the phy module is reset (i ncluding a system reset of the lsi). accordingly, when waveform adjustment is to be performed by this register, the above steps must be carried out every time the register is initialized. figure 22.11 example of connection with a pulse transformer (rj45) 662 amended pvcc pvss pvss c3 c4 r2 r1 r3 1 49.9[ohm] 0.01uf/16v 22nf/16v 49.9[ohm] 10[ohm] 2 1 2 1 2 1 2 1 2 8nf/16v figure 25.16 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 0 cycle) 733 amended tc1 tr tcw td1 tde t ad1 t ad1 t ad1 ckio a25 to a0 row address column address figure 25.17 synchronous dram single read bus cycle (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 1 cycle) 734 amended tr w tr tc1 tcw td1 tde tap t ad1 t ad1 t ad1 ckio a25 to a0 row address column address rev. 5.00 mar. 15, 2007 page 783 of 794 rej09b0237-0500 item page revision (see manual for details) figure 25.18 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 0 cycle, wtrp = 1 cycle) 735 amended tc1 tc2 td1 td2 td3 td4 tr tc4 tc4 tde tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address figure 25.19 synchronous dram burst read bus cycle (single read 4) (auto-precharge, cas latency = 2, wtrcd = 1 cycle, wtrp = 0 cycle) 736 amended tc1 tc2 td1 td2 td3 td4 tr tr w t c 3 t c 4 t d e tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address figure 25.20 synchronous dram single write bus cycle (auto-precharge, trwl = 1 cycle) 737 amended tr w l tr tc1 t ad1 t ad1 t ad1 ckio a25 to a0 row address c c ess s column addr c re c s figure 25.21 synchronous dram single write bus cycle (auto-precharge, wtrcd = 2 cycles, trwl = 1 cycle) 738 amended tr w t c 1 tr w l tr tr w t ad1 t ad1 t ad1 ckio a25 to a0 row address c c cl dd c c ress s column add c r s c figure 25.22 synchronous dram burst write bus cycle (single write 4) (auto-precharge, wtrcd = 0 cycle, trwl = 1 cycle) 739 amended tc2 tc3 tc4 trwl tr tc1 tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address figure 25.23 synchronous dram burst write bus cycle (single write 4) (auto-precharge, wtrcd = 1 cycle, trwl = 1 cycle) 740 amended tc2 tc3 tc4 trwl tr t c 1 tr w tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address figure 25.24 synchronous dram burst read bus cycle (single read 4) (bank active mode: act + read commands, cas latency = 2, wtrcd = 0 cycle) 741 amended tc3 tc4 tde tr tc2 td1 td2 td3 td4 tc1 tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address rev. 5.00 mar. 15, 2007 page 784 of 794 rej09b0237-0500 item page revision (see manual for details) figure 25.25 synchronous dram burst read bus cycle (single read 4) (bank active mode: read command, same row address, cas latency = 2, wtrcd = 0 cycle) 742 amended tc2 tc4 tde tc1 tc3 td1 td2 td3 td4 tad1 tad1 tad1 ckio a25 to a0 column address column address column address column address tad1 tad1 figure 25.26 synchronous dram burst read bus cycle (single read 4) (bank active mode: pre + act + read commands, different row addresses, cas latency = 2, wtrcd = 0 cycle) 743 amended tc3 tc4 tde tc2 td1 td2 td3 td4 tc1 tr tpw tp tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 column address column address column address column address row address figure 25.27 synchronous dram burst write bus cycle (single write 4) (bank active mode: act + write commands, wtrcd = 0 cycle, trwl = 0 cycle) 744 amended tc2 tc3 tc4 tr t c 1 tad1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address column address column address column address column address figure 25.28 synchronous dram burst write bus cycle (single write 4) (bank active mode: write command, same row address, wtrcd = 0 cycle, trwl = 0 cycle) 745 amended tc2 tc3 tc4 tnop tc1 tad1 tad1 tad1 tad1 tad1 ckio a25 to a0 column address column address column address column address figure 25.29 synchronous dram burst write bus cycle (single write 4) (bank active mode: pre + act + write commands, different row addresses, wtrcd = 0 cycle, trwl = 0 cycle) 746 amended tc2 tc3 tc4 tr tpw tp tc1 tad1 tad1 tad1 tad1 ckio a25 to a0 row address tad1 tad1 column address column address column address column address figure 25.30 synchronous dram auto-refreshing timing (wtrp = 1 cycle, wtrc = 3 cycles) 747 amended tr c tr c tr r ta p tp tr c t ad1 t ad1 ckio a25 to a0 rev. 5.00 mar. 15, 2007 page 785 of 794 rej09b0237-0500 item page revision (see manual for details) figure 25.31 synchronous dram self-refreshing timing (wtrp = 1 cycle) 748 amended trc trc trc trc tr r ta p tp tr c t ad1 t ad1 ckio a25 to a0 figure 25.32 synchronous dram mode register write timing (wtrp = 1 cycle) 749 amended tr c tr c tr c t m w t d e tr r tr r ta p tp tr c t ad1 t ad1 t ad1 pall ref ref mrs ckio a25 to a0 rev. 5.00 mar. 15, 2007 page 786 of 794 rej09b0237-0500 rev. 5.00 mar. 15, 2007 page 787 of 794 rej09b0237-0500 index numerics 100base-tx receive ............................... 641 100base-tx transmit.............................. 638 100m phase lock loop (pll) .................. 641 100m receive data across the mii........... 644 100m receive input................................. 641 100m transmit data across the mii ......... 638 100m transmit driver .............................. 640 10base-t receive .................................... 646 10base-t transmit................................... 644 10m receive data across the mii............. 646 10m receive input and squelch ............... 646 10m transmit data across the mii ........... 645 10m transmit drivers............................... 645 4b/5b enco ding ...................................... 638 5b/4b deco ding ...................................... 643 a access wait control................................. 154 accessing mii registers .......................... 258 address array............................................ 60 address error exception handling ............. 73 address error sources ............................... 73 address multiplexing.............................. 159 addressing modes..................................... 32 alignment ............................................... 643 arithmetic operation instructions ............. 45 asynchronous mode ............................... 410 auto-negotiation..................................... 648 auto-negotiation disabling ..................... 650 auto-refreshing....................................... 181 auto-request mode ................................. 339 b bank active ............................................. 174 basic timing ............................................ 149 basic timing for i/o card interface.......... 195 basic timing for memory card interface .................................................. 193 baud rate generator ................................. 473 bit rate ..................................................... 394 boundary scan......................................... 620 branch instructions ................................... 48 burst mode.............................................. 350 burst read................................................ 168 burst write............................................... 172 bus state controller (bsc) ...................... 107 byte-selection sram interface .............. 186 c cache ........................................................ 53 cache stru cture.......................................... 53 carrier sense ........................................... 651 cases when exceptions are accepted......... 78 changing clock operating mode.............. 211 changing division ratio........................... 211 changing frequency ................................ 210 changing multiplication ratio ................. 210 clock operating modes ........................... 204 clock pulse generator (cpg) .................. 201 coherency of cache and external memory 59 collision detect ....................................... 651 compare match timer (cmt) ................. 363 connection to phy-lsi.......................... 263 control registers........................................ 25 cpu........................................................... 23 cycle-steal mode..................................... 348 rev. 5.00 mar. 15, 2007 page 788 of 794 rej09b0237-0500 d data array ................................................. 61 data register............................................ 569 data transfer instructions.......................... 43 descrambling.......................................... 642 direct memory access controller (dmac) ................................................. 323 divided areas and cache ........................... 55 dual address mode.................................. 345 e endian/access size and da ta alignment ... 143 equalizer, baseline wander correction and clock and data recovery .......................... 642 etherc receiver....................................... 255 etherc transmitter .................................. 253 ethernet controller (etherc) ................... 233 ethernet controller direct memory access controller (e-dmac) ............................. 265 exception handling ................................... 67 exception handling operations ................. 68 exception handling vector table ............... 69 extension of chip select ( csn ) assertion period...................................................... 156 external request mode ............................ 339 f features of instructions............................. 29 fixed mode ............................................. 341 flow control............................................ 262 g general illegal in structions ....................... 77 general registers (rn)............................... 25 general signals ....................................... 657 h half-duplex and full-duplex.................... 651 host interface (hif)................................ 503 h-udi interrupt ...................................... 619 h-udi reset ............................................ 619 i i/o ports .................................................. 569 illegal slot in structions.............................. 77 immediate data formats............................. 29 initial values of registers........................... 27 input clock to phy module .................... 658 instruction formats .................................... 35 instruction set............................................ 39 intermittent mode.................................... 349 interrupt controller (intc) ....................... 83 interrupt exception handling ..................... 75 interrupt exception handling vector table 100 interrupt priority ....................................... 75 interrupt response time ........................... 104 interrupt sequence................................... 102 interrupt sources ....................................... 74 irq interrupts ........................................... 98 isolate mode............................................ 652 j jabber detection ...................................... 647 l led description...................................... 654 link integrity test.................................... 652 logic operation instructions ..................... 47 loopback operation ................................ 654 rev. 5.00 mar. 15, 2007 page 789 of 794 rej09b0237-0500 m mac interface ........................................ 647 magic packet detection ........................... 261 management signals ....................... 657, 661 manchester decoding .............................. 646 manchester encoding .............................. 645 memory data formats................................ 28 memory-mapped cache ............................ 60 mii.......................................................... 647 mii frame timing .................................... 256 mii signals.............................................. 656 miscellaneous functions ......................... 651 module sta ndby mode............................. 232 multi-buffer frame transmit/receive processing ............................................... 302 multiplexed pin ....................................... 535 n nmi interrupt............................................ 97 normal space interface ........................... 149 nrzi and mlt-3 decoding.................... 642 nrzi and mlt3 encoding ..................... 640 o on-chip peripheral module interrupts....... 99 on-chip peripheral module request mode340 operation by ipg setting ........................ 262 operation mode ...................................... 657 p parallel det ection .................................... 650 pcmcia interface .................................. 191 phy (on-chip phy module)................... 621 phy address ........................................... 657 phy interface (phy-if)......................... 667 phy management control....................... 625 pin assignments .......................................... 8 pin function contro ller (pfc).................. 535 pin functions ............................................... 9 power-down modes......................... 223, 652 power-on reset .......................................... 71 power-on sequence ................................. 184 r read access ............................................... 58 receive data va lid signal......................... 643 receive descriptor 0 (rd0)..................... 295 receive descriptor 1 (rd1)..................... 298 receive descriptor 2 (rd2)..................... 298 receiver errors ........................................ 644 receiving serial data (asynchronous mode) .............................. 419 receiving serial data (synchronous mode)................................ 428 refreshing............................................... 181 register data format.................................. 28 registers apr............................. 251, 683, 703, 712 bamra...................... 586, 683, 704, 712 bamrb ...................... 588, 683, 704, 712 bara ......................... 585, 683, 704, 712 barb.......................... 587, 683, 704, 712 bbra.......................... 586, 683, 705, 712 bbrb.......................... 589, 683, 704, 712 bdmrb ...................... 589, 683, 703, 712 bdrb.......................... 588, 683, 703, 712 betr .......................... 594, 683, 704, 712 brcr.......................... 591, 683, 703, 712 brdr.......................... 595, 683, 705, 712 brsr .......................... 594, 683, 704, 712 ccr1 ............................ 56, 683, 705, 712 cdcr.......................... 248, 682, 701, 711 cefcr........................ 249, 682, 702, 712 chcr.................................................. 328 chcr_0.............................. 676, 684, 706 chcr_1.............................. 676, 685, 706 rev. 5.00 mar. 15, 2007 page 790 of 794 rej09b0237-0500 chcr_2 ............................. 676, 685, 706 chcr_3 ............................. 676, 686, 706 cmcnt.............................................. 366 cmcnt_0.......................... 680, 693, 709 cmcnt_1.......................... 680, 693, 709 cmcor.............................................. 366 cmcor_0.......................... 680, 693, 709 cmcor_1.......................... 680, 693, 709 cmcsr .............................................. 365 cmcsr_0 .......................... 680, 693, 709 cmcsr_1 .......................... 680, 693, 709 cmncr.......................116, 681, 695, 710 cmstr .......................364, 680, 693, 709 cndcr .......................248, 682, 702, 712 cs0bcr ............................. 681, 695, 710 cs0wcr .....................122, 681, 696, 710 cs3bcr ............................. 681, 695, 710 cs3wcr .............124, 132, 681, 696, 710 cs4bcr ............................. 681, 695, 710 cs4wcr .....................125, 681, 696, 710 cs5bbcr........................... 681, 695, 710 cs5bwcr ..........128, 134, 681, 696, 710 cs6bbcr........................... 681, 695, 710 cs6bwcr ..........130, 134, 681, 696, 710 csnbcr ............................................. 117 csnwcr ............................................ 122 dar.................................................... 327 dar_0................................ 676, 684, 706 dar_1................................ 676, 684, 706 dar_2................................ 676, 685, 706 dar_3................................ 676, 686, 706 dmaor ......................333, 676, 686, 706 dmars.............................................. 335 dmars0............................ 677, 688, 707 dmars1............................ 677, 688, 707 dmatcr ........................................... 327 dmatcr_0 ....................... 676, 684, 706 dmatcr_1 ....................... 676, 685, 706 dmatcr_2 ....................... 676, 685, 706 dmatcr_3 ....................... 676, 686, 706 ecmr ......................... 238, 682, 700, 711 ecsipr....................... 243, 682, 700, 711 ecsr .......................... 241, 682, 700, 711 edmr......................... 267, 681, 697, 711 edocr....................... 285, 682, 699, 711 edrrr ....................... 269, 681, 698, 711 edtrr ....................... 268, 681, 697, 711 eesipr ....................... 276, 681, 698, 711 eesr........................... 271, 681, 698, 711 fcftr ........................ 287, 682, 699, 711 fdr............................. 283, 681, 699, 711 frecr........................ 249, 682, 702, 712 frqcr ....................... 206, 678, 689, 708 hifadr ..................... 516, 680, 694, 710 hifbcr...................... 517, 680, 695, 710 hifbicr..................... 519, 680, 694, 710 hifdata................... 517, 680, 694, 710 hifdtr...................... 518, 680, 694, 710 hifeicr..................... 515, 680, 694, 710 hifgsr ...................... 510, 680, 693, 710 hifidx....................... 507, 680, 693, 710 hifiicr...................... 515, 680, 694, 710 hifmcr ..................... 513, 680, 694, 710 hifscr ...................... 510, 680, 693, 710 icr0.............................. 86, 678, 689, 707 ipgr ........................... 251, 682, 703, 712 ipr ........................................................ 95 ipra ................................... 678, 689, 707 iprb ................................... 678, 689, 707 iprc ................................... 677, 688, 707 iprd ................................... 677, 688, 707 ipre.................................... 677, 688, 707 iprf.................................... 677, 688, 707 iprg ................................... 677, 688, 707 irqcr .......................... 87, 678, 689, 707 irqsr........................... 90, 67 8, 689, 707 lccr.......................... 248, 682, 701, 712 mafcr ...................... 250, 682, 702, 712 mahr ........................ 245, 682, 701, 711 malr......................... 245, 682, 701, 711 rev. 5.00 mar. 15, 2007 page 791 of 794 rej09b0237-0500 mclkcr ................... 208, 678, 688, 707 mpr............................ 252, 683, 703, 712 pacrh1..................... 546, 676, 686, 706 pacrh2..................... 546, 676, 686, 706 padrh....................... 569, 676, 686, 706 paiorh ..................... 546, 676, 686, 706 pbcrl1 ..................... 549, 677, 686, 706 pbcrl2 ..................... 549, 677, 686, 706 pbdrl ....................... 571, 676, 686, 706 pbiorl...................... 549, 676, 686, 706 pccrh2 ..................... 553, 677, 687, 707 pccrl1 ..................... 553, 677, 687, 707 pccrl2 ..................... 553, 677, 687, 707 pcdrh....................... 574, 677, 687, 706 pcdrl ....................... 574, 677, 687, 706 pciorh ..................... 553, 677, 687, 706 pciorl...................... 553, 677, 687, 706 pdcrl2 ..................... 559, 677, 687, 707 pddrl ....................... 576, 677, 687, 707 pdiorl...................... 558, 677, 687, 707 pecrh1 ..................... 561, 677, 687, 707 pecrh2 ..................... 561, 677, 688, 707 pecrl1...................... 561, 677, 688, 707 pecrl2...................... 561, 677, 688, 707 pedrh ....................... 579, 677, 687, 707 pedrl ....................... 579, 677, 687, 707 peiorh...................... 561, 677, 687, 707 peiorl ...................... 561, 677, 687, 707 phyifaddrr........... 671, 680, 692, 709 phyifcr ................... 669, 680, 692, 709 phyifsmir2............. 670, 680, 692, 709 phyifsmir3............. 671, 680, 692, 709 phyifsr.................... 672, 680, 693, 709 pir.............................. 244, 682, 700, 711 psr ............................. 247, 682, 701, 711 rbwar ..................... 286, 682, 699, 711 rdfar....................... 286, 682, 700, 711 rdlar....................... 270, 681, 698, 711 register 0 (basic control).................... 633 register 1 (basic status) ...................... 634 register 2 (phy identifier 1) .............. 634 register 3 (phy identifier 2) .............. 635 register 4 (auto negotiation advertisement)..................................... 635 register 5 (auto negotiation link partner ability) . 636 register 6 (auto negotiation expansion)............... 637 rfcr .......................... 250, 682, 702, 712 rflr .......................... 246, 682, 701, 711 rmcr......................... 284, 681, 699, 711 rmfcr....................... 281, 681, 698, 711 rtcnt ....................... 141, 681, 697, 711 rtcor ....................... 142, 681, 697, 711 rtcsr........................ 139, 681, 697, 710 sar..................................................... 327 sar_0................................. 676, 684, 706 sar_1................................. 676, 684, 706 sar_2................................. 676, 685, 706 sar_3................................. 676, 685, 706 scbrr................................................ 394 scbrr_0............................ 678, 689, 708 scbrr_1............................ 679, 690, 708 scbrr_2............................ 679, 690, 708 scfcr ................................................ 401 scfcr_0 ............................ 678, 689, 708 scfcr_1 ............................ 679, 690, 708 scfcr_2 ............................ 679, 691, 709 scfdr................................................ 404 scfdr_0............................ 678, 690, 708 scfdr_1............................ 679, 690, 708 scfdr_2............................ 679, 691, 709 scfrdr ............................................. 378 scfrdr_0 ......................... 678, 689, 708 scfrdr_1 ......................... 679, 690, 708 scfrdr_2 ......................... 679, 691, 709 scfsr ................................................ 386 scfsr_0 ............................ 678, 689, 708 scfsr_1 ............................ 679, 690, 708 scfsr_2 ............................ 679, 690, 708 rev. 5.00 mar. 15, 2007 page 792 of 794 rej09b0237-0500 scftdr............................................. 379 scftdr_0 ......................... 678, 689, 708 scftdr_1 ......................... 679, 690, 708 scftdr_2 ......................... 679, 690, 708 sclsr................................................ 409 sclsr_0............................ 678, 690, 708 sclsr_1............................ 679, 690, 708 sclsr_2............................ 679, 691, 709 scrsr................................................ 378 scscr................................................ 382 scscr_0............................ 678, 689, 708 scscr_1............................ 679, 690, 708 scscr_2............................ 679, 690, 708 scsmr............................................... 379 scsmr_0........................... 678, 689, 708 scsmr_1........................... 679, 690, 708 scsmr_2........................... 679, 690, 708 scsptr.............................................. 405 scsptr_0.......................... 678, 690, 708 scsptr_1.......................... 679, 690, 708 scsptr_2.......................... 679, 691, 709 sctsr................................................ 378 sdbpr ............................................... 608 sdbsr ............................................... 609 sdcr...........................138, 681, 697, 710 sdid............................616, 678, 688, 707 sdir............................608, 678, 688, 707 sicdar ......................469, 679, 691, 709 sictr................................................. 679 sictr................................. 448, 691, 709 sifctr .............................................. 679 sifctr .............................. 463, 691, 709 siier ...........................461, 679, 691, 709 simdr ........................445, 679, 691, 709 sircr .........................454, 680, 692, 709 sirdar ......................468, 679, 691, 709 sirdr .........................452, 679, 692, 709 siscr..........................465, 679, 691, 709 sistr ..........................455, 679, 691, 709 sitcr..........................453, 680, 692, 709 sitdar...................... 466, 679, 691, 709 sitdr......................... 451, 679, 692, 709 spicr ......................... 470, 680, 692, 709 stbcr........................ 225, 678, 689, 708 stbcr2...................... 226, 678, 689, 708 stbcr3...................... 227, 677, 688, 707 stbcr4...................... 228, 678, 688, 707 tbrar ....................... 286, 682, 700, 711 tdfar ....................... 287, 682, 700, 711 tdlar ....................... 270, 681, 698, 711 tftr........................... 282, 681, 699, 711 tlfrcr ..................... 250, 682, 702, 712 tpauser................... 252, 683, 703, 712 trimd ....................... 288, 682, 699, 711 trocr ....................... 247, 682, 701, 711 trscer ..................... 279, 681, 698, 711 tsfrcr ..................... 249, 682, 702, 712 wtcnt ...................... 217, 678, 689, 708 wtcsr....................... 217, 678, 689, 708 relationship between refresh requests and bus cy cles ......................................... 184 reset ................................................. 71, 653 re-starting auto-negotiation.................... 650 risc-type ................................................. 29 round-robin mode .................................. 342 s scif initialization (asynchronous mode) .............................. 414 scif initialization (synchronous mode)................................ 424 scrambling.............................................. 640 sdram direct connection...................... 157 sdram interface ................................... 157 searching cache ........................................ 57 self-refreshing ........................................ 183 serial communication interface with fifo (scif) ..................................................... 373 serial i/o with fifo (siof)................... 441 rev. 5.00 mar. 15, 2007 page 793 of 794 rej09b0237-0500 serial management interface (smi)........ 625 shift instructions....................................... 48 signals relevant to phy-if..................... 657 single address mode ............................... 347 single read .............................................. 172 single write............................................. 174 sleep mode ............................................. 229 smi register ............................................ 632 software standby mode........................... 230 spi mode ................................................ 494 stack states after exception handling ends 79 state transition .......................................... 51 synchronous mode ................................. 423 system control instructions....................... 49 system registers........................................ 26 t tap controller ........................................ 617 the procedures of set up the external phy lsi .......................................................... 674 the procedures of setting up the on-chip phy ........................................................ 673 transmit descriptor 0 (td0) ................... 291 transmit descriptor 1 (td1) ................... 293 transmit descriptor 2 (td2) ................... 293 transmitting and receiving serial data simultaneously (synchronous mode)....... 430 transmitting serial data (asynchronous mode) .............................. 416 transmitting serial data (synchronous mode)................................ 426 trap instructions ....................................... 76 treatment of pins when phy power supply is not used ............................................... 658 types of exception handling and priority . 67 types of exceptions triggered by instructions................................................ 76 types of power-down modes.................. 223 u u memory ................................................. 65 user break controller (ubc)................... 583 user break interrupt .................................. 99 user debugging interface (h-udi) ......... 605 w wait between access cycles .................... 198 watchdog timer (wdt) .......................... 215 write access .............................................. 59 write-back buffer...................................... 59 rev. 5.00 mar. 15, 2007 page 794 of 794 rej09b0237-0500 renesas 32-bit risc microcomputer hardware manual sh7619 group publication date: rev.1.00, mar. 18, 2005 rev.5.00, mar. 15, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 sh7619 group hardware manual |
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